Unified Coverage Report :: Module :: pwrmgr_sec_cm_checker_assert

Module : pwrmgr_sec_cm_checker_assert

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_sec_cm_checker_assert	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.pwrmgr_sec_cm_checker_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : pwrmgr_sec_cm_checker_assert

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	39	1	1	100.00
ALWAYS	40	1	1	100.00
ALWAYS	41	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv' or '../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
39	1	1
40	1	1
41	1	1

---

Cond Coverage for Module : pwrmgr_sec_cm_checker_assert

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       39
 EXPRESSION (((!rst_ni)) || disable_sva)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       40
 EXPRESSION (((!rst_esc_ni)) || disable_sva)
             -------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       41
 EXPRESSION (((!rst_slow_ni)) || disable_sva)
             --------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

---

Assert Coverage for Module : pwrmgr_sec_cm_checker_assert

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	10	10	100.00	10	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	10	10	100.00	10	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
RomAllowActiveState_A	24620852	58363	0	0
RomAllowCheckGoodState_A	24620852	58413	0	0
RomBlockActiveState_A	24620852	26649	0	0
RomBlockCheckGoodState_A	24620852	407203	0	0
RomIntgChkDisFalse_A	24620852	23957492	0	0
RomIntgChkDisTrue_A	24620852	141400	0	0
RstreqChkEsctimeout_A	24620852	4276	0	0
RstreqChkFsmterm_A	24620852	200	0	0
RstreqChkGlbesc_A	24620852	4277	0	0
RstreqChkMainpd_A	24620852	1008454	0	0

RomAllowActiveState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24620852	58363	0	0
T1	2496	2	0	0
T2	33134	39	0	0
T3	44536	101	0	0
T4	4407	10	0	0
T5	1152	3	0	0
T6	2081	1	0	0
T7	15097	2	0	0
T8	659418	1025	0	0
T9	42879	113	0	0
T10	3725	6	0	0

RomAllowCheckGoodState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24620852	58413	0	0
T1	2496	2	0	0
T2	33134	39	0	0
T3	44536	101	0	0
T4	4407	10	0	0
T5	1152	3	0	0
T6	2081	1	0	0
T7	15097	2	0	0
T8	659418	1025	0	0
T9	42879	113	0	0
T10	3725	6	0	0

RomBlockActiveState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24620852	26649	0	0
T15	2016	0	0	0
T20	1603	168	0	0
T21	0	225	0	0
T27	24368	7	0	0
T28	32462	0	0	0
T29	22042	0	0	0
T30	60980	0	0	0
T31	4433	0	0	0
T35	18901	9	0	0
T73	0	13	0	0
T77	858	0	0	0
T116	3955	0	0	0
T126	0	329	0	0
T127	0	1205	0	0
T128	0	25	0	0
T129	0	4	0	0
T130	0	25	0	0

RomBlockCheckGoodState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24620852	407203	0	0
T8	659418	3600	0	0
T9	42879	251	0	0
T10	3725	0	0	0
T13	297410	2471	0	0
T14	3953	0	0	0
T18	3154	0	0	0
T20	0	8	0	0
T25	1384	0	0	0
T26	2766	0	0	0
T27	24368	1270	0	0
T28	32462	734	0	0
T29	0	1317	0	0
T30	0	4012	0	0
T35	0	1295	0	0
T117	0	391	0	0

RomIntgChkDisFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24620852	23957492	0	0
T1	2496	2435	0	0
T2	33134	32748	0	0
T3	44536	38338	0	0
T4	4407	4355	0	0
T5	1152	1070	0	0
T6	2081	2013	0	0
T7	15097	15046	0	0
T8	659418	650896	0	0
T9	42879	41893	0	0
T10	3725	3284	0	0

RomIntgChkDisTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24620852	141400	0	0
T15	2016	0	0	0
T20	1603	928	0	0
T21	1492	35	0	0
T22	0	55	0	0
T30	60980	0	0	0
T31	4433	0	0	0
T35	18901	0	0	0
T45	2655	0	0	0
T73	0	584	0	0
T74	0	650	0	0
T75	0	580	0	0
T77	858	0	0	0
T117	18063	0	0	0
T126	0	273	0	0
T127	0	786	0	0
T128	0	323	0	0
T129	0	243	0	0
T131	1869	0	0	0

RstreqChkEsctimeout_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24620852	4276	0	0
T3	44536	20	0	0
T4	4407	0	0	0
T5	1152	0	0	0
T6	2081	0	0	0
T7	15097	1	0	0
T8	659418	71	0	0
T9	42879	14	0	0
T10	3725	0	0	0
T13	0	87	0	0
T14	3953	0	0	0
T18	0	6	0	0
T20	0	4	0	0
T25	1384	0	0	0
T26	0	5	0	0
T28	0	7	0	0
T31	0	6	0	0

RstreqChkFsmterm_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24620852	200	0	0
T3	44536	40	0	0
T4	4407	0	0	0
T5	1152	0	0	0
T6	2081	0	0	0
T7	15097	0	0	0
T8	659418	0	0	0
T9	42879	0	0	0
T10	3725	0	0	0
T14	3953	0	0	0
T16	0	40	0	0
T17	0	40	0	0
T23	0	40	0	0
T24	0	40	0	0
T25	1384	0	0	0

RstreqChkGlbesc_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24620852	4277	0	0
T3	44536	20	0	0
T4	4407	0	0	0
T5	1152	0	0	0
T6	2081	0	0	0
T7	15097	1	0	0
T8	659418	71	0	0
T9	42879	14	0	0
T10	3725	0	0	0
T13	0	87	0	0
T14	3953	0	0	0
T18	0	6	0	0
T20	0	4	0	0
T25	1384	0	0	0
T26	0	5	0	0
T28	0	7	0	0
T31	0	6	0	0

RstreqChkMainpd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24620852	1008454	0	0
T8	659418	22624	0	0
T9	42879	2573	0	0
T10	3725	27	0	0
T13	297410	10555	0	0
T14	3953	22	0	0
T18	3154	100	0	0
T25	1384	0	0	0
T26	2766	179	0	0
T27	24368	1627	0	0
T28	32462	1143	0	0
T29	0	1678	0	0