Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.95 98.23 96.58 99.44 96.00 96.37 100.00 99.02


Total test records in report: 1109
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T50 /workspace/coverage/cover_reg_top/9.pwrmgr_csr_mem_rw_with_rand_reset.3085122781 Mar 28 12:43:01 PM PDT 24 Mar 28 12:43:02 PM PDT 24 106082842 ps
T136 /workspace/coverage/cover_reg_top/0.pwrmgr_tl_intg_err.2929959607 Mar 28 12:43:03 PM PDT 24 Mar 28 12:43:04 PM PDT 24 183177877 ps
T1014 /workspace/coverage/cover_reg_top/15.pwrmgr_tl_errors.47376157 Mar 28 12:43:13 PM PDT 24 Mar 28 12:43:15 PM PDT 24 71252174 ps
T1015 /workspace/coverage/cover_reg_top/7.pwrmgr_tl_errors.827547429 Mar 28 12:43:12 PM PDT 24 Mar 28 12:43:13 PM PDT 24 97954169 ps
T1016 /workspace/coverage/cover_reg_top/38.pwrmgr_intr_test.4085343746 Mar 28 12:43:25 PM PDT 24 Mar 28 12:43:25 PM PDT 24 23815494 ps
T1017 /workspace/coverage/cover_reg_top/4.pwrmgr_intr_test.2778559399 Mar 28 12:43:16 PM PDT 24 Mar 28 12:43:17 PM PDT 24 38982755 ps
T1018 /workspace/coverage/cover_reg_top/3.pwrmgr_same_csr_outstanding.1920623599 Mar 28 12:43:09 PM PDT 24 Mar 28 12:43:10 PM PDT 24 98365745 ps
T1019 /workspace/coverage/cover_reg_top/6.pwrmgr_tl_intg_err.1990364383 Mar 28 12:43:17 PM PDT 24 Mar 28 12:43:18 PM PDT 24 237815196 ps
T1020 /workspace/coverage/cover_reg_top/24.pwrmgr_intr_test.3939793531 Mar 28 12:43:05 PM PDT 24 Mar 28 12:43:06 PM PDT 24 44273331 ps
T1021 /workspace/coverage/cover_reg_top/19.pwrmgr_same_csr_outstanding.80936596 Mar 28 12:43:09 PM PDT 24 Mar 28 12:43:10 PM PDT 24 54148502 ps
T137 /workspace/coverage/cover_reg_top/5.pwrmgr_tl_intg_err.2195998451 Mar 28 12:43:13 PM PDT 24 Mar 28 12:43:14 PM PDT 24 285414437 ps
T1022 /workspace/coverage/cover_reg_top/26.pwrmgr_intr_test.1408726555 Mar 28 12:43:10 PM PDT 24 Mar 28 12:43:11 PM PDT 24 34147946 ps
T1023 /workspace/coverage/cover_reg_top/9.pwrmgr_tl_errors.3206672085 Mar 28 12:43:04 PM PDT 24 Mar 28 12:43:07 PM PDT 24 204335666 ps
T1024 /workspace/coverage/cover_reg_top/12.pwrmgr_intr_test.3182402857 Mar 28 12:43:03 PM PDT 24 Mar 28 12:43:04 PM PDT 24 43910914 ps
T1025 /workspace/coverage/cover_reg_top/35.pwrmgr_intr_test.534134007 Mar 28 12:43:24 PM PDT 24 Mar 28 12:43:25 PM PDT 24 17932724 ps
T1026 /workspace/coverage/cover_reg_top/6.pwrmgr_same_csr_outstanding.2651504437 Mar 28 12:43:23 PM PDT 24 Mar 28 12:43:24 PM PDT 24 73486673 ps
T1027 /workspace/coverage/cover_reg_top/16.pwrmgr_intr_test.3342538688 Mar 28 12:43:02 PM PDT 24 Mar 28 12:43:03 PM PDT 24 53081926 ps
T1028 /workspace/coverage/cover_reg_top/37.pwrmgr_intr_test.3804134361 Mar 28 12:43:27 PM PDT 24 Mar 28 12:43:28 PM PDT 24 19358102 ps
T1029 /workspace/coverage/cover_reg_top/8.pwrmgr_tl_intg_err.219440863 Mar 28 12:42:58 PM PDT 24 Mar 28 12:42:59 PM PDT 24 100940370 ps
T87 /workspace/coverage/cover_reg_top/13.pwrmgr_csr_rw.3110158615 Mar 28 12:43:23 PM PDT 24 Mar 28 12:43:24 PM PDT 24 33012431 ps
T88 /workspace/coverage/cover_reg_top/1.pwrmgr_csr_hw_reset.2501933238 Mar 28 12:43:05 PM PDT 24 Mar 28 12:43:06 PM PDT 24 38970566 ps
T1030 /workspace/coverage/cover_reg_top/5.pwrmgr_csr_mem_rw_with_rand_reset.2660008207 Mar 28 12:43:06 PM PDT 24 Mar 28 12:43:07 PM PDT 24 44938796 ps
T1031 /workspace/coverage/cover_reg_top/0.pwrmgr_same_csr_outstanding.665575542 Mar 28 12:43:09 PM PDT 24 Mar 28 12:43:10 PM PDT 24 45776863 ps
T1032 /workspace/coverage/cover_reg_top/5.pwrmgr_tl_errors.3037827343 Mar 28 12:43:10 PM PDT 24 Mar 28 12:43:13 PM PDT 24 42606531 ps
T1033 /workspace/coverage/cover_reg_top/0.pwrmgr_csr_mem_rw_with_rand_reset.2395546601 Mar 28 12:43:04 PM PDT 24 Mar 28 12:43:04 PM PDT 24 56019666 ps
T133 /workspace/coverage/cover_reg_top/1.pwrmgr_tl_intg_err.354518816 Mar 28 12:43:08 PM PDT 24 Mar 28 12:43:10 PM PDT 24 213246534 ps
T1034 /workspace/coverage/cover_reg_top/17.pwrmgr_csr_mem_rw_with_rand_reset.1922567271 Mar 28 12:43:07 PM PDT 24 Mar 28 12:43:09 PM PDT 24 53128433 ps
T1035 /workspace/coverage/cover_reg_top/46.pwrmgr_intr_test.460719079 Mar 28 12:43:28 PM PDT 24 Mar 28 12:43:29 PM PDT 24 20951649 ps
T1036 /workspace/coverage/cover_reg_top/18.pwrmgr_csr_rw.2461628980 Mar 28 12:43:03 PM PDT 24 Mar 28 12:43:04 PM PDT 24 62021761 ps
T1037 /workspace/coverage/cover_reg_top/45.pwrmgr_intr_test.1223999471 Mar 28 12:43:24 PM PDT 24 Mar 28 12:43:25 PM PDT 24 19785848 ps
T1038 /workspace/coverage/cover_reg_top/3.pwrmgr_intr_test.1957163562 Mar 28 12:43:15 PM PDT 24 Mar 28 12:43:16 PM PDT 24 19393767 ps
T1039 /workspace/coverage/cover_reg_top/2.pwrmgr_tl_errors.2681741892 Mar 28 12:42:57 PM PDT 24 Mar 28 12:43:00 PM PDT 24 46661239 ps
T1040 /workspace/coverage/cover_reg_top/29.pwrmgr_intr_test.2989911167 Mar 28 12:43:10 PM PDT 24 Mar 28 12:43:11 PM PDT 24 48363174 ps
T1041 /workspace/coverage/cover_reg_top/4.pwrmgr_same_csr_outstanding.2426246831 Mar 28 12:43:09 PM PDT 24 Mar 28 12:43:10 PM PDT 24 25042961 ps
T1042 /workspace/coverage/cover_reg_top/8.pwrmgr_same_csr_outstanding.3488734373 Mar 28 12:43:07 PM PDT 24 Mar 28 12:43:08 PM PDT 24 22151817 ps
T1043 /workspace/coverage/cover_reg_top/16.pwrmgr_same_csr_outstanding.908453078 Mar 28 12:43:13 PM PDT 24 Mar 28 12:43:14 PM PDT 24 46576758 ps
T1044 /workspace/coverage/cover_reg_top/14.pwrmgr_same_csr_outstanding.660927006 Mar 28 12:43:07 PM PDT 24 Mar 28 12:43:08 PM PDT 24 33154399 ps
T1045 /workspace/coverage/cover_reg_top/4.pwrmgr_tl_errors.1754227309 Mar 28 12:43:04 PM PDT 24 Mar 28 12:43:06 PM PDT 24 91409162 ps
T1046 /workspace/coverage/cover_reg_top/12.pwrmgr_same_csr_outstanding.3237122540 Mar 28 12:43:10 PM PDT 24 Mar 28 12:43:11 PM PDT 24 84675704 ps
T1047 /workspace/coverage/cover_reg_top/10.pwrmgr_tl_errors.3602990965 Mar 28 12:43:05 PM PDT 24 Mar 28 12:43:07 PM PDT 24 127945031 ps
T1048 /workspace/coverage/cover_reg_top/31.pwrmgr_intr_test.1524853185 Mar 28 12:43:24 PM PDT 24 Mar 28 12:43:25 PM PDT 24 68079396 ps
T1049 /workspace/coverage/cover_reg_top/8.pwrmgr_intr_test.941671581 Mar 28 12:43:12 PM PDT 24 Mar 28 12:43:13 PM PDT 24 35598343 ps
T1050 /workspace/coverage/cover_reg_top/18.pwrmgr_intr_test.361472860 Mar 28 12:43:07 PM PDT 24 Mar 28 12:43:08 PM PDT 24 22145526 ps
T1051 /workspace/coverage/cover_reg_top/15.pwrmgr_intr_test.2842590816 Mar 28 12:43:09 PM PDT 24 Mar 28 12:43:10 PM PDT 24 39160613 ps
T1052 /workspace/coverage/cover_reg_top/36.pwrmgr_intr_test.3767145582 Mar 28 12:43:22 PM PDT 24 Mar 28 12:43:23 PM PDT 24 30689408 ps
T1053 /workspace/coverage/cover_reg_top/28.pwrmgr_intr_test.2551921177 Mar 28 12:43:14 PM PDT 24 Mar 28 12:43:15 PM PDT 24 20475518 ps
T1054 /workspace/coverage/cover_reg_top/42.pwrmgr_intr_test.1669933755 Mar 28 12:43:22 PM PDT 24 Mar 28 12:43:23 PM PDT 24 42800310 ps
T1055 /workspace/coverage/cover_reg_top/5.pwrmgr_same_csr_outstanding.2844667326 Mar 28 12:43:10 PM PDT 24 Mar 28 12:43:11 PM PDT 24 56884701 ps
T1056 /workspace/coverage/cover_reg_top/8.pwrmgr_csr_mem_rw_with_rand_reset.109628130 Mar 28 12:43:07 PM PDT 24 Mar 28 12:43:08 PM PDT 24 87945537 ps
T1057 /workspace/coverage/cover_reg_top/19.pwrmgr_csr_rw.334232593 Mar 28 12:43:09 PM PDT 24 Mar 28 12:43:10 PM PDT 24 43297956 ps
T1058 /workspace/coverage/cover_reg_top/7.pwrmgr_csr_mem_rw_with_rand_reset.3517895696 Mar 28 12:43:22 PM PDT 24 Mar 28 12:43:23 PM PDT 24 237159306 ps
T1059 /workspace/coverage/cover_reg_top/15.pwrmgr_csr_mem_rw_with_rand_reset.706295475 Mar 28 12:43:13 PM PDT 24 Mar 28 12:43:14 PM PDT 24 36034107 ps
T1060 /workspace/coverage/cover_reg_top/4.pwrmgr_csr_aliasing.448212266 Mar 28 12:43:10 PM PDT 24 Mar 28 12:43:11 PM PDT 24 156587739 ps
T1061 /workspace/coverage/cover_reg_top/10.pwrmgr_same_csr_outstanding.1733440603 Mar 28 12:43:07 PM PDT 24 Mar 28 12:43:07 PM PDT 24 227134000 ps
T1062 /workspace/coverage/cover_reg_top/2.pwrmgr_csr_hw_reset.1310243671 Mar 28 12:43:10 PM PDT 24 Mar 28 12:43:11 PM PDT 24 65609613 ps
T89 /workspace/coverage/cover_reg_top/17.pwrmgr_csr_rw.1394510391 Mar 28 12:43:07 PM PDT 24 Mar 28 12:43:08 PM PDT 24 16865185 ps
T1063 /workspace/coverage/cover_reg_top/10.pwrmgr_tl_intg_err.3070939311 Mar 28 12:43:07 PM PDT 24 Mar 28 12:43:08 PM PDT 24 723792704 ps
T1064 /workspace/coverage/cover_reg_top/4.pwrmgr_csr_rw.549743251 Mar 28 12:43:11 PM PDT 24 Mar 28 12:43:12 PM PDT 24 50038822 ps
T1065 /workspace/coverage/cover_reg_top/48.pwrmgr_intr_test.3236518842 Mar 28 12:43:27 PM PDT 24 Mar 28 12:43:28 PM PDT 24 22795713 ps
T1066 /workspace/coverage/cover_reg_top/6.pwrmgr_csr_mem_rw_with_rand_reset.3120994259 Mar 28 12:43:13 PM PDT 24 Mar 28 12:43:15 PM PDT 24 53363088 ps
T1067 /workspace/coverage/cover_reg_top/12.pwrmgr_csr_mem_rw_with_rand_reset.266471854 Mar 28 12:43:20 PM PDT 24 Mar 28 12:43:21 PM PDT 24 66723551 ps
T1068 /workspace/coverage/cover_reg_top/13.pwrmgr_csr_mem_rw_with_rand_reset.3570915547 Mar 28 12:42:57 PM PDT 24 Mar 28 12:42:58 PM PDT 24 58415114 ps
T1069 /workspace/coverage/cover_reg_top/7.pwrmgr_csr_rw.3900227111 Mar 28 12:43:02 PM PDT 24 Mar 28 12:43:03 PM PDT 24 20610647 ps
T1070 /workspace/coverage/cover_reg_top/0.pwrmgr_intr_test.62100683 Mar 28 12:43:04 PM PDT 24 Mar 28 12:43:04 PM PDT 24 42427653 ps
T1071 /workspace/coverage/cover_reg_top/9.pwrmgr_tl_intg_err.3117393267 Mar 28 12:43:16 PM PDT 24 Mar 28 12:43:17 PM PDT 24 251637197 ps
T1072 /workspace/coverage/cover_reg_top/11.pwrmgr_tl_intg_err.3542984188 Mar 28 12:43:15 PM PDT 24 Mar 28 12:43:17 PM PDT 24 221782287 ps
T1073 /workspace/coverage/cover_reg_top/33.pwrmgr_intr_test.3886657886 Mar 28 12:43:25 PM PDT 24 Mar 28 12:43:26 PM PDT 24 48772442 ps
T1074 /workspace/coverage/cover_reg_top/44.pwrmgr_intr_test.738013230 Mar 28 12:43:26 PM PDT 24 Mar 28 12:43:27 PM PDT 24 24246417 ps
T1075 /workspace/coverage/cover_reg_top/15.pwrmgr_same_csr_outstanding.171852797 Mar 28 12:43:22 PM PDT 24 Mar 28 12:43:23 PM PDT 24 28398943 ps
T90 /workspace/coverage/cover_reg_top/8.pwrmgr_csr_rw.4254488206 Mar 28 12:42:58 PM PDT 24 Mar 28 12:42:59 PM PDT 24 50370495 ps
T1076 /workspace/coverage/cover_reg_top/10.pwrmgr_intr_test.3645535145 Mar 28 12:43:07 PM PDT 24 Mar 28 12:43:07 PM PDT 24 23177519 ps
T1077 /workspace/coverage/cover_reg_top/2.pwrmgr_same_csr_outstanding.70815928 Mar 28 12:43:08 PM PDT 24 Mar 28 12:43:09 PM PDT 24 30615026 ps
T1078 /workspace/coverage/cover_reg_top/0.pwrmgr_csr_rw.655521541 Mar 28 12:43:09 PM PDT 24 Mar 28 12:43:11 PM PDT 24 23295889 ps
T1079 /workspace/coverage/cover_reg_top/20.pwrmgr_intr_test.2563932647 Mar 28 12:43:18 PM PDT 24 Mar 28 12:43:18 PM PDT 24 42821542 ps
T1080 /workspace/coverage/cover_reg_top/1.pwrmgr_same_csr_outstanding.2436764243 Mar 28 12:43:09 PM PDT 24 Mar 28 12:43:10 PM PDT 24 154644864 ps
T1081 /workspace/coverage/cover_reg_top/14.pwrmgr_csr_mem_rw_with_rand_reset.740045555 Mar 28 12:43:13 PM PDT 24 Mar 28 12:43:13 PM PDT 24 53638018 ps
T1082 /workspace/coverage/cover_reg_top/18.pwrmgr_csr_mem_rw_with_rand_reset.2189486314 Mar 28 12:43:02 PM PDT 24 Mar 28 12:43:03 PM PDT 24 61742068 ps
T1083 /workspace/coverage/cover_reg_top/34.pwrmgr_intr_test.572570878 Mar 28 12:43:27 PM PDT 24 Mar 28 12:43:27 PM PDT 24 24426072 ps
T1084 /workspace/coverage/cover_reg_top/14.pwrmgr_tl_errors.3123430439 Mar 28 12:43:13 PM PDT 24 Mar 28 12:43:15 PM PDT 24 209893971 ps
T1085 /workspace/coverage/cover_reg_top/12.pwrmgr_csr_rw.2562287347 Mar 28 12:43:04 PM PDT 24 Mar 28 12:43:05 PM PDT 24 46348206 ps
T1086 /workspace/coverage/cover_reg_top/21.pwrmgr_intr_test.2999492022 Mar 28 12:43:01 PM PDT 24 Mar 28 12:43:01 PM PDT 24 46226145 ps
T1087 /workspace/coverage/cover_reg_top/22.pwrmgr_intr_test.4214414239 Mar 28 12:43:09 PM PDT 24 Mar 28 12:43:10 PM PDT 24 93976146 ps
T95 /workspace/coverage/cover_reg_top/14.pwrmgr_csr_rw.1023579778 Mar 28 12:43:14 PM PDT 24 Mar 28 12:43:15 PM PDT 24 19223878 ps
T1088 /workspace/coverage/cover_reg_top/8.pwrmgr_tl_errors.2906176399 Mar 28 12:43:17 PM PDT 24 Mar 28 12:43:20 PM PDT 24 466648001 ps
T1089 /workspace/coverage/cover_reg_top/40.pwrmgr_intr_test.964864615 Mar 28 12:43:26 PM PDT 24 Mar 28 12:43:27 PM PDT 24 17800885 ps
T1090 /workspace/coverage/cover_reg_top/0.pwrmgr_tl_errors.1011794160 Mar 28 12:43:05 PM PDT 24 Mar 28 12:43:07 PM PDT 24 48739280 ps
T1091 /workspace/coverage/cover_reg_top/4.pwrmgr_csr_hw_reset.3506908867 Mar 28 12:43:10 PM PDT 24 Mar 28 12:43:11 PM PDT 24 50146990 ps
T1092 /workspace/coverage/cover_reg_top/17.pwrmgr_same_csr_outstanding.1013658804 Mar 28 12:43:09 PM PDT 24 Mar 28 12:43:10 PM PDT 24 86605643 ps
T1093 /workspace/coverage/cover_reg_top/7.pwrmgr_same_csr_outstanding.3564491063 Mar 28 12:43:02 PM PDT 24 Mar 28 12:43:03 PM PDT 24 90110996 ps
T1094 /workspace/coverage/cover_reg_top/9.pwrmgr_intr_test.1275952731 Mar 28 12:43:08 PM PDT 24 Mar 28 12:43:09 PM PDT 24 19103104 ps
T1095 /workspace/coverage/cover_reg_top/17.pwrmgr_intr_test.2317758892 Mar 28 12:43:07 PM PDT 24 Mar 28 12:43:08 PM PDT 24 22770601 ps
T1096 /workspace/coverage/cover_reg_top/2.pwrmgr_intr_test.3095432112 Mar 28 12:43:08 PM PDT 24 Mar 28 12:43:09 PM PDT 24 40537024 ps
T1097 /workspace/coverage/cover_reg_top/17.pwrmgr_tl_errors.3876048211 Mar 28 12:43:07 PM PDT 24 Mar 28 12:43:08 PM PDT 24 263116494 ps
T91 /workspace/coverage/cover_reg_top/15.pwrmgr_csr_rw.1737434146 Mar 28 12:43:09 PM PDT 24 Mar 28 12:43:10 PM PDT 24 24203233 ps
T92 /workspace/coverage/cover_reg_top/3.pwrmgr_csr_rw.996719594 Mar 28 12:43:03 PM PDT 24 Mar 28 12:43:04 PM PDT 24 21907417 ps
T1098 /workspace/coverage/cover_reg_top/0.pwrmgr_csr_aliasing.1828297880 Mar 28 12:43:09 PM PDT 24 Mar 28 12:43:11 PM PDT 24 145705604 ps
T1099 /workspace/coverage/cover_reg_top/6.pwrmgr_tl_errors.3156307098 Mar 28 12:43:07 PM PDT 24 Mar 28 12:43:08 PM PDT 24 168716626 ps
T1100 /workspace/coverage/cover_reg_top/4.pwrmgr_csr_bit_bash.1022482935 Mar 28 12:43:18 PM PDT 24 Mar 28 12:43:20 PM PDT 24 289664089 ps
T1101 /workspace/coverage/cover_reg_top/18.pwrmgr_same_csr_outstanding.1871452938 Mar 28 12:43:04 PM PDT 24 Mar 28 12:43:05 PM PDT 24 49480912 ps
T1102 /workspace/coverage/cover_reg_top/11.pwrmgr_intr_test.2364960403 Mar 28 12:43:09 PM PDT 24 Mar 28 12:43:10 PM PDT 24 20849828 ps
T1103 /workspace/coverage/cover_reg_top/19.pwrmgr_csr_mem_rw_with_rand_reset.1441875738 Mar 28 12:42:56 PM PDT 24 Mar 28 12:42:56 PM PDT 24 74444917 ps
T93 /workspace/coverage/cover_reg_top/11.pwrmgr_csr_rw.236095029 Mar 28 12:43:17 PM PDT 24 Mar 28 12:43:18 PM PDT 24 24995823 ps
T1104 /workspace/coverage/cover_reg_top/0.pwrmgr_csr_bit_bash.2819390998 Mar 28 12:43:03 PM PDT 24 Mar 28 12:43:05 PM PDT 24 86761993 ps
T1105 /workspace/coverage/cover_reg_top/18.pwrmgr_tl_intg_err.4145997672 Mar 28 12:43:02 PM PDT 24 Mar 28 12:43:04 PM PDT 24 191305572 ps
T1106 /workspace/coverage/cover_reg_top/7.pwrmgr_intr_test.2893009941 Mar 28 12:43:17 PM PDT 24 Mar 28 12:43:18 PM PDT 24 36106031 ps
T1107 /workspace/coverage/cover_reg_top/19.pwrmgr_tl_errors.4029714160 Mar 28 12:43:09 PM PDT 24 Mar 28 12:43:12 PM PDT 24 437901817 ps
T94 /workspace/coverage/cover_reg_top/2.pwrmgr_csr_aliasing.2723920212 Mar 28 12:43:09 PM PDT 24 Mar 28 12:43:10 PM PDT 24 19673936 ps
T1108 /workspace/coverage/cover_reg_top/5.pwrmgr_intr_test.4101592319 Mar 28 12:43:06 PM PDT 24 Mar 28 12:43:07 PM PDT 24 72643454 ps
T1109 /workspace/coverage/cover_reg_top/16.pwrmgr_tl_errors.3617567010 Mar 28 12:43:09 PM PDT 24 Mar 28 12:43:12 PM PDT 24 97387317 ps

Test location /workspace/coverage/default/46.pwrmgr_stress_all_with_rand_reset.3483319085
Short name T8
Test name
Test status
Simulation time 9735185357 ps
CPU time 28.89 seconds
Started Mar 28 01:26:24 PM PDT 24
Finished Mar 28 01:26:53 PM PDT 24
Peak memory 200876 kb
Host smart-402f9b67-343f-422f-b0db-3ff09e25ed54
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3483319085 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 46.pwrmgr_stress_all_with_rand_reset.3483319085
Directory /workspace/46.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.pwrmgr_reset_invalid.1200648652
Short name T18
Test name
Test status
Simulation time 160316865 ps
CPU time 0.8 seconds
Started Mar 28 01:24:47 PM PDT 24
Finished Mar 28 01:24:48 PM PDT 24
Peak memory 200600 kb
Host smart-72f106c0-293b-40b6-aa90-6024d9d33a7f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1200648652 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_reset_invalid.1200648652
Directory /workspace/25.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/1.pwrmgr_sec_cm.3484990405
Short name T24
Test name
Test status
Simulation time 646031767 ps
CPU time 2.26 seconds
Started Mar 28 01:21:54 PM PDT 24
Finished Mar 28 01:21:57 PM PDT 24
Peak memory 217076 kb
Host smart-64526b03-2c99-47cb-a191-9a5c03799bed
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3484990405 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_sec_cm.3484990405
Directory /workspace/1.pwrmgr_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/14.pwrmgr_tl_intg_err.3774988140
Short name T37
Test name
Test status
Simulation time 113453685 ps
CPU time 1.17 seconds
Started Mar 28 12:43:06 PM PDT 24
Finished Mar 28 12:43:08 PM PDT 24
Peak memory 199912 kb
Host smart-0f913b99-4ed5-4ef7-9ba8-97c4b420ef5d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3774988140 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.pwrmgr_tl_intg_er
r.3774988140
Directory /workspace/14.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/default/14.pwrmgr_lowpower_invalid.1069920779
Short name T33
Test name
Test status
Simulation time 76373075 ps
CPU time 0.69 seconds
Started Mar 28 01:23:41 PM PDT 24
Finished Mar 28 01:23:42 PM PDT 24
Peak memory 200660 kb
Host smart-20c70ca1-b43c-46ad-b276-492ce1d19809
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1069920779 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_lowpower_inval
id.1069920779
Directory /workspace/14.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/23.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2088822500
Short name T73
Test name
Test status
Simulation time 1009519009 ps
CPU time 1.99 seconds
Started Mar 28 01:24:29 PM PDT 24
Finished Mar 28 01:24:31 PM PDT 24
Peak memory 200424 kb
Host smart-45163269-5030-41ae-9541-cce3dfa662d0
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2088822500 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 23.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2088822500
Directory /workspace/23.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/cover_reg_top/2.pwrmgr_csr_mem_rw_with_rand_reset.1092483560
Short name T44
Test name
Test status
Simulation time 143997259 ps
CPU time 1.66 seconds
Started Mar 28 12:43:10 PM PDT 24
Finished Mar 28 12:43:12 PM PDT 24
Peak memory 196964 kb
Host smart-3ec98102-1783-475e-b768-fe4017657f5b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1092483560 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 2.pwrmgr_csr_mem_rw_with_rand_reset.1092483560
Directory /workspace/2.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/49.pwrmgr_intr_test.1585139251
Short name T140
Test name
Test status
Simulation time 48569444 ps
CPU time 0.6 seconds
Started Mar 28 12:43:22 PM PDT 24
Finished Mar 28 12:43:23 PM PDT 24
Peak memory 194692 kb
Host smart-114d2fbc-7381-4cc0-bf6c-e4e1f1fd0ce1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1585139251 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.pwrmgr_intr_test.1585139251
Directory /workspace/49.pwrmgr_intr_test/latest

Test location /workspace/coverage/default/32.pwrmgr_sec_cm_ctrl_config_regwen.2310127269
Short name T46
Test name
Test status
Simulation time 367135612 ps
CPU time 1.07 seconds
Started Mar 28 01:25:35 PM PDT 24
Finished Mar 28 01:25:36 PM PDT 24
Peak memory 200240 kb
Host smart-13c597d3-561e-436a-a93f-b36abbffd4dd
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2310127269 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_sec_
cm_ctrl_config_regwen.2310127269
Directory /workspace/32.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/25.pwrmgr_escalation_timeout.2532790222
Short name T7
Test name
Test status
Simulation time 946221737 ps
CPU time 0.99 seconds
Started Mar 28 01:24:49 PM PDT 24
Finished Mar 28 01:24:50 PM PDT 24
Peak memory 197624 kb
Host smart-df7b6e24-be09-4d2f-ac2c-9ec9f2d54f2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2532790222 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_escalation_timeout.2532790222
Directory /workspace/25.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/cover_reg_top/2.pwrmgr_csr_aliasing.2723920212
Short name T94
Test name
Test status
Simulation time 19673936 ps
CPU time 0.81 seconds
Started Mar 28 12:43:09 PM PDT 24
Finished Mar 28 12:43:10 PM PDT 24
Peak memory 197100 kb
Host smart-707fc84c-3eef-4ee3-9fb3-34cdf108e11a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2723920212 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.pwrmgr_csr_aliasing.2
723920212
Directory /workspace/2.pwrmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.pwrmgr_tl_intg_err.1387403550
Short name T132
Test name
Test status
Simulation time 184455226 ps
CPU time 1.63 seconds
Started Mar 28 12:43:18 PM PDT 24
Finished Mar 28 12:43:20 PM PDT 24
Peak memory 194848 kb
Host smart-28eda6c1-a506-4b5a-93af-ef56fbfc1201
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1387403550 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.pwrmgr_tl_intg_err
.1387403550
Directory /workspace/3.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/default/11.pwrmgr_stress_all_with_rand_reset.1488619396
Short name T51
Test name
Test status
Simulation time 3491905129 ps
CPU time 11.89 seconds
Started Mar 28 01:23:39 PM PDT 24
Finished Mar 28 01:23:51 PM PDT 24
Peak memory 200860 kb
Host smart-528142ba-ab64-42df-92eb-55c96af34c93
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1488619396 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 11.pwrmgr_stress_all_with_rand_reset.1488619396
Directory /workspace/11.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.pwrmgr_disable_rom_integrity_check.2721932341
Short name T22
Test name
Test status
Simulation time 237439034 ps
CPU time 0.67 seconds
Started Mar 28 01:24:29 PM PDT 24
Finished Mar 28 01:24:30 PM PDT 24
Peak memory 198520 kb
Host smart-ee63db21-1e4f-4431-a699-892ac20d730f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2721932341 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_dis
able_rom_integrity_check.2721932341
Directory /workspace/23.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/0.pwrmgr_stress_all.3209405810
Short name T9
Test name
Test status
Simulation time 589855155 ps
CPU time 3.19 seconds
Started Mar 28 01:21:46 PM PDT 24
Finished Mar 28 01:21:49 PM PDT 24
Peak memory 200564 kb
Host smart-44aa8ffe-c9d8-452a-833f-176219d44571
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3209405810 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_stress_all.3209405810
Directory /workspace/0.pwrmgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/9.pwrmgr_tl_intg_err.3117393267
Short name T1071
Test name
Test status
Simulation time 251637197 ps
CPU time 1.03 seconds
Started Mar 28 12:43:16 PM PDT 24
Finished Mar 28 12:43:17 PM PDT 24
Peak memory 194804 kb
Host smart-0ab8ebc0-8dcb-4822-8d90-a77761394b4f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3117393267 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.pwrmgr_tl_intg_err
.3117393267
Directory /workspace/9.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.pwrmgr_csr_rw.2663826788
Short name T86
Test name
Test status
Simulation time 23505937 ps
CPU time 0.68 seconds
Started Mar 28 12:43:09 PM PDT 24
Finished Mar 28 12:43:10 PM PDT 24
Peak memory 196928 kb
Host smart-e5758221-04ed-4927-bb65-380f0e066b4c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2663826788 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.pwrmgr_csr_rw.2663826788
Directory /workspace/1.pwrmgr_csr_rw/latest

Test location /workspace/coverage/default/14.pwrmgr_reset_invalid.2498617423
Short name T32
Test name
Test status
Simulation time 164952941 ps
CPU time 0.78 seconds
Started Mar 28 01:23:43 PM PDT 24
Finished Mar 28 01:23:44 PM PDT 24
Peak memory 208804 kb
Host smart-9287e02b-5f58-4b32-90fe-8d5cb61b7454
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2498617423 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_reset_invalid.2498617423
Directory /workspace/14.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/cover_reg_top/1.pwrmgr_intr_test.89838982
Short name T1012
Test name
Test status
Simulation time 23064895 ps
CPU time 0.63 seconds
Started Mar 28 12:43:09 PM PDT 24
Finished Mar 28 12:43:10 PM PDT 24
Peak memory 194656 kb
Host smart-9201f12e-4011-4628-9361-bbfb50094878
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89838982 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.pwrmgr_intr_test.89838982
Directory /workspace/1.pwrmgr_intr_test/latest

Test location /workspace/coverage/default/0.pwrmgr_disable_rom_integrity_check.1167012274
Short name T146
Test name
Test status
Simulation time 63017738 ps
CPU time 0.76 seconds
Started Mar 28 01:21:34 PM PDT 24
Finished Mar 28 01:21:34 PM PDT 24
Peak memory 198468 kb
Host smart-00d98455-24d6-4e34-9d8c-9a8748ac9038
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1167012274 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_disa
ble_rom_integrity_check.1167012274
Directory /workspace/0.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/1.pwrmgr_disable_rom_integrity_check.3009472926
Short name T558
Test name
Test status
Simulation time 64474878 ps
CPU time 0.89 seconds
Started Mar 28 01:21:54 PM PDT 24
Finished Mar 28 01:21:55 PM PDT 24
Peak memory 198360 kb
Host smart-f8d90615-9ae8-4360-9dbf-2cf76caacb94
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3009472926 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_disa
ble_rom_integrity_check.3009472926
Directory /workspace/1.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/38.pwrmgr_disable_rom_integrity_check.4064827876
Short name T145
Test name
Test status
Simulation time 58049374 ps
CPU time 0.83 seconds
Started Mar 28 01:25:55 PM PDT 24
Finished Mar 28 01:25:57 PM PDT 24
Peak memory 198048 kb
Host smart-e61c2c07-d4ea-4cee-9907-a7023af343e7
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4064827876 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_dis
able_rom_integrity_check.4064827876
Directory /workspace/38.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/42.pwrmgr_disable_rom_integrity_check.2562645963
Short name T148
Test name
Test status
Simulation time 67073254 ps
CPU time 0.75 seconds
Started Mar 28 01:26:11 PM PDT 24
Finished Mar 28 01:26:12 PM PDT 24
Peak memory 198372 kb
Host smart-936303f5-ed09-4fa4-a4ba-2ad7ecf35a63
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2562645963 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_dis
able_rom_integrity_check.2562645963
Directory /workspace/42.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/cover_reg_top/11.pwrmgr_tl_errors.86209309
Short name T48
Test name
Test status
Simulation time 84772797 ps
CPU time 2.27 seconds
Started Mar 28 12:43:05 PM PDT 24
Finished Mar 28 12:43:07 PM PDT 24
Peak memory 197060 kb
Host smart-0623a858-1d3f-494d-9cf3-6b04b7f2bcf7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86209309 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.pwrmgr_tl_errors.86209309
Directory /workspace/11.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.pwrmgr_tl_intg_err.4268732163
Short name T60
Test name
Test status
Simulation time 96559878 ps
CPU time 1.19 seconds
Started Mar 28 12:43:10 PM PDT 24
Finished Mar 28 12:43:12 PM PDT 24
Peak memory 199836 kb
Host smart-78a72324-86f9-4cf5-91a0-f4f47adcb51f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4268732163 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.pwrmgr_tl_intg_er
r.4268732163
Directory /workspace/13.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.pwrmgr_tl_intg_err.4287781353
Short name T56
Test name
Test status
Simulation time 631247980 ps
CPU time 1.49 seconds
Started Mar 28 12:43:08 PM PDT 24
Finished Mar 28 12:43:10 PM PDT 24
Peak memory 199992 kb
Host smart-61fd5964-6d3f-400b-9107-ff8b289335f1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4287781353 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.pwrmgr_tl_intg_err
.4287781353
Directory /workspace/2.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/default/17.pwrmgr_glitch.4113991275
Short name T154
Test name
Test status
Simulation time 48837734 ps
CPU time 0.69 seconds
Started Mar 28 01:24:02 PM PDT 24
Finished Mar 28 01:24:03 PM PDT 24
Peak memory 197420 kb
Host smart-6dbd2e57-416f-4b1e-b5c3-4f44146adb33
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4113991275 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_glitch.4113991275
Directory /workspace/17.pwrmgr_glitch/latest

Test location /workspace/coverage/cover_reg_top/0.pwrmgr_csr_aliasing.1828297880
Short name T1098
Test name
Test status
Simulation time 145705604 ps
CPU time 0.99 seconds
Started Mar 28 12:43:09 PM PDT 24
Finished Mar 28 12:43:11 PM PDT 24
Peak memory 194656 kb
Host smart-f10eee8f-d42e-449a-9a03-105f720ff628
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1828297880 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.pwrmgr_csr_aliasing.1
828297880
Directory /workspace/0.pwrmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.pwrmgr_csr_bit_bash.2819390998
Short name T1104
Test name
Test status
Simulation time 86761993 ps
CPU time 1.67 seconds
Started Mar 28 12:43:03 PM PDT 24
Finished Mar 28 12:43:05 PM PDT 24
Peak memory 194840 kb
Host smart-fa1d5761-141a-4734-995c-4c9a0de15bac
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2819390998 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.pwrmgr_csr_bit_bash.2
819390998
Directory /workspace/0.pwrmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.pwrmgr_csr_hw_reset.3343970635
Short name T1000
Test name
Test status
Simulation time 36881392 ps
CPU time 0.66 seconds
Started Mar 28 12:43:03 PM PDT 24
Finished Mar 28 12:43:04 PM PDT 24
Peak memory 194768 kb
Host smart-8abf4371-b489-4384-ae7d-d134d4ea67a0
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3343970635 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.pwrmgr_csr_hw_reset.3
343970635
Directory /workspace/0.pwrmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.pwrmgr_csr_mem_rw_with_rand_reset.2395546601
Short name T1033
Test name
Test status
Simulation time 56019666 ps
CPU time 0.7 seconds
Started Mar 28 12:43:04 PM PDT 24
Finished Mar 28 12:43:04 PM PDT 24
Peak memory 194556 kb
Host smart-b886210a-9ac7-4c32-b20f-21ef61431e81
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2395546601 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 0.pwrmgr_csr_mem_rw_with_rand_reset.2395546601
Directory /workspace/0.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.pwrmgr_csr_rw.655521541
Short name T1078
Test name
Test status
Simulation time 23295889 ps
CPU time 0.72 seconds
Started Mar 28 12:43:09 PM PDT 24
Finished Mar 28 12:43:11 PM PDT 24
Peak memory 196936 kb
Host smart-cc42ec07-e016-41ab-b941-9ced1cb91705
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=655521541 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.pwrmgr_csr_rw.655521541
Directory /workspace/0.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.pwrmgr_intr_test.62100683
Short name T1070
Test name
Test status
Simulation time 42427653 ps
CPU time 0.61 seconds
Started Mar 28 12:43:04 PM PDT 24
Finished Mar 28 12:43:04 PM PDT 24
Peak memory 194216 kb
Host smart-72a68d45-6ac3-4b43-bc2e-71a119da75a4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62100683 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.pwrmgr_intr_test.62100683
Directory /workspace/0.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.pwrmgr_same_csr_outstanding.665575542
Short name T1031
Test name
Test status
Simulation time 45776863 ps
CPU time 0.7 seconds
Started Mar 28 12:43:09 PM PDT 24
Finished Mar 28 12:43:10 PM PDT 24
Peak memory 194652 kb
Host smart-9e3ebd4d-2840-4ded-a7a2-8153eac3ae05
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=665575542 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.pwrmgr_sam
e_csr_outstanding.665575542
Directory /workspace/0.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.pwrmgr_tl_errors.1011794160
Short name T1090
Test name
Test status
Simulation time 48739280 ps
CPU time 2.24 seconds
Started Mar 28 12:43:05 PM PDT 24
Finished Mar 28 12:43:07 PM PDT 24
Peak memory 196868 kb
Host smart-9a9755be-ef3f-4acd-9de9-9398249feefa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1011794160 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.pwrmgr_tl_errors.1011794160
Directory /workspace/0.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.pwrmgr_tl_intg_err.2929959607
Short name T136
Test name
Test status
Simulation time 183177877 ps
CPU time 1.03 seconds
Started Mar 28 12:43:03 PM PDT 24
Finished Mar 28 12:43:04 PM PDT 24
Peak memory 199644 kb
Host smart-bac6c2c7-0592-42f9-8816-beee67e51001
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2929959607 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.pwrmgr_tl_intg_err
.2929959607
Directory /workspace/0.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.pwrmgr_csr_aliasing.3649777293
Short name T993
Test name
Test status
Simulation time 42081212 ps
CPU time 0.99 seconds
Started Mar 28 12:43:05 PM PDT 24
Finished Mar 28 12:43:06 PM PDT 24
Peak memory 194752 kb
Host smart-d30545d5-dcd5-4818-834a-be1a02299a57
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3649777293 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.pwrmgr_csr_aliasing.3
649777293
Directory /workspace/1.pwrmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.pwrmgr_csr_bit_bash.862934918
Short name T1003
Test name
Test status
Simulation time 218680838 ps
CPU time 3.23 seconds
Started Mar 28 12:43:09 PM PDT 24
Finished Mar 28 12:43:13 PM PDT 24
Peak memory 194812 kb
Host smart-eb339080-3055-4753-bace-249a0323d1da
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=862934918 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.pwrmgr_csr_bit_bash.862934918
Directory /workspace/1.pwrmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.pwrmgr_csr_hw_reset.2501933238
Short name T88
Test name
Test status
Simulation time 38970566 ps
CPU time 0.67 seconds
Started Mar 28 12:43:05 PM PDT 24
Finished Mar 28 12:43:06 PM PDT 24
Peak memory 197084 kb
Host smart-04999f66-6696-412e-91c1-c7a494ae6d35
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2501933238 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.pwrmgr_csr_hw_reset.2
501933238
Directory /workspace/1.pwrmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.pwrmgr_csr_mem_rw_with_rand_reset.3662405946
Short name T999
Test name
Test status
Simulation time 70741655 ps
CPU time 0.95 seconds
Started Mar 28 12:43:09 PM PDT 24
Finished Mar 28 12:43:10 PM PDT 24
Peak memory 194792 kb
Host smart-a49790a5-818a-4d2a-939f-3bf49457ecbd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3662405946 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 1.pwrmgr_csr_mem_rw_with_rand_reset.3662405946
Directory /workspace/1.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.pwrmgr_same_csr_outstanding.2436764243
Short name T1080
Test name
Test status
Simulation time 154644864 ps
CPU time 0.73 seconds
Started Mar 28 12:43:09 PM PDT 24
Finished Mar 28 12:43:10 PM PDT 24
Peak memory 196896 kb
Host smart-72e74abb-b668-4976-98eb-eb08f9a4fa2c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2436764243 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.pwrmgr_sa
me_csr_outstanding.2436764243
Directory /workspace/1.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.pwrmgr_tl_errors.4092510668
Short name T1008
Test name
Test status
Simulation time 226154346 ps
CPU time 1.98 seconds
Started Mar 28 12:43:04 PM PDT 24
Finished Mar 28 12:43:06 PM PDT 24
Peak memory 195420 kb
Host smart-202ec322-beaa-4be5-a54a-07393b9927bf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4092510668 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.pwrmgr_tl_errors.4092510668
Directory /workspace/1.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.pwrmgr_tl_intg_err.354518816
Short name T133
Test name
Test status
Simulation time 213246534 ps
CPU time 1.74 seconds
Started Mar 28 12:43:08 PM PDT 24
Finished Mar 28 12:43:10 PM PDT 24
Peak memory 200084 kb
Host smart-61035f1b-35df-4454-9cb0-094423756176
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=354518816 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.pwrmgr_tl_intg_err.
354518816
Directory /workspace/1.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.pwrmgr_csr_mem_rw_with_rand_reset.2474585611
Short name T1001
Test name
Test status
Simulation time 55001856 ps
CPU time 1 seconds
Started Mar 28 12:43:09 PM PDT 24
Finished Mar 28 12:43:11 PM PDT 24
Peak memory 195736 kb
Host smart-196c1b8d-7e1f-40a2-b5bc-bb8b553ef74f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2474585611 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 10.pwrmgr_csr_mem_rw_with_rand_reset.2474585611
Directory /workspace/10.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.pwrmgr_csr_rw.1361488623
Short name T98
Test name
Test status
Simulation time 47177252 ps
CPU time 0.64 seconds
Started Mar 28 12:43:04 PM PDT 24
Finished Mar 28 12:43:05 PM PDT 24
Peak memory 196912 kb
Host smart-1aeb7867-ad1a-416d-87e8-316c54e27895
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1361488623 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.pwrmgr_csr_rw.1361488623
Directory /workspace/10.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.pwrmgr_intr_test.3645535145
Short name T1076
Test name
Test status
Simulation time 23177519 ps
CPU time 0.67 seconds
Started Mar 28 12:43:07 PM PDT 24
Finished Mar 28 12:43:07 PM PDT 24
Peak memory 194636 kb
Host smart-9c038010-e2a5-4f75-ab31-63b2b7930543
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3645535145 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.pwrmgr_intr_test.3645535145
Directory /workspace/10.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.pwrmgr_same_csr_outstanding.1733440603
Short name T1061
Test name
Test status
Simulation time 227134000 ps
CPU time 0.71 seconds
Started Mar 28 12:43:07 PM PDT 24
Finished Mar 28 12:43:07 PM PDT 24
Peak memory 194672 kb
Host smart-f675ed99-2676-44d3-996f-1f69247a28f7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1733440603 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.pwrmgr_s
ame_csr_outstanding.1733440603
Directory /workspace/10.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.pwrmgr_tl_errors.3602990965
Short name T1047
Test name
Test status
Simulation time 127945031 ps
CPU time 1.61 seconds
Started Mar 28 12:43:05 PM PDT 24
Finished Mar 28 12:43:07 PM PDT 24
Peak memory 195920 kb
Host smart-4ac28ced-7fd8-45b4-832b-e5551157d8e1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3602990965 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.pwrmgr_tl_errors.3602990965
Directory /workspace/10.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.pwrmgr_tl_intg_err.3070939311
Short name T1063
Test name
Test status
Simulation time 723792704 ps
CPU time 1.04 seconds
Started Mar 28 12:43:07 PM PDT 24
Finished Mar 28 12:43:08 PM PDT 24
Peak memory 194716 kb
Host smart-783116fa-c967-4a13-9025-aeb5ae6cbbf6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3070939311 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.pwrmgr_tl_intg_er
r.3070939311
Directory /workspace/10.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.pwrmgr_csr_mem_rw_with_rand_reset.2589877906
Short name T1005
Test name
Test status
Simulation time 109547700 ps
CPU time 0.8 seconds
Started Mar 28 12:43:09 PM PDT 24
Finished Mar 28 12:43:10 PM PDT 24
Peak memory 194864 kb
Host smart-256ea3be-e26f-414e-9fb0-2e36a5104cad
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2589877906 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 11.pwrmgr_csr_mem_rw_with_rand_reset.2589877906
Directory /workspace/11.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.pwrmgr_csr_rw.236095029
Short name T93
Test name
Test status
Simulation time 24995823 ps
CPU time 0.66 seconds
Started Mar 28 12:43:17 PM PDT 24
Finished Mar 28 12:43:18 PM PDT 24
Peak memory 194748 kb
Host smart-0e8d30d7-09d8-4fac-8950-1d22b29f1165
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=236095029 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.pwrmgr_csr_rw.236095029
Directory /workspace/11.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.pwrmgr_intr_test.2364960403
Short name T1102
Test name
Test status
Simulation time 20849828 ps
CPU time 0.6 seconds
Started Mar 28 12:43:09 PM PDT 24
Finished Mar 28 12:43:10 PM PDT 24
Peak memory 194640 kb
Host smart-f8067ec5-ec09-431e-a840-aaf29a913a6d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2364960403 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.pwrmgr_intr_test.2364960403
Directory /workspace/11.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.pwrmgr_same_csr_outstanding.1547308362
Short name T102
Test name
Test status
Simulation time 123784932 ps
CPU time 0.72 seconds
Started Mar 28 12:43:09 PM PDT 24
Finished Mar 28 12:43:10 PM PDT 24
Peak memory 194724 kb
Host smart-762c323b-25cb-4a44-81fc-c8c735fa829f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1547308362 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.pwrmgr_s
ame_csr_outstanding.1547308362
Directory /workspace/11.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.pwrmgr_tl_intg_err.3542984188
Short name T1072
Test name
Test status
Simulation time 221782287 ps
CPU time 1.1 seconds
Started Mar 28 12:43:15 PM PDT 24
Finished Mar 28 12:43:17 PM PDT 24
Peak memory 199440 kb
Host smart-4386de47-acdb-4f46-a856-7f07481816e7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3542984188 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.pwrmgr_tl_intg_er
r.3542984188
Directory /workspace/11.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.pwrmgr_csr_mem_rw_with_rand_reset.266471854
Short name T1067
Test name
Test status
Simulation time 66723551 ps
CPU time 0.86 seconds
Started Mar 28 12:43:20 PM PDT 24
Finished Mar 28 12:43:21 PM PDT 24
Peak memory 194684 kb
Host smart-4008ad76-f8bd-4f12-87cd-84ee15264f02
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=266471854 -assert nopostproc +UVM_TESTNAME=
pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 12.pwrmgr_csr_mem_rw_with_rand_reset.266471854
Directory /workspace/12.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.pwrmgr_csr_rw.2562287347
Short name T1085
Test name
Test status
Simulation time 46348206 ps
CPU time 0.65 seconds
Started Mar 28 12:43:04 PM PDT 24
Finished Mar 28 12:43:05 PM PDT 24
Peak memory 196916 kb
Host smart-f1324992-1404-4103-82d2-51cf3a30f245
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2562287347 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.pwrmgr_csr_rw.2562287347
Directory /workspace/12.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.pwrmgr_intr_test.3182402857
Short name T1024
Test name
Test status
Simulation time 43910914 ps
CPU time 0.62 seconds
Started Mar 28 12:43:03 PM PDT 24
Finished Mar 28 12:43:04 PM PDT 24
Peak memory 194612 kb
Host smart-3a86807e-400d-4bf0-b569-7403d0cde8cf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3182402857 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.pwrmgr_intr_test.3182402857
Directory /workspace/12.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.pwrmgr_same_csr_outstanding.3237122540
Short name T1046
Test name
Test status
Simulation time 84675704 ps
CPU time 0.71 seconds
Started Mar 28 12:43:10 PM PDT 24
Finished Mar 28 12:43:11 PM PDT 24
Peak memory 198040 kb
Host smart-e151d298-3546-4f44-8bb4-1817f19cda4c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3237122540 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.pwrmgr_s
ame_csr_outstanding.3237122540
Directory /workspace/12.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.pwrmgr_tl_errors.409262853
Short name T59
Test name
Test status
Simulation time 44168843 ps
CPU time 1.65 seconds
Started Mar 28 12:43:09 PM PDT 24
Finished Mar 28 12:43:11 PM PDT 24
Peak memory 196900 kb
Host smart-1da167cb-ea5f-460c-a00c-91a52418479d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=409262853 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.pwrmgr_tl_errors.409262853
Directory /workspace/12.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.pwrmgr_tl_intg_err.407891894
Short name T43
Test name
Test status
Simulation time 94990383 ps
CPU time 1.23 seconds
Started Mar 28 12:43:05 PM PDT 24
Finished Mar 28 12:43:06 PM PDT 24
Peak memory 199740 kb
Host smart-9e569b19-ba3a-476d-872c-fb76511750ff
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=407891894 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.pwrmgr_tl_intg_err
.407891894
Directory /workspace/12.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.pwrmgr_csr_mem_rw_with_rand_reset.3570915547
Short name T1068
Test name
Test status
Simulation time 58415114 ps
CPU time 1.16 seconds
Started Mar 28 12:42:57 PM PDT 24
Finished Mar 28 12:42:58 PM PDT 24
Peak memory 198524 kb
Host smart-098b53fd-8b68-42e8-b41d-12eb1079df97
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3570915547 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 13.pwrmgr_csr_mem_rw_with_rand_reset.3570915547
Directory /workspace/13.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.pwrmgr_csr_rw.3110158615
Short name T87
Test name
Test status
Simulation time 33012431 ps
CPU time 0.62 seconds
Started Mar 28 12:43:23 PM PDT 24
Finished Mar 28 12:43:24 PM PDT 24
Peak memory 194616 kb
Host smart-2d531aec-0d03-495f-bd58-6497a35ddd6e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3110158615 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.pwrmgr_csr_rw.3110158615
Directory /workspace/13.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.pwrmgr_intr_test.301547879
Short name T1009
Test name
Test status
Simulation time 42968758 ps
CPU time 0.65 seconds
Started Mar 28 12:43:10 PM PDT 24
Finished Mar 28 12:43:11 PM PDT 24
Peak memory 194736 kb
Host smart-50a00da9-97d3-4ac0-93f2-68e1d24bf820
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=301547879 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.pwrmgr_intr_test.301547879
Directory /workspace/13.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.pwrmgr_same_csr_outstanding.2775162441
Short name T103
Test name
Test status
Simulation time 72252309 ps
CPU time 0.88 seconds
Started Mar 28 12:43:18 PM PDT 24
Finished Mar 28 12:43:19 PM PDT 24
Peak memory 194540 kb
Host smart-85a8bc39-a795-45ee-baff-17e17432bbb1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2775162441 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.pwrmgr_s
ame_csr_outstanding.2775162441
Directory /workspace/13.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.pwrmgr_tl_errors.469233097
Short name T52
Test name
Test status
Simulation time 361250914 ps
CPU time 2.17 seconds
Started Mar 28 12:43:10 PM PDT 24
Finished Mar 28 12:43:13 PM PDT 24
Peak memory 195988 kb
Host smart-6e47dcc9-0792-4b51-912a-ebe7c69c035e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=469233097 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.pwrmgr_tl_errors.469233097
Directory /workspace/13.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.pwrmgr_csr_mem_rw_with_rand_reset.740045555
Short name T1081
Test name
Test status
Simulation time 53638018 ps
CPU time 0.78 seconds
Started Mar 28 12:43:13 PM PDT 24
Finished Mar 28 12:43:13 PM PDT 24
Peak memory 194772 kb
Host smart-9e469114-c1cb-4a46-ba8a-1a2c8dc9b2ab
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=740045555 -assert nopostproc +UVM_TESTNAME=
pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 14.pwrmgr_csr_mem_rw_with_rand_reset.740045555
Directory /workspace/14.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.pwrmgr_csr_rw.1023579778
Short name T95
Test name
Test status
Simulation time 19223878 ps
CPU time 0.66 seconds
Started Mar 28 12:43:14 PM PDT 24
Finished Mar 28 12:43:15 PM PDT 24
Peak memory 194628 kb
Host smart-7fe84ecd-d33a-47ef-a8df-f6f709776743
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1023579778 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.pwrmgr_csr_rw.1023579778
Directory /workspace/14.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.pwrmgr_intr_test.3179012605
Short name T142
Test name
Test status
Simulation time 21696189 ps
CPU time 0.64 seconds
Started Mar 28 12:43:13 PM PDT 24
Finished Mar 28 12:43:14 PM PDT 24
Peak memory 194536 kb
Host smart-faaa09cd-de98-4d7a-a2b6-19b58d0034d8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3179012605 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.pwrmgr_intr_test.3179012605
Directory /workspace/14.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.pwrmgr_same_csr_outstanding.660927006
Short name T1044
Test name
Test status
Simulation time 33154399 ps
CPU time 0.94 seconds
Started Mar 28 12:43:07 PM PDT 24
Finished Mar 28 12:43:08 PM PDT 24
Peak memory 194592 kb
Host smart-ab62f099-f612-4e5b-9003-add08dea1be6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=660927006 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.pwrmgr_sa
me_csr_outstanding.660927006
Directory /workspace/14.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.pwrmgr_tl_errors.3123430439
Short name T1084
Test name
Test status
Simulation time 209893971 ps
CPU time 1.49 seconds
Started Mar 28 12:43:13 PM PDT 24
Finished Mar 28 12:43:15 PM PDT 24
Peak memory 194856 kb
Host smart-edadedf7-fb05-47fa-8da4-c7faf077b125
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3123430439 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.pwrmgr_tl_errors.3123430439
Directory /workspace/14.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.pwrmgr_csr_mem_rw_with_rand_reset.706295475
Short name T1059
Test name
Test status
Simulation time 36034107 ps
CPU time 0.8 seconds
Started Mar 28 12:43:13 PM PDT 24
Finished Mar 28 12:43:14 PM PDT 24
Peak memory 194552 kb
Host smart-2d5d3721-2ea2-4001-8eb8-2622d9454db6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=706295475 -assert nopostproc +UVM_TESTNAME=
pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 15.pwrmgr_csr_mem_rw_with_rand_reset.706295475
Directory /workspace/15.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.pwrmgr_csr_rw.1737434146
Short name T91
Test name
Test status
Simulation time 24203233 ps
CPU time 0.63 seconds
Started Mar 28 12:43:09 PM PDT 24
Finished Mar 28 12:43:10 PM PDT 24
Peak memory 194796 kb
Host smart-d9fd39c8-f2b4-48e2-9493-9e926688b2b6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1737434146 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.pwrmgr_csr_rw.1737434146
Directory /workspace/15.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.pwrmgr_intr_test.2842590816
Short name T1051
Test name
Test status
Simulation time 39160613 ps
CPU time 0.59 seconds
Started Mar 28 12:43:09 PM PDT 24
Finished Mar 28 12:43:10 PM PDT 24
Peak memory 194664 kb
Host smart-5f1fa45c-e058-466e-a3e3-dec21ac9a9ff
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2842590816 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.pwrmgr_intr_test.2842590816
Directory /workspace/15.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.pwrmgr_same_csr_outstanding.171852797
Short name T1075
Test name
Test status
Simulation time 28398943 ps
CPU time 0.77 seconds
Started Mar 28 12:43:22 PM PDT 24
Finished Mar 28 12:43:23 PM PDT 24
Peak memory 196948 kb
Host smart-a4db6af6-b6e4-4019-8e50-6d74c31af217
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=171852797 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.pwrmgr_sa
me_csr_outstanding.171852797
Directory /workspace/15.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.pwrmgr_tl_errors.47376157
Short name T1014
Test name
Test status
Simulation time 71252174 ps
CPU time 1.66 seconds
Started Mar 28 12:43:13 PM PDT 24
Finished Mar 28 12:43:15 PM PDT 24
Peak memory 195780 kb
Host smart-bc72fa75-7073-45aa-8072-9c26a4400b38
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47376157 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.pwrmgr_tl_errors.47376157
Directory /workspace/15.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.pwrmgr_tl_intg_err.4263381382
Short name T61
Test name
Test status
Simulation time 237496193 ps
CPU time 1.15 seconds
Started Mar 28 12:43:09 PM PDT 24
Finished Mar 28 12:43:10 PM PDT 24
Peak memory 199500 kb
Host smart-ce887c66-bbfb-4c14-ac50-17afd4abe1e4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4263381382 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.pwrmgr_tl_intg_er
r.4263381382
Directory /workspace/15.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.pwrmgr_csr_mem_rw_with_rand_reset.566418497
Short name T998
Test name
Test status
Simulation time 212862190 ps
CPU time 0.88 seconds
Started Mar 28 12:42:59 PM PDT 24
Finished Mar 28 12:43:00 PM PDT 24
Peak memory 194956 kb
Host smart-ee046a16-ec27-493b-932c-fb2a6a03e3bf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=566418497 -assert nopostproc +UVM_TESTNAME=
pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 16.pwrmgr_csr_mem_rw_with_rand_reset.566418497
Directory /workspace/16.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.pwrmgr_csr_rw.1634183423
Short name T99
Test name
Test status
Simulation time 45065944 ps
CPU time 0.64 seconds
Started Mar 28 12:43:02 PM PDT 24
Finished Mar 28 12:43:03 PM PDT 24
Peak memory 194752 kb
Host smart-9ce2226b-cf1f-4086-bfad-db103ef103a7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1634183423 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.pwrmgr_csr_rw.1634183423
Directory /workspace/16.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.pwrmgr_intr_test.3342538688
Short name T1027
Test name
Test status
Simulation time 53081926 ps
CPU time 0.58 seconds
Started Mar 28 12:43:02 PM PDT 24
Finished Mar 28 12:43:03 PM PDT 24
Peak memory 194620 kb
Host smart-aad28809-9457-4c8f-9662-9c353b5f8eb2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3342538688 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.pwrmgr_intr_test.3342538688
Directory /workspace/16.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.pwrmgr_same_csr_outstanding.908453078
Short name T1043
Test name
Test status
Simulation time 46576758 ps
CPU time 0.85 seconds
Started Mar 28 12:43:13 PM PDT 24
Finished Mar 28 12:43:14 PM PDT 24
Peak memory 194628 kb
Host smart-dee68de1-88be-4075-8a10-4be5f30272e4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=908453078 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.pwrmgr_sa
me_csr_outstanding.908453078
Directory /workspace/16.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.pwrmgr_tl_errors.3617567010
Short name T1109
Test name
Test status
Simulation time 97387317 ps
CPU time 1.92 seconds
Started Mar 28 12:43:09 PM PDT 24
Finished Mar 28 12:43:12 PM PDT 24
Peak memory 196972 kb
Host smart-4cfbb6c1-e154-4ce2-9807-5833d53eacd6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3617567010 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.pwrmgr_tl_errors.3617567010
Directory /workspace/16.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.pwrmgr_tl_intg_err.3436696828
Short name T49
Test name
Test status
Simulation time 398672870 ps
CPU time 1.43 seconds
Started Mar 28 12:43:17 PM PDT 24
Finished Mar 28 12:43:18 PM PDT 24
Peak memory 194988 kb
Host smart-1775f021-2ebf-4fb7-bf96-9e727c9dc506
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3436696828 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.pwrmgr_tl_intg_er
r.3436696828
Directory /workspace/16.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.pwrmgr_csr_mem_rw_with_rand_reset.1922567271
Short name T1034
Test name
Test status
Simulation time 53128433 ps
CPU time 1.22 seconds
Started Mar 28 12:43:07 PM PDT 24
Finished Mar 28 12:43:09 PM PDT 24
Peak memory 196868 kb
Host smart-0f5b55ab-c3ed-496a-8788-c8472e2e32b7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1922567271 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 17.pwrmgr_csr_mem_rw_with_rand_reset.1922567271
Directory /workspace/17.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.pwrmgr_csr_rw.1394510391
Short name T89
Test name
Test status
Simulation time 16865185 ps
CPU time 0.63 seconds
Started Mar 28 12:43:07 PM PDT 24
Finished Mar 28 12:43:08 PM PDT 24
Peak memory 196824 kb
Host smart-69638a53-5ddb-49e5-aebe-413354d945b8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1394510391 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.pwrmgr_csr_rw.1394510391
Directory /workspace/17.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.pwrmgr_intr_test.2317758892
Short name T1095
Test name
Test status
Simulation time 22770601 ps
CPU time 0.64 seconds
Started Mar 28 12:43:07 PM PDT 24
Finished Mar 28 12:43:08 PM PDT 24
Peak memory 194684 kb
Host smart-4f410873-7ef2-4016-ab57-ceba8bf77c00
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2317758892 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.pwrmgr_intr_test.2317758892
Directory /workspace/17.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.pwrmgr_same_csr_outstanding.1013658804
Short name T1092
Test name
Test status
Simulation time 86605643 ps
CPU time 0.8 seconds
Started Mar 28 12:43:09 PM PDT 24
Finished Mar 28 12:43:10 PM PDT 24
Peak memory 194652 kb
Host smart-96462efe-855f-45b4-8b5c-a6959da76259
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1013658804 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.pwrmgr_s
ame_csr_outstanding.1013658804
Directory /workspace/17.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.pwrmgr_tl_errors.3876048211
Short name T1097
Test name
Test status
Simulation time 263116494 ps
CPU time 1.43 seconds
Started Mar 28 12:43:07 PM PDT 24
Finished Mar 28 12:43:08 PM PDT 24
Peak memory 196048 kb
Host smart-23ef0ef8-4487-4cfb-a968-d84c357409c6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3876048211 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.pwrmgr_tl_errors.3876048211
Directory /workspace/17.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.pwrmgr_tl_intg_err.3121843557
Short name T1007
Test name
Test status
Simulation time 1369216693 ps
CPU time 1.49 seconds
Started Mar 28 12:43:07 PM PDT 24
Finished Mar 28 12:43:09 PM PDT 24
Peak memory 200132 kb
Host smart-8f669547-239b-41ae-88e4-c3d0ed3b26b5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3121843557 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.pwrmgr_tl_intg_er
r.3121843557
Directory /workspace/17.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.pwrmgr_csr_mem_rw_with_rand_reset.2189486314
Short name T1082
Test name
Test status
Simulation time 61742068 ps
CPU time 1 seconds
Started Mar 28 12:43:02 PM PDT 24
Finished Mar 28 12:43:03 PM PDT 24
Peak memory 194860 kb
Host smart-e9aad7d9-c28d-4f15-8da6-d60d2c21f37d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2189486314 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 18.pwrmgr_csr_mem_rw_with_rand_reset.2189486314
Directory /workspace/18.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.pwrmgr_csr_rw.2461628980
Short name T1036
Test name
Test status
Simulation time 62021761 ps
CPU time 0.65 seconds
Started Mar 28 12:43:03 PM PDT 24
Finished Mar 28 12:43:04 PM PDT 24
Peak memory 196904 kb
Host smart-9ea58d05-0641-4852-a66e-816dfc6dd2b6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2461628980 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.pwrmgr_csr_rw.2461628980
Directory /workspace/18.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.pwrmgr_intr_test.361472860
Short name T1050
Test name
Test status
Simulation time 22145526 ps
CPU time 0.63 seconds
Started Mar 28 12:43:07 PM PDT 24
Finished Mar 28 12:43:08 PM PDT 24
Peak memory 194572 kb
Host smart-717fd488-0d25-4775-b82f-af8438595c36
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=361472860 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.pwrmgr_intr_test.361472860
Directory /workspace/18.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.pwrmgr_same_csr_outstanding.1871452938
Short name T1101
Test name
Test status
Simulation time 49480912 ps
CPU time 0.75 seconds
Started Mar 28 12:43:04 PM PDT 24
Finished Mar 28 12:43:05 PM PDT 24
Peak memory 196648 kb
Host smart-2639e889-c38d-432b-a87d-b1501428ab3e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1871452938 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.pwrmgr_s
ame_csr_outstanding.1871452938
Directory /workspace/18.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.pwrmgr_tl_errors.2730631825
Short name T57
Test name
Test status
Simulation time 434618671 ps
CPU time 1.11 seconds
Started Mar 28 12:43:16 PM PDT 24
Finished Mar 28 12:43:17 PM PDT 24
Peak memory 195660 kb
Host smart-fbcf6ba8-ec59-48f1-a82c-31d06eedc3ea
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2730631825 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.pwrmgr_tl_errors.2730631825
Directory /workspace/18.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.pwrmgr_tl_intg_err.4145997672
Short name T1105
Test name
Test status
Simulation time 191305572 ps
CPU time 1.91 seconds
Started Mar 28 12:43:02 PM PDT 24
Finished Mar 28 12:43:04 PM PDT 24
Peak memory 200028 kb
Host smart-156e8253-2ab0-4dfc-8eba-ba01eb2c647e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4145997672 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.pwrmgr_tl_intg_er
r.4145997672
Directory /workspace/18.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.pwrmgr_csr_mem_rw_with_rand_reset.1441875738
Short name T1103
Test name
Test status
Simulation time 74444917 ps
CPU time 0.84 seconds
Started Mar 28 12:42:56 PM PDT 24
Finished Mar 28 12:42:56 PM PDT 24
Peak memory 194920 kb
Host smart-435c8708-35ce-4d29-b82b-7027e4bdb36a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1441875738 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 19.pwrmgr_csr_mem_rw_with_rand_reset.1441875738
Directory /workspace/19.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.pwrmgr_csr_rw.334232593
Short name T1057
Test name
Test status
Simulation time 43297956 ps
CPU time 0.63 seconds
Started Mar 28 12:43:09 PM PDT 24
Finished Mar 28 12:43:10 PM PDT 24
Peak memory 194748 kb
Host smart-15d67f16-24a8-4dac-95a3-5b514de7b28e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=334232593 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.pwrmgr_csr_rw.334232593
Directory /workspace/19.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.pwrmgr_intr_test.3708056420
Short name T54
Test name
Test status
Simulation time 22301561 ps
CPU time 0.67 seconds
Started Mar 28 12:43:09 PM PDT 24
Finished Mar 28 12:43:10 PM PDT 24
Peak memory 194624 kb
Host smart-5c1a7419-e09a-4739-aba5-5a134a87391f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3708056420 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.pwrmgr_intr_test.3708056420
Directory /workspace/19.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.pwrmgr_same_csr_outstanding.80936596
Short name T1021
Test name
Test status
Simulation time 54148502 ps
CPU time 0.81 seconds
Started Mar 28 12:43:09 PM PDT 24
Finished Mar 28 12:43:10 PM PDT 24
Peak memory 197876 kb
Host smart-7782789b-3a2f-4dcd-9dee-c79658810749
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80936596 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmg
r_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.pwrmgr_sam
e_csr_outstanding.80936596
Directory /workspace/19.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.pwrmgr_tl_errors.4029714160
Short name T1107
Test name
Test status
Simulation time 437901817 ps
CPU time 2.51 seconds
Started Mar 28 12:43:09 PM PDT 24
Finished Mar 28 12:43:12 PM PDT 24
Peak memory 196992 kb
Host smart-6df65209-99a1-49fa-b6d7-f1549a63d104
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4029714160 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.pwrmgr_tl_errors.4029714160
Directory /workspace/19.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.pwrmgr_tl_intg_err.1031433046
Short name T38
Test name
Test status
Simulation time 385801587 ps
CPU time 1.15 seconds
Started Mar 28 12:43:09 PM PDT 24
Finished Mar 28 12:43:11 PM PDT 24
Peak memory 194788 kb
Host smart-d6d4e148-91f6-4e2b-af33-9afffc32ba52
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1031433046 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.pwrmgr_tl_intg_er
r.1031433046
Directory /workspace/19.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.pwrmgr_csr_bit_bash.3083334496
Short name T1011
Test name
Test status
Simulation time 354351473 ps
CPU time 2.77 seconds
Started Mar 28 12:43:07 PM PDT 24
Finished Mar 28 12:43:10 PM PDT 24
Peak memory 198452 kb
Host smart-2b2fa101-1bdf-4b94-8e14-7c02282947af
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3083334496 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.pwrmgr_csr_bit_bash.3
083334496
Directory /workspace/2.pwrmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.pwrmgr_csr_hw_reset.1310243671
Short name T1062
Test name
Test status
Simulation time 65609613 ps
CPU time 0.63 seconds
Started Mar 28 12:43:10 PM PDT 24
Finished Mar 28 12:43:11 PM PDT 24
Peak memory 196696 kb
Host smart-6b3b1272-1c4e-4845-b2e5-2e23f9ac1fa2
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1310243671 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.pwrmgr_csr_hw_reset.1
310243671
Directory /workspace/2.pwrmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.pwrmgr_csr_rw.4029633823
Short name T97
Test name
Test status
Simulation time 19417055 ps
CPU time 0.62 seconds
Started Mar 28 12:43:16 PM PDT 24
Finished Mar 28 12:43:16 PM PDT 24
Peak memory 196836 kb
Host smart-19da3fd6-cc05-4bf3-bcbf-28872868592e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4029633823 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.pwrmgr_csr_rw.4029633823
Directory /workspace/2.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.pwrmgr_intr_test.3095432112
Short name T1096
Test name
Test status
Simulation time 40537024 ps
CPU time 0.58 seconds
Started Mar 28 12:43:08 PM PDT 24
Finished Mar 28 12:43:09 PM PDT 24
Peak memory 194576 kb
Host smart-7f08ef34-0dd4-4032-a497-3b067388f57b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3095432112 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.pwrmgr_intr_test.3095432112
Directory /workspace/2.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.pwrmgr_same_csr_outstanding.70815928
Short name T1077
Test name
Test status
Simulation time 30615026 ps
CPU time 0.72 seconds
Started Mar 28 12:43:08 PM PDT 24
Finished Mar 28 12:43:09 PM PDT 24
Peak memory 196816 kb
Host smart-742acf8e-e80c-4118-a36f-6e8eedc03382
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70815928 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmg
r_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.pwrmgr_same
_csr_outstanding.70815928
Directory /workspace/2.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.pwrmgr_tl_errors.2681741892
Short name T1039
Test name
Test status
Simulation time 46661239 ps
CPU time 2.29 seconds
Started Mar 28 12:42:57 PM PDT 24
Finished Mar 28 12:43:00 PM PDT 24
Peak memory 197252 kb
Host smart-453aebc6-aabe-42e1-8fe6-c0885e3eeca1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2681741892 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.pwrmgr_tl_errors.2681741892
Directory /workspace/2.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/20.pwrmgr_intr_test.2563932647
Short name T1079
Test name
Test status
Simulation time 42821542 ps
CPU time 0.63 seconds
Started Mar 28 12:43:18 PM PDT 24
Finished Mar 28 12:43:18 PM PDT 24
Peak memory 194640 kb
Host smart-5f81932c-4143-45bf-b1bc-4fa39fc7d74a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2563932647 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.pwrmgr_intr_test.2563932647
Directory /workspace/20.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.pwrmgr_intr_test.2999492022
Short name T1086
Test name
Test status
Simulation time 46226145 ps
CPU time 0.63 seconds
Started Mar 28 12:43:01 PM PDT 24
Finished Mar 28 12:43:01 PM PDT 24
Peak memory 194640 kb
Host smart-7ba05aee-c109-4be4-9178-00ef9d1b2d25
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2999492022 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.pwrmgr_intr_test.2999492022
Directory /workspace/21.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.pwrmgr_intr_test.4214414239
Short name T1087
Test name
Test status
Simulation time 93976146 ps
CPU time 0.6 seconds
Started Mar 28 12:43:09 PM PDT 24
Finished Mar 28 12:43:10 PM PDT 24
Peak memory 194640 kb
Host smart-9c575ab3-53e1-49e7-92bc-503d5ba5d54a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4214414239 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.pwrmgr_intr_test.4214414239
Directory /workspace/22.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.pwrmgr_intr_test.4267517334
Short name T139
Test name
Test status
Simulation time 25121858 ps
CPU time 0.61 seconds
Started Mar 28 12:43:04 PM PDT 24
Finished Mar 28 12:43:04 PM PDT 24
Peak memory 194616 kb
Host smart-1bcb3fec-f5bb-4ce5-935d-b16245e38702
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4267517334 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.pwrmgr_intr_test.4267517334
Directory /workspace/23.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.pwrmgr_intr_test.3939793531
Short name T1020
Test name
Test status
Simulation time 44273331 ps
CPU time 0.68 seconds
Started Mar 28 12:43:05 PM PDT 24
Finished Mar 28 12:43:06 PM PDT 24
Peak memory 194612 kb
Host smart-673c069d-dafe-48fc-952b-bfe541b9c942
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3939793531 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.pwrmgr_intr_test.3939793531
Directory /workspace/24.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.pwrmgr_intr_test.1847687644
Short name T1002
Test name
Test status
Simulation time 19315407 ps
CPU time 0.63 seconds
Started Mar 28 12:43:08 PM PDT 24
Finished Mar 28 12:43:09 PM PDT 24
Peak memory 194552 kb
Host smart-cf2c1900-21b0-4b06-a2d4-f29609b77f05
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1847687644 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.pwrmgr_intr_test.1847687644
Directory /workspace/25.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.pwrmgr_intr_test.1408726555
Short name T1022
Test name
Test status
Simulation time 34147946 ps
CPU time 0.64 seconds
Started Mar 28 12:43:10 PM PDT 24
Finished Mar 28 12:43:11 PM PDT 24
Peak memory 194636 kb
Host smart-a37d46d5-9c39-45c3-afdd-f0a0f9a30177
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1408726555 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.pwrmgr_intr_test.1408726555
Directory /workspace/26.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.pwrmgr_intr_test.171362438
Short name T141
Test name
Test status
Simulation time 72116490 ps
CPU time 0.6 seconds
Started Mar 28 12:43:13 PM PDT 24
Finished Mar 28 12:43:14 PM PDT 24
Peak memory 194540 kb
Host smart-c0340fa0-a170-4de6-ab3f-efb4c55f53b7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=171362438 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.pwrmgr_intr_test.171362438
Directory /workspace/27.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.pwrmgr_intr_test.2551921177
Short name T1053
Test name
Test status
Simulation time 20475518 ps
CPU time 0.63 seconds
Started Mar 28 12:43:14 PM PDT 24
Finished Mar 28 12:43:15 PM PDT 24
Peak memory 194540 kb
Host smart-417821ac-981f-4c53-9ada-d58f0869ed8d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2551921177 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.pwrmgr_intr_test.2551921177
Directory /workspace/28.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.pwrmgr_intr_test.2989911167
Short name T1040
Test name
Test status
Simulation time 48363174 ps
CPU time 0.62 seconds
Started Mar 28 12:43:10 PM PDT 24
Finished Mar 28 12:43:11 PM PDT 24
Peak memory 194732 kb
Host smart-559e5c90-f004-43f9-9091-c66e34974246
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2989911167 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.pwrmgr_intr_test.2989911167
Directory /workspace/29.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.pwrmgr_csr_aliasing.2715339703
Short name T995
Test name
Test status
Simulation time 59700766 ps
CPU time 0.82 seconds
Started Mar 28 12:43:09 PM PDT 24
Finished Mar 28 12:43:10 PM PDT 24
Peak memory 197212 kb
Host smart-d0a3ea3f-cccf-4b9a-9109-bbc5ef928301
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2715339703 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.pwrmgr_csr_aliasing.2
715339703
Directory /workspace/3.pwrmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.pwrmgr_csr_bit_bash.2155090986
Short name T996
Test name
Test status
Simulation time 74985162 ps
CPU time 2.9 seconds
Started Mar 28 12:43:09 PM PDT 24
Finished Mar 28 12:43:12 PM PDT 24
Peak memory 198340 kb
Host smart-0800ec3a-98b9-4c0b-a34e-27eeb8e2c77e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2155090986 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.pwrmgr_csr_bit_bash.2
155090986
Directory /workspace/3.pwrmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.pwrmgr_csr_hw_reset.2168739260
Short name T997
Test name
Test status
Simulation time 40271528 ps
CPU time 0.67 seconds
Started Mar 28 12:43:14 PM PDT 24
Finished Mar 28 12:43:15 PM PDT 24
Peak memory 195868 kb
Host smart-4fb0034a-9f43-4a01-b8e0-f5234600ea0c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2168739260 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.pwrmgr_csr_hw_reset.2
168739260
Directory /workspace/3.pwrmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.pwrmgr_csr_mem_rw_with_rand_reset.1421877386
Short name T76
Test name
Test status
Simulation time 65161509 ps
CPU time 0.77 seconds
Started Mar 28 12:43:11 PM PDT 24
Finished Mar 28 12:43:11 PM PDT 24
Peak memory 194808 kb
Host smart-508a0f36-1f59-4af2-8605-e2427202f99f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1421877386 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 3.pwrmgr_csr_mem_rw_with_rand_reset.1421877386
Directory /workspace/3.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.pwrmgr_csr_rw.996719594
Short name T92
Test name
Test status
Simulation time 21907417 ps
CPU time 0.68 seconds
Started Mar 28 12:43:03 PM PDT 24
Finished Mar 28 12:43:04 PM PDT 24
Peak memory 196920 kb
Host smart-6964fbfc-9f27-40d3-afb7-1d2b9a7d3803
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=996719594 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.pwrmgr_csr_rw.996719594
Directory /workspace/3.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.pwrmgr_intr_test.1957163562
Short name T1038
Test name
Test status
Simulation time 19393767 ps
CPU time 0.64 seconds
Started Mar 28 12:43:15 PM PDT 24
Finished Mar 28 12:43:16 PM PDT 24
Peak memory 194428 kb
Host smart-0089fbcb-3950-4f9d-8ce3-f5e97bb47853
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1957163562 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.pwrmgr_intr_test.1957163562
Directory /workspace/3.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.pwrmgr_same_csr_outstanding.1920623599
Short name T1018
Test name
Test status
Simulation time 98365745 ps
CPU time 0.72 seconds
Started Mar 28 12:43:09 PM PDT 24
Finished Mar 28 12:43:10 PM PDT 24
Peak memory 196916 kb
Host smart-c06aacc7-f733-4b2e-99f2-e16b1ea4da3b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1920623599 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.pwrmgr_sa
me_csr_outstanding.1920623599
Directory /workspace/3.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.pwrmgr_tl_errors.302525498
Short name T42
Test name
Test status
Simulation time 64489002 ps
CPU time 1.5 seconds
Started Mar 28 12:43:10 PM PDT 24
Finished Mar 28 12:43:12 PM PDT 24
Peak memory 195976 kb
Host smart-b406c1f7-8af8-4b23-b311-58ffe6ab5c51
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=302525498 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.pwrmgr_tl_errors.302525498
Directory /workspace/3.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/30.pwrmgr_intr_test.3281466522
Short name T1006
Test name
Test status
Simulation time 49276218 ps
CPU time 0.58 seconds
Started Mar 28 12:43:23 PM PDT 24
Finished Mar 28 12:43:24 PM PDT 24
Peak memory 194748 kb
Host smart-a1133590-bde8-4932-9bdf-81c8cf9b2b43
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3281466522 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.pwrmgr_intr_test.3281466522
Directory /workspace/30.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.pwrmgr_intr_test.1524853185
Short name T1048
Test name
Test status
Simulation time 68079396 ps
CPU time 0.62 seconds
Started Mar 28 12:43:24 PM PDT 24
Finished Mar 28 12:43:25 PM PDT 24
Peak memory 194684 kb
Host smart-d7be77e9-6413-46a5-8a47-6384673eba13
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1524853185 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.pwrmgr_intr_test.1524853185
Directory /workspace/31.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.pwrmgr_intr_test.2909602345
Short name T1010
Test name
Test status
Simulation time 116791323 ps
CPU time 0.56 seconds
Started Mar 28 12:43:27 PM PDT 24
Finished Mar 28 12:43:27 PM PDT 24
Peak memory 194688 kb
Host smart-7027b9fd-9a63-4b3e-926c-9e2ca7c5f56c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2909602345 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.pwrmgr_intr_test.2909602345
Directory /workspace/32.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.pwrmgr_intr_test.3886657886
Short name T1073
Test name
Test status
Simulation time 48772442 ps
CPU time 0.64 seconds
Started Mar 28 12:43:25 PM PDT 24
Finished Mar 28 12:43:26 PM PDT 24
Peak memory 194776 kb
Host smart-74cb1ff7-b7be-4261-ac29-dc3b3e60e980
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3886657886 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.pwrmgr_intr_test.3886657886
Directory /workspace/33.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.pwrmgr_intr_test.572570878
Short name T1083
Test name
Test status
Simulation time 24426072 ps
CPU time 0.62 seconds
Started Mar 28 12:43:27 PM PDT 24
Finished Mar 28 12:43:27 PM PDT 24
Peak memory 194756 kb
Host smart-a0a1f8a1-9c2b-4bd7-8689-1e6f5a985678
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=572570878 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.pwrmgr_intr_test.572570878
Directory /workspace/34.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.pwrmgr_intr_test.534134007
Short name T1025
Test name
Test status
Simulation time 17932724 ps
CPU time 0.62 seconds
Started Mar 28 12:43:24 PM PDT 24
Finished Mar 28 12:43:25 PM PDT 24
Peak memory 194756 kb
Host smart-a2a55246-1bd4-4b06-a3e7-b2910a690495
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=534134007 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.pwrmgr_intr_test.534134007
Directory /workspace/35.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.pwrmgr_intr_test.3767145582
Short name T1052
Test name
Test status
Simulation time 30689408 ps
CPU time 0.61 seconds
Started Mar 28 12:43:22 PM PDT 24
Finished Mar 28 12:43:23 PM PDT 24
Peak memory 194704 kb
Host smart-90241465-2c2b-43c4-b368-e19bc6c81894
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3767145582 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.pwrmgr_intr_test.3767145582
Directory /workspace/36.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.pwrmgr_intr_test.3804134361
Short name T1028
Test name
Test status
Simulation time 19358102 ps
CPU time 0.61 seconds
Started Mar 28 12:43:27 PM PDT 24
Finished Mar 28 12:43:28 PM PDT 24
Peak memory 194684 kb
Host smart-30cef592-81cf-4b7e-8549-58d1a1a7079b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3804134361 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.pwrmgr_intr_test.3804134361
Directory /workspace/37.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.pwrmgr_intr_test.4085343746
Short name T1016
Test name
Test status
Simulation time 23815494 ps
CPU time 0.65 seconds
Started Mar 28 12:43:25 PM PDT 24
Finished Mar 28 12:43:25 PM PDT 24
Peak memory 194684 kb
Host smart-38cb351f-e79e-43ba-8acc-c505b69e0bec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4085343746 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.pwrmgr_intr_test.4085343746
Directory /workspace/38.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.pwrmgr_intr_test.1921426986
Short name T1004
Test name
Test status
Simulation time 42764949 ps
CPU time 0.62 seconds
Started Mar 28 12:43:24 PM PDT 24
Finished Mar 28 12:43:25 PM PDT 24
Peak memory 194704 kb
Host smart-d2d2f1a4-72f0-45f2-940e-bbc24246d529
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1921426986 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.pwrmgr_intr_test.1921426986
Directory /workspace/39.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.pwrmgr_csr_aliasing.448212266
Short name T1060
Test name
Test status
Simulation time 156587739 ps
CPU time 1 seconds
Started Mar 28 12:43:10 PM PDT 24
Finished Mar 28 12:43:11 PM PDT 24
Peak memory 194596 kb
Host smart-a16213c3-5e09-47eb-b384-765f51faab69
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=448212266 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.pwrmgr_csr_aliasing.448212266
Directory /workspace/4.pwrmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.pwrmgr_csr_bit_bash.1022482935
Short name T1100
Test name
Test status
Simulation time 289664089 ps
CPU time 1.99 seconds
Started Mar 28 12:43:18 PM PDT 24
Finished Mar 28 12:43:20 PM PDT 24
Peak memory 194824 kb
Host smart-20c9c853-81d0-4ea2-b42e-0e297c329da0
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1022482935 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.pwrmgr_csr_bit_bash.1
022482935
Directory /workspace/4.pwrmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.pwrmgr_csr_hw_reset.3506908867
Short name T1091
Test name
Test status
Simulation time 50146990 ps
CPU time 0.65 seconds
Started Mar 28 12:43:10 PM PDT 24
Finished Mar 28 12:43:11 PM PDT 24
Peak memory 198032 kb
Host smart-dce098eb-2a0a-4ce7-a462-a9e7b9182e7d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3506908867 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.pwrmgr_csr_hw_reset.3
506908867
Directory /workspace/4.pwrmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.pwrmgr_csr_mem_rw_with_rand_reset.3300383672
Short name T994
Test name
Test status
Simulation time 49406790 ps
CPU time 1.12 seconds
Started Mar 28 12:43:12 PM PDT 24
Finished Mar 28 12:43:13 PM PDT 24
Peak memory 195688 kb
Host smart-3600456c-4660-4ad2-b2bb-a14c454e4840
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3300383672 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 4.pwrmgr_csr_mem_rw_with_rand_reset.3300383672
Directory /workspace/4.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.pwrmgr_csr_rw.549743251
Short name T1064
Test name
Test status
Simulation time 50038822 ps
CPU time 0.66 seconds
Started Mar 28 12:43:11 PM PDT 24
Finished Mar 28 12:43:12 PM PDT 24
Peak memory 197020 kb
Host smart-f9f89cd6-1b4c-4b19-928a-613a2d7c5002
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=549743251 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.pwrmgr_csr_rw.549743251
Directory /workspace/4.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.pwrmgr_intr_test.2778559399
Short name T1017
Test name
Test status
Simulation time 38982755 ps
CPU time 0.62 seconds
Started Mar 28 12:43:16 PM PDT 24
Finished Mar 28 12:43:17 PM PDT 24
Peak memory 194636 kb
Host smart-b94704a8-0451-431a-a313-6df9b2ef2c8f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2778559399 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.pwrmgr_intr_test.2778559399
Directory /workspace/4.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.pwrmgr_same_csr_outstanding.2426246831
Short name T1041
Test name
Test status
Simulation time 25042961 ps
CPU time 0.71 seconds
Started Mar 28 12:43:09 PM PDT 24
Finished Mar 28 12:43:10 PM PDT 24
Peak memory 194644 kb
Host smart-fc95b365-067c-4e7f-8cc4-dd1127342051
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2426246831 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.pwrmgr_sa
me_csr_outstanding.2426246831
Directory /workspace/4.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.pwrmgr_tl_errors.1754227309
Short name T1045
Test name
Test status
Simulation time 91409162 ps
CPU time 1.33 seconds
Started Mar 28 12:43:04 PM PDT 24
Finished Mar 28 12:43:06 PM PDT 24
Peak memory 195904 kb
Host smart-f5967cc7-eaa3-4d3f-bd14-d3d55a338b81
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1754227309 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.pwrmgr_tl_errors.1754227309
Directory /workspace/4.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.pwrmgr_tl_intg_err.192779957
Short name T135
Test name
Test status
Simulation time 106688959 ps
CPU time 1.13 seconds
Started Mar 28 12:43:10 PM PDT 24
Finished Mar 28 12:43:11 PM PDT 24
Peak memory 200128 kb
Host smart-d778942a-e9e6-427d-a7a9-3e3c0c3b98f1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=192779957 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.pwrmgr_tl_intg_err.
192779957
Directory /workspace/4.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.pwrmgr_intr_test.964864615
Short name T1089
Test name
Test status
Simulation time 17800885 ps
CPU time 0.65 seconds
Started Mar 28 12:43:26 PM PDT 24
Finished Mar 28 12:43:27 PM PDT 24
Peak memory 194704 kb
Host smart-a55b2058-bc16-4cb9-8411-4bf15093d69c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=964864615 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.pwrmgr_intr_test.964864615
Directory /workspace/40.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.pwrmgr_intr_test.604924990
Short name T138
Test name
Test status
Simulation time 16458081 ps
CPU time 0.58 seconds
Started Mar 28 12:43:24 PM PDT 24
Finished Mar 28 12:43:25 PM PDT 24
Peak memory 194676 kb
Host smart-cd533f8c-fe6b-42f2-aecf-40e6a154e347
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=604924990 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.pwrmgr_intr_test.604924990
Directory /workspace/41.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.pwrmgr_intr_test.1669933755
Short name T1054
Test name
Test status
Simulation time 42800310 ps
CPU time 0.57 seconds
Started Mar 28 12:43:22 PM PDT 24
Finished Mar 28 12:43:23 PM PDT 24
Peak memory 194768 kb
Host smart-4f700df5-19c4-4693-a716-278748e3e2b7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1669933755 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.pwrmgr_intr_test.1669933755
Directory /workspace/42.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.pwrmgr_intr_test.2038585721
Short name T53
Test name
Test status
Simulation time 54304549 ps
CPU time 0.61 seconds
Started Mar 28 12:43:25 PM PDT 24
Finished Mar 28 12:43:25 PM PDT 24
Peak memory 194776 kb
Host smart-09b22477-ab5a-44e7-9618-41a4b09635cc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2038585721 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.pwrmgr_intr_test.2038585721
Directory /workspace/43.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.pwrmgr_intr_test.738013230
Short name T1074
Test name
Test status
Simulation time 24246417 ps
CPU time 0.63 seconds
Started Mar 28 12:43:26 PM PDT 24
Finished Mar 28 12:43:27 PM PDT 24
Peak memory 194704 kb
Host smart-480ddb93-4194-4997-92f3-fa8947b79041
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=738013230 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.pwrmgr_intr_test.738013230
Directory /workspace/44.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.pwrmgr_intr_test.1223999471
Short name T1037
Test name
Test status
Simulation time 19785848 ps
CPU time 0.62 seconds
Started Mar 28 12:43:24 PM PDT 24
Finished Mar 28 12:43:25 PM PDT 24
Peak memory 194680 kb
Host smart-ec78f27c-5f30-4e68-b447-bd8e5c889400
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1223999471 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.pwrmgr_intr_test.1223999471
Directory /workspace/45.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.pwrmgr_intr_test.460719079
Short name T1035
Test name
Test status
Simulation time 20951649 ps
CPU time 0.66 seconds
Started Mar 28 12:43:28 PM PDT 24
Finished Mar 28 12:43:29 PM PDT 24
Peak memory 194776 kb
Host smart-9df097d6-bcdf-45e4-b4fc-03ad1c7d7ae0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=460719079 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.pwrmgr_intr_test.460719079
Directory /workspace/46.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.pwrmgr_intr_test.1201875004
Short name T1013
Test name
Test status
Simulation time 44720804 ps
CPU time 0.59 seconds
Started Mar 28 12:43:25 PM PDT 24
Finished Mar 28 12:43:25 PM PDT 24
Peak memory 194772 kb
Host smart-1c49c941-0656-4404-9934-583b9fceb694
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1201875004 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.pwrmgr_intr_test.1201875004
Directory /workspace/47.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.pwrmgr_intr_test.3236518842
Short name T1065
Test name
Test status
Simulation time 22795713 ps
CPU time 0.61 seconds
Started Mar 28 12:43:27 PM PDT 24
Finished Mar 28 12:43:28 PM PDT 24
Peak memory 194684 kb
Host smart-119088bf-1e38-477c-9176-6ea546f4a4a0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3236518842 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.pwrmgr_intr_test.3236518842
Directory /workspace/48.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.pwrmgr_csr_mem_rw_with_rand_reset.2660008207
Short name T1030
Test name
Test status
Simulation time 44938796 ps
CPU time 1.2 seconds
Started Mar 28 12:43:06 PM PDT 24
Finished Mar 28 12:43:07 PM PDT 24
Peak memory 196864 kb
Host smart-6ded6d6a-9eca-4048-84a3-a41df3b10cb9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2660008207 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 5.pwrmgr_csr_mem_rw_with_rand_reset.2660008207
Directory /workspace/5.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.pwrmgr_csr_rw.4122339091
Short name T47
Test name
Test status
Simulation time 19379547 ps
CPU time 0.66 seconds
Started Mar 28 12:43:14 PM PDT 24
Finished Mar 28 12:43:15 PM PDT 24
Peak memory 197828 kb
Host smart-3251ea98-f8d2-4097-9237-7595f6ef0247
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4122339091 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.pwrmgr_csr_rw.4122339091
Directory /workspace/5.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.pwrmgr_intr_test.4101592319
Short name T1108
Test name
Test status
Simulation time 72643454 ps
CPU time 0.6 seconds
Started Mar 28 12:43:06 PM PDT 24
Finished Mar 28 12:43:07 PM PDT 24
Peak memory 194560 kb
Host smart-54dae602-7c51-4930-b2dd-02588730e7bb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4101592319 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.pwrmgr_intr_test.4101592319
Directory /workspace/5.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.pwrmgr_same_csr_outstanding.2844667326
Short name T1055
Test name
Test status
Simulation time 56884701 ps
CPU time 0.69 seconds
Started Mar 28 12:43:10 PM PDT 24
Finished Mar 28 12:43:11 PM PDT 24
Peak memory 194704 kb
Host smart-5be096f0-b363-45c8-9b61-9ecf35b51fd2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2844667326 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.pwrmgr_sa
me_csr_outstanding.2844667326
Directory /workspace/5.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.pwrmgr_tl_errors.3037827343
Short name T1032
Test name
Test status
Simulation time 42606531 ps
CPU time 2.04 seconds
Started Mar 28 12:43:10 PM PDT 24
Finished Mar 28 12:43:13 PM PDT 24
Peak memory 196020 kb
Host smart-20fff300-2bbf-4eb7-837a-099b0d7f71a3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3037827343 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.pwrmgr_tl_errors.3037827343
Directory /workspace/5.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.pwrmgr_tl_intg_err.2195998451
Short name T137
Test name
Test status
Simulation time 285414437 ps
CPU time 1.11 seconds
Started Mar 28 12:43:13 PM PDT 24
Finished Mar 28 12:43:14 PM PDT 24
Peak memory 194760 kb
Host smart-7d9e7e13-f832-49ee-872d-24fd8eabbd1a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2195998451 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.pwrmgr_tl_intg_err
.2195998451
Directory /workspace/5.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.pwrmgr_csr_mem_rw_with_rand_reset.3120994259
Short name T1066
Test name
Test status
Simulation time 53363088 ps
CPU time 0.93 seconds
Started Mar 28 12:43:13 PM PDT 24
Finished Mar 28 12:43:15 PM PDT 24
Peak memory 194776 kb
Host smart-cde535ac-e0d0-4460-b130-eac23c64b030
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3120994259 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 6.pwrmgr_csr_mem_rw_with_rand_reset.3120994259
Directory /workspace/6.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.pwrmgr_csr_rw.1634756620
Short name T96
Test name
Test status
Simulation time 30235322 ps
CPU time 0.61 seconds
Started Mar 28 12:43:09 PM PDT 24
Finished Mar 28 12:43:09 PM PDT 24
Peak memory 194816 kb
Host smart-555cbcae-1307-4607-9017-58ab19d19f8b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1634756620 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.pwrmgr_csr_rw.1634756620
Directory /workspace/6.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.pwrmgr_intr_test.2333481603
Short name T55
Test name
Test status
Simulation time 17924990 ps
CPU time 0.62 seconds
Started Mar 28 12:43:17 PM PDT 24
Finished Mar 28 12:43:18 PM PDT 24
Peak memory 194668 kb
Host smart-d35a0685-42a4-4047-82fe-9cefae28fe31
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2333481603 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.pwrmgr_intr_test.2333481603
Directory /workspace/6.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.pwrmgr_same_csr_outstanding.2651504437
Short name T1026
Test name
Test status
Simulation time 73486673 ps
CPU time 0.73 seconds
Started Mar 28 12:43:23 PM PDT 24
Finished Mar 28 12:43:24 PM PDT 24
Peak memory 196808 kb
Host smart-68051c50-a108-4c97-919b-6a0a65d89ae9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2651504437 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.pwrmgr_sa
me_csr_outstanding.2651504437
Directory /workspace/6.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.pwrmgr_tl_errors.3156307098
Short name T1099
Test name
Test status
Simulation time 168716626 ps
CPU time 1.18 seconds
Started Mar 28 12:43:07 PM PDT 24
Finished Mar 28 12:43:08 PM PDT 24
Peak memory 196676 kb
Host smart-c27dde12-fcd8-4117-b2d1-6d33f005f1cd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3156307098 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.pwrmgr_tl_errors.3156307098
Directory /workspace/6.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.pwrmgr_tl_intg_err.1990364383
Short name T1019
Test name
Test status
Simulation time 237815196 ps
CPU time 1.08 seconds
Started Mar 28 12:43:17 PM PDT 24
Finished Mar 28 12:43:18 PM PDT 24
Peak memory 200028 kb
Host smart-bf357b52-1022-4de1-af28-7f1cfadec156
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1990364383 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.pwrmgr_tl_intg_err
.1990364383
Directory /workspace/6.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.pwrmgr_csr_mem_rw_with_rand_reset.3517895696
Short name T1058
Test name
Test status
Simulation time 237159306 ps
CPU time 0.85 seconds
Started Mar 28 12:43:22 PM PDT 24
Finished Mar 28 12:43:23 PM PDT 24
Peak memory 194780 kb
Host smart-fd64a6cb-d355-4a08-9a74-a0a669ced24e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3517895696 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 7.pwrmgr_csr_mem_rw_with_rand_reset.3517895696
Directory /workspace/7.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.pwrmgr_csr_rw.3900227111
Short name T1069
Test name
Test status
Simulation time 20610647 ps
CPU time 0.66 seconds
Started Mar 28 12:43:02 PM PDT 24
Finished Mar 28 12:43:03 PM PDT 24
Peak memory 194664 kb
Host smart-ef65d277-fccc-49ad-a3f9-c98cdf9ee220
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3900227111 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.pwrmgr_csr_rw.3900227111
Directory /workspace/7.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.pwrmgr_intr_test.2893009941
Short name T1106
Test name
Test status
Simulation time 36106031 ps
CPU time 0.62 seconds
Started Mar 28 12:43:17 PM PDT 24
Finished Mar 28 12:43:18 PM PDT 24
Peak memory 194656 kb
Host smart-c7d93363-c71a-42c9-8297-18dfdc96ad7f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2893009941 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.pwrmgr_intr_test.2893009941
Directory /workspace/7.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.pwrmgr_same_csr_outstanding.3564491063
Short name T1093
Test name
Test status
Simulation time 90110996 ps
CPU time 0.87 seconds
Started Mar 28 12:43:02 PM PDT 24
Finished Mar 28 12:43:03 PM PDT 24
Peak memory 197976 kb
Host smart-3693ebed-169f-47a0-b826-2a2d2ffa5a55
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3564491063 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.pwrmgr_sa
me_csr_outstanding.3564491063
Directory /workspace/7.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.pwrmgr_tl_errors.827547429
Short name T1015
Test name
Test status
Simulation time 97954169 ps
CPU time 1.15 seconds
Started Mar 28 12:43:12 PM PDT 24
Finished Mar 28 12:43:13 PM PDT 24
Peak memory 196748 kb
Host smart-d4ff4219-52be-4ec0-8aa4-1c07814d66fa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=827547429 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.pwrmgr_tl_errors.827547429
Directory /workspace/7.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.pwrmgr_tl_intg_err.626420049
Short name T134
Test name
Test status
Simulation time 111692998 ps
CPU time 1.28 seconds
Started Mar 28 12:43:21 PM PDT 24
Finished Mar 28 12:43:23 PM PDT 24
Peak memory 200000 kb
Host smart-aaa1cdfd-8650-4764-818c-9b2e2dc4b00f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=626420049 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.pwrmgr_tl_intg_err.
626420049
Directory /workspace/7.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.pwrmgr_csr_mem_rw_with_rand_reset.109628130
Short name T1056
Test name
Test status
Simulation time 87945537 ps
CPU time 1.14 seconds
Started Mar 28 12:43:07 PM PDT 24
Finished Mar 28 12:43:08 PM PDT 24
Peak memory 195032 kb
Host smart-ce136dd6-c2a7-4c40-bbab-c81c844beab0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109628130 -assert nopostproc +UVM_TESTNAME=
pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 8.pwrmgr_csr_mem_rw_with_rand_reset.109628130
Directory /workspace/8.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.pwrmgr_csr_rw.4254488206
Short name T90
Test name
Test status
Simulation time 50370495 ps
CPU time 0.61 seconds
Started Mar 28 12:42:58 PM PDT 24
Finished Mar 28 12:42:59 PM PDT 24
Peak memory 194720 kb
Host smart-d7cb5a51-494b-4db9-b111-d0c262e5f863
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4254488206 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.pwrmgr_csr_rw.4254488206
Directory /workspace/8.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.pwrmgr_intr_test.941671581
Short name T1049
Test name
Test status
Simulation time 35598343 ps
CPU time 0.58 seconds
Started Mar 28 12:43:12 PM PDT 24
Finished Mar 28 12:43:13 PM PDT 24
Peak memory 194628 kb
Host smart-08d634a7-1710-4b04-b65c-ddcd3f24f922
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=941671581 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.pwrmgr_intr_test.941671581
Directory /workspace/8.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.pwrmgr_same_csr_outstanding.3488734373
Short name T1042
Test name
Test status
Simulation time 22151817 ps
CPU time 0.84 seconds
Started Mar 28 12:43:07 PM PDT 24
Finished Mar 28 12:43:08 PM PDT 24
Peak memory 197952 kb
Host smart-7b3ae7b1-6238-4a50-9f3d-706f219d6946
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3488734373 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.pwrmgr_sa
me_csr_outstanding.3488734373
Directory /workspace/8.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.pwrmgr_tl_errors.2906176399
Short name T1088
Test name
Test status
Simulation time 466648001 ps
CPU time 2.69 seconds
Started Mar 28 12:43:17 PM PDT 24
Finished Mar 28 12:43:20 PM PDT 24
Peak memory 196928 kb
Host smart-6dc6f005-fcb0-4cc7-8be5-2e62361ddd55
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2906176399 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.pwrmgr_tl_errors.2906176399
Directory /workspace/8.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.pwrmgr_tl_intg_err.219440863
Short name T1029
Test name
Test status
Simulation time 100940370 ps
CPU time 1.09 seconds
Started Mar 28 12:42:58 PM PDT 24
Finished Mar 28 12:42:59 PM PDT 24
Peak memory 194684 kb
Host smart-0fb149fb-8101-4d44-ad80-125b6e5a667a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=219440863 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.pwrmgr_tl_intg_err.
219440863
Directory /workspace/8.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.pwrmgr_csr_mem_rw_with_rand_reset.3085122781
Short name T50
Test name
Test status
Simulation time 106082842 ps
CPU time 1.26 seconds
Started Mar 28 12:43:01 PM PDT 24
Finished Mar 28 12:43:02 PM PDT 24
Peak memory 197520 kb
Host smart-cddfae0d-6f2d-4690-8abf-ec3a387c065a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3085122781 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 9.pwrmgr_csr_mem_rw_with_rand_reset.3085122781
Directory /workspace/9.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.pwrmgr_csr_rw.2597213827
Short name T100
Test name
Test status
Simulation time 28964544 ps
CPU time 0.59 seconds
Started Mar 28 12:43:07 PM PDT 24
Finished Mar 28 12:43:08 PM PDT 24
Peak memory 194672 kb
Host smart-cf4d9243-249a-45c0-a13c-0308ef677ed1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2597213827 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.pwrmgr_csr_rw.2597213827
Directory /workspace/9.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.pwrmgr_intr_test.1275952731
Short name T1094
Test name
Test status
Simulation time 19103104 ps
CPU time 0.62 seconds
Started Mar 28 12:43:08 PM PDT 24
Finished Mar 28 12:43:09 PM PDT 24
Peak memory 194692 kb
Host smart-fe58568e-06bd-4a80-b0c0-606e8558a43b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1275952731 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.pwrmgr_intr_test.1275952731
Directory /workspace/9.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.pwrmgr_same_csr_outstanding.3064599495
Short name T101
Test name
Test status
Simulation time 105802418 ps
CPU time 0.87 seconds
Started Mar 28 12:43:09 PM PDT 24
Finished Mar 28 12:43:11 PM PDT 24
Peak memory 197968 kb
Host smart-9c1b5280-6587-403e-a44b-8fb6ba53bc02
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3064599495 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.pwrmgr_sa
me_csr_outstanding.3064599495
Directory /workspace/9.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.pwrmgr_tl_errors.3206672085
Short name T1023
Test name
Test status
Simulation time 204335666 ps
CPU time 2.41 seconds
Started Mar 28 12:43:04 PM PDT 24
Finished Mar 28 12:43:07 PM PDT 24
Peak memory 197020 kb
Host smart-2748f50b-d5e4-4a1d-b6e3-9a13d73e0957
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3206672085 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.pwrmgr_tl_errors.3206672085
Directory /workspace/9.pwrmgr_tl_errors/latest

Test location /workspace/coverage/default/0.pwrmgr_aborted_low_power.3200342468
Short name T542
Test name
Test status
Simulation time 49503257 ps
CPU time 0.68 seconds
Started Mar 28 01:21:26 PM PDT 24
Finished Mar 28 01:21:27 PM PDT 24
Peak memory 198344 kb
Host smart-6785f233-0341-40ba-af02-0a78edd74c86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3200342468 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_aborted_low_power.3200342468
Directory /workspace/0.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/0.pwrmgr_esc_clk_rst_malfunc.1170014488
Short name T907
Test name
Test status
Simulation time 34005585 ps
CPU time 0.62 seconds
Started Mar 28 01:21:31 PM PDT 24
Finished Mar 28 01:21:31 PM PDT 24
Peak memory 197408 kb
Host smart-28b7b779-382a-460c-8828-3f594843583d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1170014488 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_esc_clk_rst_
malfunc.1170014488
Directory /workspace/0.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/0.pwrmgr_escalation_timeout.625867278
Short name T695
Test name
Test status
Simulation time 166438218 ps
CPU time 0.93 seconds
Started Mar 28 01:21:32 PM PDT 24
Finished Mar 28 01:21:33 PM PDT 24
Peak memory 197408 kb
Host smart-c205c74a-af98-4945-a8d0-e8ca1be71a7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=625867278 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_escalation_timeout.625867278
Directory /workspace/0.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/0.pwrmgr_glitch.4056291519
Short name T366
Test name
Test status
Simulation time 40193676 ps
CPU time 0.67 seconds
Started Mar 28 01:21:34 PM PDT 24
Finished Mar 28 01:21:35 PM PDT 24
Peak memory 196700 kb
Host smart-246726f3-e6c0-4eef-9adf-ef1d811e7f67
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4056291519 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_glitch.4056291519
Directory /workspace/0.pwrmgr_glitch/latest

Test location /workspace/coverage/default/0.pwrmgr_global_esc.4002169970
Short name T777
Test name
Test status
Simulation time 25542761 ps
CPU time 0.61 seconds
Started Mar 28 01:21:32 PM PDT 24
Finished Mar 28 01:21:33 PM PDT 24
Peak memory 197716 kb
Host smart-9a8f51c9-2bb5-4583-a0eb-c431ff552aed
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4002169970 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_global_esc.4002169970
Directory /workspace/0.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/0.pwrmgr_lowpower_invalid.4225269888
Short name T975
Test name
Test status
Simulation time 45348729 ps
CPU time 0.72 seconds
Started Mar 28 01:21:35 PM PDT 24
Finished Mar 28 01:21:35 PM PDT 24
Peak memory 200544 kb
Host smart-8a3e15f7-5d8a-46a6-b776-16c70be1cd99
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4225269888 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_lowpower_invali
d.4225269888
Directory /workspace/0.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/0.pwrmgr_lowpower_wakeup_race.73648382
Short name T973
Test name
Test status
Simulation time 224043100 ps
CPU time 1.15 seconds
Started Mar 28 01:21:32 PM PDT 24
Finished Mar 28 01:21:34 PM PDT 24
Peak memory 198944 kb
Host smart-3951b3c9-b775-4ac8-b9ed-ef443fa592b1
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73648382 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup
_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_lowpower_wake
up_race.73648382
Directory /workspace/0.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/0.pwrmgr_reset.1662757296
Short name T884
Test name
Test status
Simulation time 61422038 ps
CPU time 0.96 seconds
Started Mar 28 01:21:31 PM PDT 24
Finished Mar 28 01:21:32 PM PDT 24
Peak memory 199108 kb
Host smart-fbea3b31-0d11-41f2-afa6-0b406495e606
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1662757296 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_reset.1662757296
Directory /workspace/0.pwrmgr_reset/latest

Test location /workspace/coverage/default/0.pwrmgr_reset_invalid.1054824733
Short name T575
Test name
Test status
Simulation time 123701052 ps
CPU time 0.87 seconds
Started Mar 28 01:21:31 PM PDT 24
Finished Mar 28 01:21:32 PM PDT 24
Peak memory 200640 kb
Host smart-9a9c18b2-c199-44da-bb49-9fff5b64d9c7
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1054824733 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_reset_invalid.1054824733
Directory /workspace/0.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/0.pwrmgr_sec_cm.4106137179
Short name T16
Test name
Test status
Simulation time 658822532 ps
CPU time 2.18 seconds
Started Mar 28 01:21:44 PM PDT 24
Finished Mar 28 01:21:47 PM PDT 24
Peak memory 216524 kb
Host smart-365a5ceb-4e05-456d-93e6-26294961465d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4106137179 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_sec_cm.4106137179
Directory /workspace/0.pwrmgr_sec_cm/latest

Test location /workspace/coverage/default/0.pwrmgr_sec_cm_ctrl_config_regwen.2688923016
Short name T517
Test name
Test status
Simulation time 183371696 ps
CPU time 1.05 seconds
Started Mar 28 01:21:31 PM PDT 24
Finished Mar 28 01:21:33 PM PDT 24
Peak memory 199344 kb
Host smart-34ce10d4-993e-4c3a-b201-5f250d8b310b
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2688923016 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_sec_c
m_ctrl_config_regwen.2688923016
Directory /workspace/0.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/0.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2086675413
Short name T129
Test name
Test status
Simulation time 1224893748 ps
CPU time 2.23 seconds
Started Mar 28 01:21:29 PM PDT 24
Finished Mar 28 01:21:31 PM PDT 24
Peak memory 200516 kb
Host smart-4730c77e-757b-4dcb-94a3-24a2fcf53077
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2086675413 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 0.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2086675413
Directory /workspace/0.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/0.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3560219933
Short name T826
Test name
Test status
Simulation time 1238877290 ps
CPU time 2.29 seconds
Started Mar 28 01:21:28 PM PDT 24
Finished Mar 28 01:21:31 PM PDT 24
Peak memory 200444 kb
Host smart-53e63c81-e8de-43b4-901b-3bba731ee38a
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3560219933 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 0.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3560219933
Directory /workspace/0.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/0.pwrmgr_sec_cm_rstmgr_intersig_mubi.2023992559
Short name T756
Test name
Test status
Simulation time 154857659 ps
CPU time 0.88 seconds
Started Mar 28 01:21:29 PM PDT 24
Finished Mar 28 01:21:30 PM PDT 24
Peak memory 198440 kb
Host smart-fa8a8362-05de-45df-bfb6-678f7a9a68d2
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2023992559 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_sec_cm_rstmgr_intersig_
mubi.2023992559
Directory /workspace/0.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/0.pwrmgr_smoke.2550521884
Short name T867
Test name
Test status
Simulation time 40884512 ps
CPU time 0.64 seconds
Started Mar 28 01:21:30 PM PDT 24
Finished Mar 28 01:21:30 PM PDT 24
Peak memory 197808 kb
Host smart-6e88fd64-3c5c-4324-a0a5-f30c39ecbc9a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2550521884 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_smoke.2550521884
Directory /workspace/0.pwrmgr_smoke/latest

Test location /workspace/coverage/default/0.pwrmgr_stress_all_with_rand_reset.922363224
Short name T113
Test name
Test status
Simulation time 10897260699 ps
CPU time 35.63 seconds
Started Mar 28 01:21:47 PM PDT 24
Finished Mar 28 01:22:23 PM PDT 24
Peak memory 200872 kb
Host smart-668f8b2c-d99f-413b-9349-765067224392
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=922363224 -assert nopost
proc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 0.pwrmgr_stress_all_with_rand_reset.922363224
Directory /workspace/0.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.pwrmgr_wakeup.1984716201
Short name T699
Test name
Test status
Simulation time 268008544 ps
CPU time 0.94 seconds
Started Mar 28 01:21:28 PM PDT 24
Finished Mar 28 01:21:30 PM PDT 24
Peak memory 199060 kb
Host smart-3121a1aa-8bac-431c-ab82-1682db1f9f20
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1984716201 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_wakeup.1984716201
Directory /workspace/0.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/0.pwrmgr_wakeup_reset.1124579775
Short name T117
Test name
Test status
Simulation time 290188006 ps
CPU time 1.42 seconds
Started Mar 28 01:21:29 PM PDT 24
Finished Mar 28 01:21:30 PM PDT 24
Peak memory 200492 kb
Host smart-ed1bb79b-c4f2-42cb-bdc6-364b4d4fc6e9
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1124579775 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_wakeup_reset.1124579775
Directory /workspace/0.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/1.pwrmgr_aborted_low_power.4177986462
Short name T357
Test name
Test status
Simulation time 39322161 ps
CPU time 0.85 seconds
Started Mar 28 01:21:44 PM PDT 24
Finished Mar 28 01:21:45 PM PDT 24
Peak memory 199280 kb
Host smart-dc0a242b-8155-48a5-a898-2770c7cdf2e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4177986462 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_aborted_low_power.4177986462
Directory /workspace/1.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/1.pwrmgr_esc_clk_rst_malfunc.195745210
Short name T383
Test name
Test status
Simulation time 46106743 ps
CPU time 0.64 seconds
Started Mar 28 01:21:45 PM PDT 24
Finished Mar 28 01:21:45 PM PDT 24
Peak memory 196644 kb
Host smart-83c2ce47-eb6d-48a8-8bd4-c1100cd7d023
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=195745210 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_ma
lfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_esc_clk_rst_m
alfunc.195745210
Directory /workspace/1.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/1.pwrmgr_escalation_timeout.4027802353
Short name T471
Test name
Test status
Simulation time 307484960 ps
CPU time 0.96 seconds
Started Mar 28 01:21:54 PM PDT 24
Finished Mar 28 01:21:55 PM PDT 24
Peak memory 197388 kb
Host smart-39e4d637-1197-4e8e-8c2f-9f42bda6dfdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4027802353 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_escalation_timeout.4027802353
Directory /workspace/1.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/1.pwrmgr_glitch.3228025005
Short name T638
Test name
Test status
Simulation time 47176923 ps
CPU time 0.67 seconds
Started Mar 28 01:21:46 PM PDT 24
Finished Mar 28 01:21:46 PM PDT 24
Peak memory 197388 kb
Host smart-91b1b291-bf83-4866-97fa-9def305c173c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3228025005 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_glitch.3228025005
Directory /workspace/1.pwrmgr_glitch/latest

Test location /workspace/coverage/default/1.pwrmgr_global_esc.2780251824
Short name T852
Test name
Test status
Simulation time 45703533 ps
CPU time 0.63 seconds
Started Mar 28 01:21:44 PM PDT 24
Finished Mar 28 01:21:45 PM PDT 24
Peak memory 197456 kb
Host smart-c2383d9e-2266-4f6c-b019-3e039aafacbb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2780251824 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_global_esc.2780251824
Directory /workspace/1.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/1.pwrmgr_lowpower_invalid.3548256317
Short name T746
Test name
Test status
Simulation time 86437490 ps
CPU time 0.67 seconds
Started Mar 28 01:21:45 PM PDT 24
Finished Mar 28 01:21:46 PM PDT 24
Peak memory 200696 kb
Host smart-202d840f-d7fd-4110-93cc-cd5393c1bc7b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3548256317 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_lowpower_invali
d.3548256317
Directory /workspace/1.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/1.pwrmgr_lowpower_wakeup_race.4189484514
Short name T955
Test name
Test status
Simulation time 174532217 ps
CPU time 1 seconds
Started Mar 28 01:21:44 PM PDT 24
Finished Mar 28 01:21:45 PM PDT 24
Peak memory 199076 kb
Host smart-fb78860a-b20a-4c02-9412-619a40f51e36
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4189484514 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_lowpower_wa
keup_race.4189484514
Directory /workspace/1.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/1.pwrmgr_reset.3125443146
Short name T574
Test name
Test status
Simulation time 82159060 ps
CPU time 0.98 seconds
Started Mar 28 01:21:46 PM PDT 24
Finished Mar 28 01:21:47 PM PDT 24
Peak memory 199348 kb
Host smart-fb4d933d-9099-42c3-8a7f-e37b1fa4040b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3125443146 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_reset.3125443146
Directory /workspace/1.pwrmgr_reset/latest

Test location /workspace/coverage/default/1.pwrmgr_reset_invalid.3371133228
Short name T604
Test name
Test status
Simulation time 197708509 ps
CPU time 0.76 seconds
Started Mar 28 01:21:44 PM PDT 24
Finished Mar 28 01:21:45 PM PDT 24
Peak memory 208672 kb
Host smart-20d523d1-084f-4531-8c97-7ddf48ea8bac
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3371133228 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_reset_invalid.3371133228
Directory /workspace/1.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/1.pwrmgr_sec_cm_ctrl_config_regwen.1973782257
Short name T392
Test name
Test status
Simulation time 174171231 ps
CPU time 1.19 seconds
Started Mar 28 01:21:46 PM PDT 24
Finished Mar 28 01:21:48 PM PDT 24
Peak memory 199216 kb
Host smart-63bfdc3c-27c4-430e-bf31-e68b99e12cda
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1973782257 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_sec_c
m_ctrl_config_regwen.1973782257
Directory /workspace/1.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/1.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2222494561
Short name T780
Test name
Test status
Simulation time 1166067097 ps
CPU time 2.1 seconds
Started Mar 28 01:21:46 PM PDT 24
Finished Mar 28 01:21:49 PM PDT 24
Peak memory 200452 kb
Host smart-3b9356e6-ce5b-43d5-b5c4-2e170c0913d0
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2222494561 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 1.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2222494561
Directory /workspace/1.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/1.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1786342017
Short name T665
Test name
Test status
Simulation time 842665633 ps
CPU time 3.17 seconds
Started Mar 28 01:21:44 PM PDT 24
Finished Mar 28 01:21:47 PM PDT 24
Peak memory 200532 kb
Host smart-f3bdda0e-4337-4450-bdc1-14168478a2dd
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1786342017 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 1.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1786342017
Directory /workspace/1.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/1.pwrmgr_sec_cm_rstmgr_intersig_mubi.27222947
Short name T668
Test name
Test status
Simulation time 73526048 ps
CPU time 1.01 seconds
Started Mar 28 01:21:53 PM PDT 24
Finished Mar 28 01:21:55 PM PDT 24
Peak memory 198664 kb
Host smart-e7593a25-2ab1-4a99-bb24-90a52a49f6e2
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27222947 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_sec_cm_rstmgr_intersig_mu
bi.27222947
Directory /workspace/1.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/1.pwrmgr_smoke.1162889620
Short name T843
Test name
Test status
Simulation time 62094334 ps
CPU time 0.66 seconds
Started Mar 28 01:21:54 PM PDT 24
Finished Mar 28 01:21:55 PM PDT 24
Peak memory 197764 kb
Host smart-74fdcef7-2bca-40ef-bd8a-82cd9fedb9a7
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1162889620 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_smoke.1162889620
Directory /workspace/1.pwrmgr_smoke/latest

Test location /workspace/coverage/default/1.pwrmgr_stress_all.3721919720
Short name T875
Test name
Test status
Simulation time 581664415 ps
CPU time 2.54 seconds
Started Mar 28 01:21:46 PM PDT 24
Finished Mar 28 01:21:49 PM PDT 24
Peak memory 200560 kb
Host smart-31c7dd71-07f3-4f58-9810-0837211b6e5e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3721919720 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_stress_all.3721919720
Directory /workspace/1.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/1.pwrmgr_stress_all_with_rand_reset.1668846299
Short name T745
Test name
Test status
Simulation time 2967857496 ps
CPU time 11.8 seconds
Started Mar 28 01:21:54 PM PDT 24
Finished Mar 28 01:22:06 PM PDT 24
Peak memory 200788 kb
Host smart-d3152805-a8d3-4fa2-bce7-bef04d823191
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1668846299 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 1.pwrmgr_stress_all_with_rand_reset.1668846299
Directory /workspace/1.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.pwrmgr_wakeup.1383652777
Short name T623
Test name
Test status
Simulation time 666840308 ps
CPU time 0.9 seconds
Started Mar 28 01:21:45 PM PDT 24
Finished Mar 28 01:21:46 PM PDT 24
Peak memory 198784 kb
Host smart-2a1b3464-138a-475d-becf-14da21da1dcc
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1383652777 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_wakeup.1383652777
Directory /workspace/1.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/1.pwrmgr_wakeup_reset.4003329877
Short name T289
Test name
Test status
Simulation time 309959332 ps
CPU time 1.39 seconds
Started Mar 28 01:21:53 PM PDT 24
Finished Mar 28 01:21:55 PM PDT 24
Peak memory 200408 kb
Host smart-2bb12795-9749-4f18-8c4c-c2464f724abf
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4003329877 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_wakeup_reset.4003329877
Directory /workspace/1.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/10.pwrmgr_aborted_low_power.3098727094
Short name T294
Test name
Test status
Simulation time 41978254 ps
CPU time 0.91 seconds
Started Mar 28 01:23:18 PM PDT 24
Finished Mar 28 01:23:18 PM PDT 24
Peak memory 200164 kb
Host smart-008b9c7c-0301-470c-b06d-3e6869c7af97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3098727094 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_aborted_low_power.3098727094
Directory /workspace/10.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/10.pwrmgr_disable_rom_integrity_check.2459261999
Short name T678
Test name
Test status
Simulation time 64862837 ps
CPU time 0.82 seconds
Started Mar 28 01:23:18 PM PDT 24
Finished Mar 28 01:23:19 PM PDT 24
Peak memory 198488 kb
Host smart-ae8473d6-8ccc-421c-9db8-519bb16ffd87
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2459261999 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_dis
able_rom_integrity_check.2459261999
Directory /workspace/10.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/10.pwrmgr_esc_clk_rst_malfunc.3468943386
Short name T690
Test name
Test status
Simulation time 49973286 ps
CPU time 0.59 seconds
Started Mar 28 01:23:21 PM PDT 24
Finished Mar 28 01:23:22 PM PDT 24
Peak memory 197296 kb
Host smart-764a165f-25e1-4dac-8fd8-37f616773e71
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3468943386 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_esc_clk_rst
_malfunc.3468943386
Directory /workspace/10.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/10.pwrmgr_escalation_timeout.4250223999
Short name T846
Test name
Test status
Simulation time 159998790 ps
CPU time 1.02 seconds
Started Mar 28 01:23:20 PM PDT 24
Finished Mar 28 01:23:21 PM PDT 24
Peak memory 197452 kb
Host smart-0afcc726-e02c-4a66-a41d-f7bd7bc5c8e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4250223999 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_escalation_timeout.4250223999
Directory /workspace/10.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/10.pwrmgr_glitch.2829315069
Short name T476
Test name
Test status
Simulation time 69028966 ps
CPU time 0.62 seconds
Started Mar 28 01:23:24 PM PDT 24
Finished Mar 28 01:23:25 PM PDT 24
Peak memory 197272 kb
Host smart-0b738558-a602-4c8d-904e-1dda6967041c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2829315069 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_glitch.2829315069
Directory /workspace/10.pwrmgr_glitch/latest

Test location /workspace/coverage/default/10.pwrmgr_global_esc.514301687
Short name T168
Test name
Test status
Simulation time 40005170 ps
CPU time 0.59 seconds
Started Mar 28 01:23:20 PM PDT 24
Finished Mar 28 01:23:20 PM PDT 24
Peak memory 197372 kb
Host smart-f2abb57a-273a-4b7c-89f9-e69431c033f2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=514301687 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_global_esc.514301687
Directory /workspace/10.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/10.pwrmgr_lowpower_invalid.2671178901
Short name T981
Test name
Test status
Simulation time 76602279 ps
CPU time 0.66 seconds
Started Mar 28 01:23:20 PM PDT 24
Finished Mar 28 01:23:20 PM PDT 24
Peak memory 200748 kb
Host smart-f83302c8-aa3a-4397-a884-dcf0b848c8ba
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2671178901 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_lowpower_inval
id.2671178901
Directory /workspace/10.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/10.pwrmgr_lowpower_wakeup_race.418578074
Short name T683
Test name
Test status
Simulation time 78528944 ps
CPU time 0.82 seconds
Started Mar 28 01:23:21 PM PDT 24
Finished Mar 28 01:23:22 PM PDT 24
Peak memory 198420 kb
Host smart-121dae6e-31b1-4909-a486-ddbf383cc0d1
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=418578074 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeu
p_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_lowpower_wa
keup_race.418578074
Directory /workspace/10.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/10.pwrmgr_reset.957360576
Short name T267
Test name
Test status
Simulation time 209689741 ps
CPU time 0.77 seconds
Started Mar 28 01:23:19 PM PDT 24
Finished Mar 28 01:23:19 PM PDT 24
Peak memory 198080 kb
Host smart-2eeb710f-3161-43a1-af9b-31eef44c5f1c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=957360576 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_reset.957360576
Directory /workspace/10.pwrmgr_reset/latest

Test location /workspace/coverage/default/10.pwrmgr_reset_invalid.1189549359
Short name T588
Test name
Test status
Simulation time 159434557 ps
CPU time 0.88 seconds
Started Mar 28 01:23:18 PM PDT 24
Finished Mar 28 01:23:19 PM PDT 24
Peak memory 208884 kb
Host smart-1b13d0a3-dc94-4482-ae45-cfa6da53caf3
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1189549359 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_reset_invalid.1189549359
Directory /workspace/10.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/10.pwrmgr_sec_cm_ctrl_config_regwen.4096013028
Short name T815
Test name
Test status
Simulation time 298179922 ps
CPU time 1.13 seconds
Started Mar 28 01:23:18 PM PDT 24
Finished Mar 28 01:23:19 PM PDT 24
Peak memory 200232 kb
Host smart-943cd244-deb8-402e-abd0-abd9ce4baecd
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4096013028 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_sec_
cm_ctrl_config_regwen.4096013028
Directory /workspace/10.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/10.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1164631663
Short name T234
Test name
Test status
Simulation time 1273773539 ps
CPU time 2.3 seconds
Started Mar 28 01:23:20 PM PDT 24
Finished Mar 28 01:23:22 PM PDT 24
Peak memory 200500 kb
Host smart-40dfb20e-5309-4181-83c9-33c12ba9f004
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1164631663 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 10.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1164631663
Directory /workspace/10.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/10.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1681577281
Short name T380
Test name
Test status
Simulation time 801143088 ps
CPU time 3.37 seconds
Started Mar 28 01:23:24 PM PDT 24
Finished Mar 28 01:23:28 PM PDT 24
Peak memory 200472 kb
Host smart-1e63bc6c-4535-4268-abc7-bb27bda6c192
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1681577281 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 10.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1681577281
Directory /workspace/10.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/10.pwrmgr_sec_cm_rstmgr_intersig_mubi.2085331247
Short name T434
Test name
Test status
Simulation time 52226758 ps
CPU time 0.95 seconds
Started Mar 28 01:23:18 PM PDT 24
Finished Mar 28 01:23:19 PM PDT 24
Peak memory 198612 kb
Host smart-261cece8-3fb1-44b7-b5f1-00a8ca7a53a9
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2085331247 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_sec_cm_rstmgr_intersig
_mubi.2085331247
Directory /workspace/10.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/10.pwrmgr_smoke.2815683746
Short name T504
Test name
Test status
Simulation time 51811879 ps
CPU time 0.61 seconds
Started Mar 28 01:23:20 PM PDT 24
Finished Mar 28 01:23:20 PM PDT 24
Peak memory 198664 kb
Host smart-d1a48527-3ded-4e1c-a012-59ace617cc6f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2815683746 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_smoke.2815683746
Directory /workspace/10.pwrmgr_smoke/latest

Test location /workspace/coverage/default/10.pwrmgr_stress_all_with_rand_reset.396404620
Short name T616
Test name
Test status
Simulation time 5605937500 ps
CPU time 20.71 seconds
Started Mar 28 01:23:19 PM PDT 24
Finished Mar 28 01:23:40 PM PDT 24
Peak memory 200820 kb
Host smart-1164a7af-d1dd-49f3-8429-1b8282f01f4e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=396404620 -assert nopost
proc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 10.pwrmgr_stress_all_with_rand_reset.396404620
Directory /workspace/10.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.pwrmgr_wakeup.4038987281
Short name T757
Test name
Test status
Simulation time 186993873 ps
CPU time 1.08 seconds
Started Mar 28 01:23:19 PM PDT 24
Finished Mar 28 01:23:20 PM PDT 24
Peak memory 198836 kb
Host smart-b3220448-02e0-4325-86bc-f6e64289a569
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4038987281 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_wakeup.4038987281
Directory /workspace/10.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/10.pwrmgr_wakeup_reset.3962789971
Short name T424
Test name
Test status
Simulation time 55753618 ps
CPU time 0.68 seconds
Started Mar 28 01:23:20 PM PDT 24
Finished Mar 28 01:23:21 PM PDT 24
Peak memory 198396 kb
Host smart-683ed9a8-d30a-4a47-9899-4cd9ad5cdc32
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3962789971 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_wakeup_reset.3962789971
Directory /workspace/10.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/11.pwrmgr_aborted_low_power.3908900452
Short name T79
Test name
Test status
Simulation time 112572134 ps
CPU time 0.81 seconds
Started Mar 28 01:23:18 PM PDT 24
Finished Mar 28 01:23:19 PM PDT 24
Peak memory 199148 kb
Host smart-d49afa5d-b0cb-4e7a-8021-e39b199ad546
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3908900452 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_aborted_low_power.3908900452
Directory /workspace/11.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/11.pwrmgr_disable_rom_integrity_check.4182785803
Short name T713
Test name
Test status
Simulation time 68851119 ps
CPU time 0.75 seconds
Started Mar 28 01:23:20 PM PDT 24
Finished Mar 28 01:23:21 PM PDT 24
Peak memory 198380 kb
Host smart-bbc0373b-d143-4d12-bceb-00135840c290
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4182785803 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_dis
able_rom_integrity_check.4182785803
Directory /workspace/11.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/11.pwrmgr_esc_clk_rst_malfunc.3669974730
Short name T744
Test name
Test status
Simulation time 39024625 ps
CPU time 0.59 seconds
Started Mar 28 01:23:20 PM PDT 24
Finished Mar 28 01:23:20 PM PDT 24
Peak memory 197384 kb
Host smart-8d5413c6-5cdd-4615-9104-16c8a3ad1ca8
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3669974730 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_esc_clk_rst
_malfunc.3669974730
Directory /workspace/11.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/11.pwrmgr_escalation_timeout.2691981930
Short name T273
Test name
Test status
Simulation time 161631504 ps
CPU time 0.97 seconds
Started Mar 28 01:23:21 PM PDT 24
Finished Mar 28 01:23:22 PM PDT 24
Peak memory 197764 kb
Host smart-74d77c4e-fd67-4781-8b78-df9e1a4b2ff1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2691981930 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_escalation_timeout.2691981930
Directory /workspace/11.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/11.pwrmgr_glitch.3490375407
Short name T755
Test name
Test status
Simulation time 59627433 ps
CPU time 0.67 seconds
Started Mar 28 01:23:16 PM PDT 24
Finished Mar 28 01:23:17 PM PDT 24
Peak memory 197428 kb
Host smart-c88fdcea-6fa0-4783-9a64-0e502cd649f4
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3490375407 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_glitch.3490375407
Directory /workspace/11.pwrmgr_glitch/latest

Test location /workspace/coverage/default/11.pwrmgr_global_esc.1080656290
Short name T944
Test name
Test status
Simulation time 70554667 ps
CPU time 0.59 seconds
Started Mar 28 01:23:18 PM PDT 24
Finished Mar 28 01:23:19 PM PDT 24
Peak memory 197404 kb
Host smart-4e52d654-1d88-492c-a052-7c4c18d10054
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1080656290 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_global_esc.1080656290
Directory /workspace/11.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/11.pwrmgr_lowpower_invalid.463172912
Short name T415
Test name
Test status
Simulation time 42537910 ps
CPU time 0.72 seconds
Started Mar 28 01:23:40 PM PDT 24
Finished Mar 28 01:23:41 PM PDT 24
Peak memory 200760 kb
Host smart-0d66b645-b9ea-4897-b30c-0fb3df198bf7
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=463172912 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inval
id_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_lowpower_invali
d.463172912
Directory /workspace/11.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/11.pwrmgr_lowpower_wakeup_race.3948327668
Short name T614
Test name
Test status
Simulation time 129206614 ps
CPU time 0.69 seconds
Started Mar 28 01:23:19 PM PDT 24
Finished Mar 28 01:23:20 PM PDT 24
Peak memory 197680 kb
Host smart-add2d984-c071-4fbb-b562-de65702582ce
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3948327668 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_lowpower_w
akeup_race.3948327668
Directory /workspace/11.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/11.pwrmgr_reset.499964799
Short name T541
Test name
Test status
Simulation time 87169157 ps
CPU time 0.74 seconds
Started Mar 28 01:23:22 PM PDT 24
Finished Mar 28 01:23:23 PM PDT 24
Peak memory 198528 kb
Host smart-f0492293-b270-4d91-b6c9-3b36f566d452
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=499964799 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_reset.499964799
Directory /workspace/11.pwrmgr_reset/latest

Test location /workspace/coverage/default/11.pwrmgr_reset_invalid.1975280487
Short name T308
Test name
Test status
Simulation time 109953584 ps
CPU time 0.85 seconds
Started Mar 28 01:23:39 PM PDT 24
Finished Mar 28 01:23:40 PM PDT 24
Peak memory 208780 kb
Host smart-61ac85e3-adfa-4349-83d3-393bef553572
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1975280487 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_reset_invalid.1975280487
Directory /workspace/11.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/11.pwrmgr_sec_cm_ctrl_config_regwen.3928012260
Short name T170
Test name
Test status
Simulation time 199258725 ps
CPU time 0.74 seconds
Started Mar 28 01:23:19 PM PDT 24
Finished Mar 28 01:23:20 PM PDT 24
Peak memory 197948 kb
Host smart-9c0173b0-0737-4993-8672-ca1e5e103851
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3928012260 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_sec_
cm_ctrl_config_regwen.3928012260
Directory /workspace/11.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/11.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2164425931
Short name T615
Test name
Test status
Simulation time 912912453 ps
CPU time 2.37 seconds
Started Mar 28 01:23:20 PM PDT 24
Finished Mar 28 01:23:23 PM PDT 24
Peak memory 200468 kb
Host smart-0a70e4a3-897c-44fb-8061-7418c555b19f
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2164425931 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 11.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2164425931
Directory /workspace/11.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/11.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.834652651
Short name T953
Test name
Test status
Simulation time 1030864746 ps
CPU time 2.04 seconds
Started Mar 28 01:23:19 PM PDT 24
Finished Mar 28 01:23:22 PM PDT 24
Peak memory 200512 kb
Host smart-6124527a-50a2-4bd3-b98b-cdcc0ffcabae
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=834652651 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 11.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.834652651
Directory /workspace/11.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/11.pwrmgr_sec_cm_rstmgr_intersig_mubi.1526799007
Short name T514
Test name
Test status
Simulation time 144828174 ps
CPU time 0.82 seconds
Started Mar 28 01:23:19 PM PDT 24
Finished Mar 28 01:23:20 PM PDT 24
Peak memory 198448 kb
Host smart-77e4fcce-2673-47dd-b06b-719c6c81eb64
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1526799007 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_sec_cm_rstmgr_intersig
_mubi.1526799007
Directory /workspace/11.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/11.pwrmgr_smoke.2694546417
Short name T423
Test name
Test status
Simulation time 153054367 ps
CPU time 0.62 seconds
Started Mar 28 01:23:17 PM PDT 24
Finished Mar 28 01:23:18 PM PDT 24
Peak memory 197740 kb
Host smart-2f4d1ba3-f3c6-4324-90a2-d135b3ecaed2
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2694546417 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_smoke.2694546417
Directory /workspace/11.pwrmgr_smoke/latest

Test location /workspace/coverage/default/11.pwrmgr_stress_all.250593737
Short name T67
Test name
Test status
Simulation time 2721402382 ps
CPU time 5.44 seconds
Started Mar 28 01:23:40 PM PDT 24
Finished Mar 28 01:23:47 PM PDT 24
Peak memory 200720 kb
Host smart-3624fa02-200d-4382-877a-92825916db2f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=250593737 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_stress_all.250593737
Directory /workspace/11.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/11.pwrmgr_wakeup.4080030774
Short name T543
Test name
Test status
Simulation time 335932315 ps
CPU time 1.07 seconds
Started Mar 28 01:23:19 PM PDT 24
Finished Mar 28 01:23:21 PM PDT 24
Peak memory 199116 kb
Host smart-c834bdcd-472b-4486-b6aa-2d4c6573b27a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4080030774 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_wakeup.4080030774
Directory /workspace/11.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/11.pwrmgr_wakeup_reset.2645349262
Short name T291
Test name
Test status
Simulation time 120645800 ps
CPU time 0.89 seconds
Started Mar 28 01:23:18 PM PDT 24
Finished Mar 28 01:23:19 PM PDT 24
Peak memory 198644 kb
Host smart-1e38577b-58bc-4d93-a531-aeee1243ea5a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2645349262 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_wakeup_reset.2645349262
Directory /workspace/11.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/12.pwrmgr_aborted_low_power.1670713569
Short name T562
Test name
Test status
Simulation time 75032371 ps
CPU time 0.62 seconds
Started Mar 28 01:23:41 PM PDT 24
Finished Mar 28 01:23:42 PM PDT 24
Peak memory 197796 kb
Host smart-b701e07c-cbe4-4d74-81a1-77808360dd0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1670713569 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_aborted_low_power.1670713569
Directory /workspace/12.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/12.pwrmgr_disable_rom_integrity_check.2672154644
Short name T151
Test name
Test status
Simulation time 74366312 ps
CPU time 0.71 seconds
Started Mar 28 01:23:38 PM PDT 24
Finished Mar 28 01:23:39 PM PDT 24
Peak memory 197908 kb
Host smart-2f965eb2-279a-4f45-957d-63898e9976a6
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2672154644 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_dis
able_rom_integrity_check.2672154644
Directory /workspace/12.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/12.pwrmgr_esc_clk_rst_malfunc.217050190
Short name T493
Test name
Test status
Simulation time 30882562 ps
CPU time 0.63 seconds
Started Mar 28 01:23:38 PM PDT 24
Finished Mar 28 01:23:39 PM PDT 24
Peak memory 197360 kb
Host smart-32fd8ac4-516e-4ee4-ab03-2e1005247ff7
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=217050190 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_ma
lfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_esc_clk_rst_
malfunc.217050190
Directory /workspace/12.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/12.pwrmgr_escalation_timeout.1720190541
Short name T280
Test name
Test status
Simulation time 639487446 ps
CPU time 0.93 seconds
Started Mar 28 01:23:40 PM PDT 24
Finished Mar 28 01:23:41 PM PDT 24
Peak memory 197444 kb
Host smart-fbf01006-efd2-4f8f-b561-791e0296cd66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1720190541 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_escalation_timeout.1720190541
Directory /workspace/12.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/12.pwrmgr_glitch.2649099110
Short name T645
Test name
Test status
Simulation time 48378853 ps
CPU time 0.63 seconds
Started Mar 28 01:23:41 PM PDT 24
Finished Mar 28 01:23:42 PM PDT 24
Peak memory 197436 kb
Host smart-4cedf81b-38b0-4256-8ccc-36754e6875fc
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2649099110 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_glitch.2649099110
Directory /workspace/12.pwrmgr_glitch/latest

Test location /workspace/coverage/default/12.pwrmgr_global_esc.3743585210
Short name T201
Test name
Test status
Simulation time 24606826 ps
CPU time 0.6 seconds
Started Mar 28 01:23:38 PM PDT 24
Finished Mar 28 01:23:39 PM PDT 24
Peak memory 197392 kb
Host smart-946b9b07-b3f7-4cd6-98e4-26310101fd63
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3743585210 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_global_esc.3743585210
Directory /workspace/12.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/12.pwrmgr_lowpower_invalid.2926798598
Short name T794
Test name
Test status
Simulation time 84479851 ps
CPU time 0.7 seconds
Started Mar 28 01:23:39 PM PDT 24
Finished Mar 28 01:23:39 PM PDT 24
Peak memory 200548 kb
Host smart-42888800-9cbc-4712-972c-ad08d57ff009
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2926798598 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_lowpower_inval
id.2926798598
Directory /workspace/12.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/12.pwrmgr_lowpower_wakeup_race.966739187
Short name T566
Test name
Test status
Simulation time 276606908 ps
CPU time 0.86 seconds
Started Mar 28 01:23:40 PM PDT 24
Finished Mar 28 01:23:42 PM PDT 24
Peak memory 197912 kb
Host smart-68a0b349-05e8-49aa-96ca-42f4798a4438
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=966739187 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeu
p_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_lowpower_wa
keup_race.966739187
Directory /workspace/12.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/12.pwrmgr_reset.1083517110
Short name T925
Test name
Test status
Simulation time 65808331 ps
CPU time 0.92 seconds
Started Mar 28 01:23:41 PM PDT 24
Finished Mar 28 01:23:42 PM PDT 24
Peak memory 198452 kb
Host smart-ce2dd103-5bfa-43fb-a0d1-b39a1df746cc
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1083517110 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_reset.1083517110
Directory /workspace/12.pwrmgr_reset/latest

Test location /workspace/coverage/default/12.pwrmgr_reset_invalid.3615189032
Short name T481
Test name
Test status
Simulation time 119818977 ps
CPU time 0.92 seconds
Started Mar 28 01:23:38 PM PDT 24
Finished Mar 28 01:23:39 PM PDT 24
Peak memory 208748 kb
Host smart-b504d134-ccfa-4b70-af6a-1e1a38d92fdd
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3615189032 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_reset_invalid.3615189032
Directory /workspace/12.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/12.pwrmgr_sec_cm_ctrl_config_regwen.861792240
Short name T345
Test name
Test status
Simulation time 306556556 ps
CPU time 0.96 seconds
Started Mar 28 01:23:43 PM PDT 24
Finished Mar 28 01:23:44 PM PDT 24
Peak memory 199396 kb
Host smart-6e2c0fdc-51ed-4700-b05f-857d6efcc24a
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=861792240 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_c
onfig_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_sec_c
m_ctrl_config_regwen.861792240
Directory /workspace/12.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/12.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.155577293
Short name T211
Test name
Test status
Simulation time 1232907379 ps
CPU time 2.34 seconds
Started Mar 28 01:23:40 PM PDT 24
Finished Mar 28 01:23:43 PM PDT 24
Peak memory 200432 kb
Host smart-0410aac5-1566-4738-b9d8-2022d5f5a42c
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=155577293 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 12.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.155577293
Directory /workspace/12.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/12.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1589101783
Short name T895
Test name
Test status
Simulation time 776912225 ps
CPU time 3.17 seconds
Started Mar 28 01:23:43 PM PDT 24
Finished Mar 28 01:23:46 PM PDT 24
Peak memory 200436 kb
Host smart-14bcbc04-971c-4db5-9cf2-e3e1c92a5c34
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1589101783 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 12.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1589101783
Directory /workspace/12.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/12.pwrmgr_sec_cm_rstmgr_intersig_mubi.2553471152
Short name T353
Test name
Test status
Simulation time 131934023 ps
CPU time 0.84 seconds
Started Mar 28 01:23:40 PM PDT 24
Finished Mar 28 01:23:42 PM PDT 24
Peak memory 198648 kb
Host smart-d4640b5d-68eb-46d1-8920-5714870bdd9a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2553471152 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_sec_cm_rstmgr_intersig
_mubi.2553471152
Directory /workspace/12.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/12.pwrmgr_smoke.2855713671
Short name T388
Test name
Test status
Simulation time 51408804 ps
CPU time 0.65 seconds
Started Mar 28 01:23:38 PM PDT 24
Finished Mar 28 01:23:39 PM PDT 24
Peak memory 198604 kb
Host smart-804ca166-d29f-4c97-b350-fc991040c77f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2855713671 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_smoke.2855713671
Directory /workspace/12.pwrmgr_smoke/latest

Test location /workspace/coverage/default/12.pwrmgr_stress_all_with_rand_reset.3970707280
Short name T120
Test name
Test status
Simulation time 21148341731 ps
CPU time 30.3 seconds
Started Mar 28 01:23:38 PM PDT 24
Finished Mar 28 01:24:09 PM PDT 24
Peak memory 200876 kb
Host smart-3ba183d0-ad7f-4d2f-a85c-42ccb9e024ab
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3970707280 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 12.pwrmgr_stress_all_with_rand_reset.3970707280
Directory /workspace/12.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.pwrmgr_wakeup.394726542
Short name T729
Test name
Test status
Simulation time 118135286 ps
CPU time 0.7 seconds
Started Mar 28 01:23:40 PM PDT 24
Finished Mar 28 01:23:42 PM PDT 24
Peak memory 198432 kb
Host smart-390c5af3-5ac9-4ecd-965c-110cc36638ee
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=394726542 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_wakeup.394726542
Directory /workspace/12.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/12.pwrmgr_wakeup_reset.424643811
Short name T676
Test name
Test status
Simulation time 572251146 ps
CPU time 1.24 seconds
Started Mar 28 01:23:38 PM PDT 24
Finished Mar 28 01:23:39 PM PDT 24
Peak memory 200520 kb
Host smart-541a30be-a68f-45b2-8640-6038fc18331f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=424643811 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_wakeup_reset.424643811
Directory /workspace/12.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/13.pwrmgr_aborted_low_power.2506141913
Short name T212
Test name
Test status
Simulation time 68850290 ps
CPU time 0.87 seconds
Started Mar 28 01:23:39 PM PDT 24
Finished Mar 28 01:23:40 PM PDT 24
Peak memory 199528 kb
Host smart-a8151332-e8dd-4368-a029-1d8061ec07e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2506141913 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_aborted_low_power.2506141913
Directory /workspace/13.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/13.pwrmgr_disable_rom_integrity_check.2982468194
Short name T286
Test name
Test status
Simulation time 64175898 ps
CPU time 0.89 seconds
Started Mar 28 01:23:41 PM PDT 24
Finished Mar 28 01:23:42 PM PDT 24
Peak memory 199208 kb
Host smart-d843821f-9d76-4b95-9e42-f1b38a33b5e5
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2982468194 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_dis
able_rom_integrity_check.2982468194
Directory /workspace/13.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/13.pwrmgr_esc_clk_rst_malfunc.2807118383
Short name T245
Test name
Test status
Simulation time 28827558 ps
CPU time 0.62 seconds
Started Mar 28 01:23:38 PM PDT 24
Finished Mar 28 01:23:39 PM PDT 24
Peak memory 197360 kb
Host smart-66ffa35b-cb9c-4e3c-8d97-4ad3e0ab96a6
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2807118383 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_esc_clk_rst
_malfunc.2807118383
Directory /workspace/13.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/13.pwrmgr_escalation_timeout.1896050446
Short name T499
Test name
Test status
Simulation time 166058633 ps
CPU time 0.94 seconds
Started Mar 28 01:23:41 PM PDT 24
Finished Mar 28 01:23:42 PM PDT 24
Peak memory 197632 kb
Host smart-37cb941f-7215-4851-aaa0-d7df3c1e24e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1896050446 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_escalation_timeout.1896050446
Directory /workspace/13.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/13.pwrmgr_glitch.319823132
Short name T283
Test name
Test status
Simulation time 52094429 ps
CPU time 0.67 seconds
Started Mar 28 01:23:40 PM PDT 24
Finished Mar 28 01:23:42 PM PDT 24
Peak memory 197468 kb
Host smart-2ad58bd7-9d8c-4b18-8455-a15644ffa80a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=319823132 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_glitch.319823132
Directory /workspace/13.pwrmgr_glitch/latest

Test location /workspace/coverage/default/13.pwrmgr_global_esc.256201042
Short name T759
Test name
Test status
Simulation time 47541790 ps
CPU time 0.59 seconds
Started Mar 28 01:23:39 PM PDT 24
Finished Mar 28 01:23:40 PM PDT 24
Peak memory 197472 kb
Host smart-a2714196-5188-447c-be26-42c83462fb99
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=256201042 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_global_esc.256201042
Directory /workspace/13.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/13.pwrmgr_lowpower_invalid.3938290291
Short name T990
Test name
Test status
Simulation time 39683272 ps
CPU time 0.76 seconds
Started Mar 28 01:23:39 PM PDT 24
Finished Mar 28 01:23:40 PM PDT 24
Peak memory 200756 kb
Host smart-8195fd0c-9725-4630-997c-e6dff78a6fde
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3938290291 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_lowpower_inval
id.3938290291
Directory /workspace/13.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/13.pwrmgr_lowpower_wakeup_race.1413915813
Short name T932
Test name
Test status
Simulation time 202005786 ps
CPU time 0.82 seconds
Started Mar 28 01:23:40 PM PDT 24
Finished Mar 28 01:23:42 PM PDT 24
Peak memory 197876 kb
Host smart-b39419e8-535e-4dcd-b38a-5a2f47bf08ae
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1413915813 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_lowpower_w
akeup_race.1413915813
Directory /workspace/13.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/13.pwrmgr_reset.1637968427
Short name T942
Test name
Test status
Simulation time 48698564 ps
CPU time 0.81 seconds
Started Mar 28 01:23:39 PM PDT 24
Finished Mar 28 01:23:40 PM PDT 24
Peak memory 198504 kb
Host smart-356de745-9877-4908-b39e-39c0ff81f32c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1637968427 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_reset.1637968427
Directory /workspace/13.pwrmgr_reset/latest

Test location /workspace/coverage/default/13.pwrmgr_reset_invalid.43115392
Short name T930
Test name
Test status
Simulation time 101375182 ps
CPU time 0.89 seconds
Started Mar 28 01:23:39 PM PDT 24
Finished Mar 28 01:23:41 PM PDT 24
Peak memory 208880 kb
Host smart-4a89a8ef-f3f6-42b5-862c-97bc78d1b15e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43115392 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_reset_invalid.43115392
Directory /workspace/13.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/13.pwrmgr_sec_cm_ctrl_config_regwen.3778230319
Short name T708
Test name
Test status
Simulation time 191481025 ps
CPU time 1.26 seconds
Started Mar 28 01:23:40 PM PDT 24
Finished Mar 28 01:23:42 PM PDT 24
Peak memory 199504 kb
Host smart-9cf313a0-4537-492e-8a24-13b40f984b07
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3778230319 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_sec_
cm_ctrl_config_regwen.3778230319
Directory /workspace/13.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/13.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.4126411798
Short name T513
Test name
Test status
Simulation time 1239258417 ps
CPU time 2.18 seconds
Started Mar 28 01:23:38 PM PDT 24
Finished Mar 28 01:23:40 PM PDT 24
Peak memory 200432 kb
Host smart-7477c509-b719-4698-b3cc-9909bdf760f7
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4126411798 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 13.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.4126411798
Directory /workspace/13.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/13.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1951117396
Short name T35
Test name
Test status
Simulation time 1085243108 ps
CPU time 2.14 seconds
Started Mar 28 01:23:40 PM PDT 24
Finished Mar 28 01:23:43 PM PDT 24
Peak memory 200452 kb
Host smart-8410e8c0-55ac-4b57-9005-652a175b17bd
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1951117396 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 13.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1951117396
Directory /workspace/13.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/13.pwrmgr_sec_cm_rstmgr_intersig_mubi.2933767581
Short name T735
Test name
Test status
Simulation time 96079418 ps
CPU time 0.85 seconds
Started Mar 28 01:23:41 PM PDT 24
Finished Mar 28 01:23:42 PM PDT 24
Peak memory 198856 kb
Host smart-af3b53a2-a370-4637-b69d-5f9159d91e56
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2933767581 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_sec_cm_rstmgr_intersig
_mubi.2933767581
Directory /workspace/13.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/13.pwrmgr_smoke.1946647263
Short name T838
Test name
Test status
Simulation time 52548836 ps
CPU time 0.64 seconds
Started Mar 28 01:23:37 PM PDT 24
Finished Mar 28 01:23:38 PM PDT 24
Peak memory 197708 kb
Host smart-0fc39984-1020-4424-858f-2327676cb6a9
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1946647263 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_smoke.1946647263
Directory /workspace/13.pwrmgr_smoke/latest

Test location /workspace/coverage/default/13.pwrmgr_stress_all.749726628
Short name T324
Test name
Test status
Simulation time 965803832 ps
CPU time 2.77 seconds
Started Mar 28 01:23:39 PM PDT 24
Finished Mar 28 01:23:42 PM PDT 24
Peak memory 200512 kb
Host smart-24a01257-064a-483b-8c4f-7d5fa8d09f71
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=749726628 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_stress_all.749726628
Directory /workspace/13.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/13.pwrmgr_stress_all_with_rand_reset.4023954688
Short name T63
Test name
Test status
Simulation time 7566039081 ps
CPU time 23.13 seconds
Started Mar 28 01:23:41 PM PDT 24
Finished Mar 28 01:24:04 PM PDT 24
Peak memory 200880 kb
Host smart-5906e04e-ae69-43a1-970e-dbe942e50121
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4023954688 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 13.pwrmgr_stress_all_with_rand_reset.4023954688
Directory /workspace/13.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.pwrmgr_wakeup.1160981295
Short name T270
Test name
Test status
Simulation time 85646229 ps
CPU time 0.69 seconds
Started Mar 28 01:23:40 PM PDT 24
Finished Mar 28 01:23:41 PM PDT 24
Peak memory 197864 kb
Host smart-5cc6f2c3-879c-43f2-92b6-6017b4ea2e0d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1160981295 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_wakeup.1160981295
Directory /workspace/13.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/13.pwrmgr_wakeup_reset.3529645228
Short name T609
Test name
Test status
Simulation time 536677204 ps
CPU time 1.06 seconds
Started Mar 28 01:23:39 PM PDT 24
Finished Mar 28 01:23:40 PM PDT 24
Peak memory 200428 kb
Host smart-dd77db1f-c4e4-4910-a503-ea2257d7e46a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3529645228 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_wakeup_reset.3529645228
Directory /workspace/13.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/14.pwrmgr_aborted_low_power.3471681970
Short name T109
Test name
Test status
Simulation time 59244075 ps
CPU time 0.68 seconds
Started Mar 28 01:23:40 PM PDT 24
Finished Mar 28 01:23:41 PM PDT 24
Peak memory 198048 kb
Host smart-af2d77f6-99ca-45e1-b4c7-239c4eadbf66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3471681970 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_aborted_low_power.3471681970
Directory /workspace/14.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/14.pwrmgr_disable_rom_integrity_check.2287899797
Short name T149
Test name
Test status
Simulation time 48270621 ps
CPU time 0.88 seconds
Started Mar 28 01:23:38 PM PDT 24
Finished Mar 28 01:23:39 PM PDT 24
Peak memory 198444 kb
Host smart-0740e50f-97e7-4116-bd44-4c0fbc015d7a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2287899797 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_dis
able_rom_integrity_check.2287899797
Directory /workspace/14.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/14.pwrmgr_esc_clk_rst_malfunc.1353878716
Short name T655
Test name
Test status
Simulation time 39940960 ps
CPU time 0.58 seconds
Started Mar 28 01:23:37 PM PDT 24
Finished Mar 28 01:23:39 PM PDT 24
Peak memory 197288 kb
Host smart-3d0a1d44-1a25-4af5-bbea-897d17fa266c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1353878716 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_esc_clk_rst
_malfunc.1353878716
Directory /workspace/14.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/14.pwrmgr_escalation_timeout.982024777
Short name T316
Test name
Test status
Simulation time 629871230 ps
CPU time 0.96 seconds
Started Mar 28 01:23:40 PM PDT 24
Finished Mar 28 01:23:42 PM PDT 24
Peak memory 197436 kb
Host smart-79000170-92a3-44fa-acda-351458ac5999
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=982024777 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_escalation_timeout.982024777
Directory /workspace/14.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/14.pwrmgr_glitch.3827830565
Short name T295
Test name
Test status
Simulation time 23501467 ps
CPU time 0.63 seconds
Started Mar 28 01:23:42 PM PDT 24
Finished Mar 28 01:23:43 PM PDT 24
Peak memory 196632 kb
Host smart-ff1a0339-afdc-488d-9038-ffbb8bbd7de5
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3827830565 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_glitch.3827830565
Directory /workspace/14.pwrmgr_glitch/latest

Test location /workspace/coverage/default/14.pwrmgr_global_esc.2082298111
Short name T405
Test name
Test status
Simulation time 37891707 ps
CPU time 0.64 seconds
Started Mar 28 01:23:39 PM PDT 24
Finished Mar 28 01:23:40 PM PDT 24
Peak memory 197464 kb
Host smart-2a5b22a3-2f8b-4b59-bbca-bb57e15a8a40
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2082298111 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_global_esc.2082298111
Directory /workspace/14.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/14.pwrmgr_lowpower_wakeup_race.1452132968
Short name T991
Test name
Test status
Simulation time 256887197 ps
CPU time 1.29 seconds
Started Mar 28 01:23:40 PM PDT 24
Finished Mar 28 01:23:42 PM PDT 24
Peak memory 198900 kb
Host smart-57722793-7476-4345-b4fe-52db8ed9d1c0
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1452132968 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_lowpower_w
akeup_race.1452132968
Directory /workspace/14.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/14.pwrmgr_reset.3265853318
Short name T343
Test name
Test status
Simulation time 47933705 ps
CPU time 0.63 seconds
Started Mar 28 01:23:38 PM PDT 24
Finished Mar 28 01:23:39 PM PDT 24
Peak memory 197580 kb
Host smart-1b0add59-9602-4aec-a853-9b365d315440
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3265853318 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_reset.3265853318
Directory /workspace/14.pwrmgr_reset/latest

Test location /workspace/coverage/default/14.pwrmgr_sec_cm_ctrl_config_regwen.3155782670
Short name T455
Test name
Test status
Simulation time 44204272 ps
CPU time 0.73 seconds
Started Mar 28 01:23:40 PM PDT 24
Finished Mar 28 01:23:42 PM PDT 24
Peak memory 198420 kb
Host smart-660943f8-afc9-49dd-aa0e-ce2a683c85ef
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3155782670 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_sec_
cm_ctrl_config_regwen.3155782670
Directory /workspace/14.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/14.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3021481504
Short name T456
Test name
Test status
Simulation time 895175241 ps
CPU time 2.53 seconds
Started Mar 28 01:23:40 PM PDT 24
Finished Mar 28 01:23:44 PM PDT 24
Peak memory 200600 kb
Host smart-3ba66594-dfca-4e1d-bf71-99522564aba5
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3021481504 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 14.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3021481504
Directory /workspace/14.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/14.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.751747176
Short name T911
Test name
Test status
Simulation time 1165596658 ps
CPU time 2.13 seconds
Started Mar 28 01:23:38 PM PDT 24
Finished Mar 28 01:23:40 PM PDT 24
Peak memory 200668 kb
Host smart-cef427af-6341-4e7c-9f73-379a913d4c40
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=751747176 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 14.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.751747176
Directory /workspace/14.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/14.pwrmgr_sec_cm_rstmgr_intersig_mubi.1582301068
Short name T657
Test name
Test status
Simulation time 55768353 ps
CPU time 0.89 seconds
Started Mar 28 01:23:41 PM PDT 24
Finished Mar 28 01:23:42 PM PDT 24
Peak memory 198736 kb
Host smart-6c4ad197-ba49-40a5-b795-0b2a5cd1ca2f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1582301068 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_sec_cm_rstmgr_intersig
_mubi.1582301068
Directory /workspace/14.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/14.pwrmgr_smoke.1848117365
Short name T417
Test name
Test status
Simulation time 27644810 ps
CPU time 0.68 seconds
Started Mar 28 01:23:40 PM PDT 24
Finished Mar 28 01:23:41 PM PDT 24
Peak memory 198576 kb
Host smart-9aff9e6a-2e7c-4c16-a1c0-b53d8267ce7f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1848117365 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_smoke.1848117365
Directory /workspace/14.pwrmgr_smoke/latest

Test location /workspace/coverage/default/14.pwrmgr_stress_all.2095540194
Short name T104
Test name
Test status
Simulation time 1236266571 ps
CPU time 5.78 seconds
Started Mar 28 01:23:40 PM PDT 24
Finished Mar 28 01:23:46 PM PDT 24
Peak memory 200580 kb
Host smart-9bcfbb1d-43ac-4f1b-8309-0b7faea1bdbe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2095540194 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_stress_all.2095540194
Directory /workspace/14.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/14.pwrmgr_stress_all_with_rand_reset.2873303608
Short name T115
Test name
Test status
Simulation time 14878495973 ps
CPU time 24.4 seconds
Started Mar 28 01:23:40 PM PDT 24
Finished Mar 28 01:24:05 PM PDT 24
Peak memory 200876 kb
Host smart-6b4c4304-7c49-43da-b607-36b73daa3871
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2873303608 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 14.pwrmgr_stress_all_with_rand_reset.2873303608
Directory /workspace/14.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.pwrmgr_wakeup.2807871548
Short name T800
Test name
Test status
Simulation time 144176496 ps
CPU time 0.81 seconds
Started Mar 28 01:23:39 PM PDT 24
Finished Mar 28 01:23:41 PM PDT 24
Peak memory 197788 kb
Host smart-41e9e403-2993-4459-8b6b-b3c03fd878b8
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2807871548 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_wakeup.2807871548
Directory /workspace/14.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/14.pwrmgr_wakeup_reset.710764596
Short name T764
Test name
Test status
Simulation time 258065645 ps
CPU time 1.19 seconds
Started Mar 28 01:23:40 PM PDT 24
Finished Mar 28 01:23:42 PM PDT 24
Peak memory 199396 kb
Host smart-2abd32f3-31be-4fe9-b1c1-3a05c220e35d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=710764596 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_wakeup_reset.710764596
Directory /workspace/14.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/15.pwrmgr_aborted_low_power.1811734004
Short name T412
Test name
Test status
Simulation time 120302486 ps
CPU time 0.83 seconds
Started Mar 28 01:23:54 PM PDT 24
Finished Mar 28 01:23:55 PM PDT 24
Peak memory 199276 kb
Host smart-70f29a5b-0e31-497a-9acd-b9f6d571d957
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1811734004 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_aborted_low_power.1811734004
Directory /workspace/15.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/15.pwrmgr_disable_rom_integrity_check.1475337931
Short name T494
Test name
Test status
Simulation time 70815488 ps
CPU time 0.83 seconds
Started Mar 28 01:23:57 PM PDT 24
Finished Mar 28 01:23:58 PM PDT 24
Peak memory 197924 kb
Host smart-9f7eb546-c7f3-4cf2-aad1-871fb8fd42c6
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1475337931 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_dis
able_rom_integrity_check.1475337931
Directory /workspace/15.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/15.pwrmgr_esc_clk_rst_malfunc.2185019527
Short name T411
Test name
Test status
Simulation time 40235388 ps
CPU time 0.61 seconds
Started Mar 28 01:23:55 PM PDT 24
Finished Mar 28 01:23:56 PM PDT 24
Peak memory 197364 kb
Host smart-2e2a6f94-28f2-4b38-af3d-7e9b1d0ff4c5
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2185019527 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_esc_clk_rst
_malfunc.2185019527
Directory /workspace/15.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/15.pwrmgr_escalation_timeout.576528903
Short name T667
Test name
Test status
Simulation time 626685695 ps
CPU time 0.99 seconds
Started Mar 28 01:23:57 PM PDT 24
Finished Mar 28 01:23:58 PM PDT 24
Peak memory 197756 kb
Host smart-95f11e96-cf98-423b-8069-6a60624d7e18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=576528903 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_escalation_timeout.576528903
Directory /workspace/15.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/15.pwrmgr_glitch.2674404077
Short name T717
Test name
Test status
Simulation time 50251818 ps
CPU time 0.65 seconds
Started Mar 28 01:23:55 PM PDT 24
Finished Mar 28 01:23:56 PM PDT 24
Peak memory 197412 kb
Host smart-ae5d2096-b616-4d5a-bd07-7749d13f5d8f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2674404077 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_glitch.2674404077
Directory /workspace/15.pwrmgr_glitch/latest

Test location /workspace/coverage/default/15.pwrmgr_global_esc.1296328401
Short name T437
Test name
Test status
Simulation time 60045371 ps
CPU time 0.56 seconds
Started Mar 28 01:23:53 PM PDT 24
Finished Mar 28 01:23:54 PM PDT 24
Peak memory 197464 kb
Host smart-1bfa499c-9ae9-4fcb-9d21-bfcde3257f95
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1296328401 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_global_esc.1296328401
Directory /workspace/15.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/15.pwrmgr_lowpower_invalid.3494064590
Short name T985
Test name
Test status
Simulation time 72318145 ps
CPU time 0.69 seconds
Started Mar 28 01:23:55 PM PDT 24
Finished Mar 28 01:23:56 PM PDT 24
Peak memory 200724 kb
Host smart-6abbb5db-2724-4adf-965a-62de17d0af54
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3494064590 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_lowpower_inval
id.3494064590
Directory /workspace/15.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/15.pwrmgr_lowpower_wakeup_race.1286686495
Short name T397
Test name
Test status
Simulation time 140993860 ps
CPU time 0.81 seconds
Started Mar 28 01:23:40 PM PDT 24
Finished Mar 28 01:23:41 PM PDT 24
Peak memory 198428 kb
Host smart-d76a7f98-c3a1-423b-800f-8a07dedd1f2f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1286686495 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_lowpower_w
akeup_race.1286686495
Directory /workspace/15.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/15.pwrmgr_reset.117691385
Short name T597
Test name
Test status
Simulation time 55413222 ps
CPU time 0.77 seconds
Started Mar 28 01:23:37 PM PDT 24
Finished Mar 28 01:23:39 PM PDT 24
Peak memory 198468 kb
Host smart-04f60f0e-46d0-4457-8f90-f16676919124
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=117691385 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_reset.117691385
Directory /workspace/15.pwrmgr_reset/latest

Test location /workspace/coverage/default/15.pwrmgr_reset_invalid.417978777
Short name T952
Test name
Test status
Simulation time 108633462 ps
CPU time 1.14 seconds
Started Mar 28 01:24:01 PM PDT 24
Finished Mar 28 01:24:03 PM PDT 24
Peak memory 208860 kb
Host smart-713cb9fd-4829-4792-9c47-64547a6ef234
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=417978777 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_reset_invalid.417978777
Directory /workspace/15.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/15.pwrmgr_sec_cm_ctrl_config_regwen.621880813
Short name T693
Test name
Test status
Simulation time 331784867 ps
CPU time 1.14 seconds
Started Mar 28 01:23:54 PM PDT 24
Finished Mar 28 01:23:56 PM PDT 24
Peak memory 200272 kb
Host smart-f4197439-e24a-401d-9bfc-86d0111e150d
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=621880813 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_c
onfig_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_sec_c
m_ctrl_config_regwen.621880813
Directory /workspace/15.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/15.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1596788623
Short name T449
Test name
Test status
Simulation time 777146231 ps
CPU time 3.13 seconds
Started Mar 28 01:24:01 PM PDT 24
Finished Mar 28 01:24:04 PM PDT 24
Peak memory 200468 kb
Host smart-cc772fa7-c95e-4530-a3e1-eb34ba4586b4
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1596788623 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 15.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1596788623
Directory /workspace/15.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/15.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.4231698894
Short name T844
Test name
Test status
Simulation time 891406208 ps
CPU time 3.53 seconds
Started Mar 28 01:24:02 PM PDT 24
Finished Mar 28 01:24:05 PM PDT 24
Peak memory 200468 kb
Host smart-f1dbb6c5-d6a9-4522-8313-2cc78d20c9e1
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4231698894 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 15.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.4231698894
Directory /workspace/15.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/15.pwrmgr_sec_cm_rstmgr_intersig_mubi.2486432656
Short name T656
Test name
Test status
Simulation time 71285817 ps
CPU time 0.87 seconds
Started Mar 28 01:23:54 PM PDT 24
Finished Mar 28 01:23:55 PM PDT 24
Peak memory 198440 kb
Host smart-913d1e66-1699-4574-8f2b-becb35b4b294
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2486432656 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_sec_cm_rstmgr_intersig
_mubi.2486432656
Directory /workspace/15.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/15.pwrmgr_smoke.1115108413
Short name T920
Test name
Test status
Simulation time 28538304 ps
CPU time 0.7 seconds
Started Mar 28 01:23:40 PM PDT 24
Finished Mar 28 01:23:42 PM PDT 24
Peak memory 198668 kb
Host smart-88374f4f-a3b7-44df-8ae2-4aa9e40b18aa
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1115108413 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_smoke.1115108413
Directory /workspace/15.pwrmgr_smoke/latest

Test location /workspace/coverage/default/15.pwrmgr_stress_all.1369415704
Short name T105
Test name
Test status
Simulation time 1929283043 ps
CPU time 4.95 seconds
Started Mar 28 01:23:58 PM PDT 24
Finished Mar 28 01:24:03 PM PDT 24
Peak memory 200640 kb
Host smart-aeff94d7-0a42-4c92-a4d2-32859396e89e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1369415704 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_stress_all.1369415704
Directory /workspace/15.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/15.pwrmgr_stress_all_with_rand_reset.3562119130
Short name T641
Test name
Test status
Simulation time 11473283207 ps
CPU time 18.53 seconds
Started Mar 28 01:23:56 PM PDT 24
Finished Mar 28 01:24:15 PM PDT 24
Peak memory 200904 kb
Host smart-b80ba599-07cf-4bb8-8920-54313a2598f0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3562119130 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 15.pwrmgr_stress_all_with_rand_reset.3562119130
Directory /workspace/15.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.pwrmgr_wakeup.2056224978
Short name T216
Test name
Test status
Simulation time 93484531 ps
CPU time 0.73 seconds
Started Mar 28 01:23:41 PM PDT 24
Finished Mar 28 01:23:42 PM PDT 24
Peak memory 197904 kb
Host smart-76567aaa-a39c-485f-be0a-5b9f64abb336
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2056224978 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_wakeup.2056224978
Directory /workspace/15.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/15.pwrmgr_wakeup_reset.1581975888
Short name T521
Test name
Test status
Simulation time 88606442 ps
CPU time 0.87 seconds
Started Mar 28 01:23:40 PM PDT 24
Finished Mar 28 01:23:42 PM PDT 24
Peak memory 198056 kb
Host smart-322b596f-6c23-4b0a-9d60-1f1ecc890f71
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1581975888 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_wakeup_reset.1581975888
Directory /workspace/15.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/16.pwrmgr_aborted_low_power.2423581942
Short name T909
Test name
Test status
Simulation time 41615224 ps
CPU time 0.88 seconds
Started Mar 28 01:23:54 PM PDT 24
Finished Mar 28 01:23:55 PM PDT 24
Peak memory 200204 kb
Host smart-9939f95e-325f-4151-a349-9eb7a82a87e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2423581942 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_aborted_low_power.2423581942
Directory /workspace/16.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/16.pwrmgr_disable_rom_integrity_check.3820637705
Short name T613
Test name
Test status
Simulation time 63907312 ps
CPU time 0.69 seconds
Started Mar 28 01:24:01 PM PDT 24
Finished Mar 28 01:24:02 PM PDT 24
Peak memory 198496 kb
Host smart-191e2978-21dc-40bb-b27b-4ff27159bc96
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3820637705 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_dis
able_rom_integrity_check.3820637705
Directory /workspace/16.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/16.pwrmgr_esc_clk_rst_malfunc.3919722397
Short name T320
Test name
Test status
Simulation time 32158161 ps
CPU time 0.63 seconds
Started Mar 28 01:24:02 PM PDT 24
Finished Mar 28 01:24:03 PM PDT 24
Peak memory 197328 kb
Host smart-39f96701-42e5-47f2-949c-3ba601cb29fe
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3919722397 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_esc_clk_rst
_malfunc.3919722397
Directory /workspace/16.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/16.pwrmgr_escalation_timeout.3661406352
Short name T490
Test name
Test status
Simulation time 582214756 ps
CPU time 0.96 seconds
Started Mar 28 01:24:01 PM PDT 24
Finished Mar 28 01:24:02 PM PDT 24
Peak memory 197468 kb
Host smart-aef29d6b-964a-47eb-b0d1-33aa1ee1a18e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3661406352 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_escalation_timeout.3661406352
Directory /workspace/16.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/16.pwrmgr_glitch.3292699730
Short name T459
Test name
Test status
Simulation time 47642500 ps
CPU time 0.73 seconds
Started Mar 28 01:23:54 PM PDT 24
Finished Mar 28 01:23:55 PM PDT 24
Peak memory 197432 kb
Host smart-719e25b9-9c36-4caf-b0f8-8a8be64c6cf1
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3292699730 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_glitch.3292699730
Directory /workspace/16.pwrmgr_glitch/latest

Test location /workspace/coverage/default/16.pwrmgr_global_esc.2367888212
Short name T365
Test name
Test status
Simulation time 85185468 ps
CPU time 0.62 seconds
Started Mar 28 01:23:53 PM PDT 24
Finished Mar 28 01:23:54 PM PDT 24
Peak memory 197464 kb
Host smart-bf7df998-e0a1-4849-8d64-068106bb8abd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2367888212 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_global_esc.2367888212
Directory /workspace/16.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/16.pwrmgr_lowpower_invalid.1561125567
Short name T681
Test name
Test status
Simulation time 38784426 ps
CPU time 0.7 seconds
Started Mar 28 01:23:57 PM PDT 24
Finished Mar 28 01:23:58 PM PDT 24
Peak memory 200664 kb
Host smart-6604f2c0-459d-46c1-b074-146d9f3fc97d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1561125567 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_lowpower_inval
id.1561125567
Directory /workspace/16.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/16.pwrmgr_lowpower_wakeup_race.3556943217
Short name T868
Test name
Test status
Simulation time 312310761 ps
CPU time 0.92 seconds
Started Mar 28 01:24:01 PM PDT 24
Finished Mar 28 01:24:02 PM PDT 24
Peak memory 198956 kb
Host smart-ca8d1a3e-bd09-4323-a2aa-329f3dd0a3fe
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3556943217 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_lowpower_w
akeup_race.3556943217
Directory /workspace/16.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/16.pwrmgr_reset.3621718903
Short name T986
Test name
Test status
Simulation time 127184422 ps
CPU time 0.82 seconds
Started Mar 28 01:24:07 PM PDT 24
Finished Mar 28 01:24:08 PM PDT 24
Peak memory 198416 kb
Host smart-875278f5-5f0e-4efc-a9e6-3203f0cf949f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3621718903 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_reset.3621718903
Directory /workspace/16.pwrmgr_reset/latest

Test location /workspace/coverage/default/16.pwrmgr_reset_invalid.3643634863
Short name T539
Test name
Test status
Simulation time 98282769 ps
CPU time 1.03 seconds
Started Mar 28 01:23:57 PM PDT 24
Finished Mar 28 01:23:58 PM PDT 24
Peak memory 208840 kb
Host smart-aa876cbe-e67e-4e65-a64f-4c471fe75ca6
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3643634863 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_reset_invalid.3643634863
Directory /workspace/16.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/16.pwrmgr_sec_cm_ctrl_config_regwen.323796779
Short name T202
Test name
Test status
Simulation time 177325107 ps
CPU time 0.64 seconds
Started Mar 28 01:23:56 PM PDT 24
Finished Mar 28 01:23:57 PM PDT 24
Peak memory 197884 kb
Host smart-b17fdeb9-f391-4f87-a8e5-0bae18814a99
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=323796779 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_c
onfig_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_sec_c
m_ctrl_config_regwen.323796779
Directory /workspace/16.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/16.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.926030495
Short name T724
Test name
Test status
Simulation time 805254823 ps
CPU time 2.32 seconds
Started Mar 28 01:23:56 PM PDT 24
Finished Mar 28 01:23:59 PM PDT 24
Peak memory 200512 kb
Host smart-915890b7-a9b7-4be8-96af-dd38b5981a46
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=926030495 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 16.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.926030495
Directory /workspace/16.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/16.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.13398313
Short name T446
Test name
Test status
Simulation time 874475547 ps
CPU time 2.91 seconds
Started Mar 28 01:23:56 PM PDT 24
Finished Mar 28 01:23:59 PM PDT 24
Peak memory 200512 kb
Host smart-fcd587cb-6576-4d47-814e-5f45fee6410f
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13398313 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 16.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.13398313
Directory /workspace/16.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/16.pwrmgr_sec_cm_rstmgr_intersig_mubi.1823260884
Short name T414
Test name
Test status
Simulation time 54854699 ps
CPU time 0.94 seconds
Started Mar 28 01:23:54 PM PDT 24
Finished Mar 28 01:23:55 PM PDT 24
Peak memory 198656 kb
Host smart-6cc2f49b-9559-4c4a-b9cd-11342981eab2
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1823260884 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_sec_cm_rstmgr_intersig
_mubi.1823260884
Directory /workspace/16.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/16.pwrmgr_smoke.2697425247
Short name T861
Test name
Test status
Simulation time 28133313 ps
CPU time 0.67 seconds
Started Mar 28 01:23:57 PM PDT 24
Finished Mar 28 01:23:58 PM PDT 24
Peak memory 198672 kb
Host smart-e9fd612b-e27a-4286-b341-9e240c41384b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2697425247 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_smoke.2697425247
Directory /workspace/16.pwrmgr_smoke/latest

Test location /workspace/coverage/default/16.pwrmgr_stress_all.1519107368
Short name T106
Test name
Test status
Simulation time 2361941980 ps
CPU time 5.31 seconds
Started Mar 28 01:23:56 PM PDT 24
Finished Mar 28 01:24:02 PM PDT 24
Peak memory 200732 kb
Host smart-a8be4367-97f4-4468-a21a-340033fa4bec
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1519107368 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_stress_all.1519107368
Directory /workspace/16.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/16.pwrmgr_stress_all_with_rand_reset.2465109883
Short name T361
Test name
Test status
Simulation time 4341039309 ps
CPU time 10.9 seconds
Started Mar 28 01:24:01 PM PDT 24
Finished Mar 28 01:24:12 PM PDT 24
Peak memory 200888 kb
Host smart-9649837c-f820-4829-a45c-9a1f04e75693
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2465109883 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 16.pwrmgr_stress_all_with_rand_reset.2465109883
Directory /workspace/16.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.pwrmgr_wakeup.2379108789
Short name T348
Test name
Test status
Simulation time 272234494 ps
CPU time 1.18 seconds
Started Mar 28 01:23:53 PM PDT 24
Finished Mar 28 01:23:54 PM PDT 24
Peak memory 198772 kb
Host smart-ac2463d9-7509-4ee7-8b31-acf53dc482e0
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2379108789 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_wakeup.2379108789
Directory /workspace/16.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/16.pwrmgr_wakeup_reset.2547284998
Short name T351
Test name
Test status
Simulation time 282055705 ps
CPU time 1.21 seconds
Started Mar 28 01:24:02 PM PDT 24
Finished Mar 28 01:24:03 PM PDT 24
Peak memory 199496 kb
Host smart-1293f5f5-3967-40cd-963a-12c2326f7207
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2547284998 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_wakeup_reset.2547284998
Directory /workspace/16.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/17.pwrmgr_aborted_low_power.2391166418
Short name T108
Test name
Test status
Simulation time 119734588 ps
CPU time 0.9 seconds
Started Mar 28 01:24:07 PM PDT 24
Finished Mar 28 01:24:08 PM PDT 24
Peak memory 199500 kb
Host smart-e76f64b5-152b-4e1d-b4c9-4b4400d2fc6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2391166418 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_aborted_low_power.2391166418
Directory /workspace/17.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/17.pwrmgr_disable_rom_integrity_check.1134542636
Short name T897
Test name
Test status
Simulation time 96020803 ps
CPU time 0.69 seconds
Started Mar 28 01:24:06 PM PDT 24
Finished Mar 28 01:24:07 PM PDT 24
Peak memory 197640 kb
Host smart-30dd3f71-a00f-40fd-b781-626cd9e089b9
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1134542636 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_dis
able_rom_integrity_check.1134542636
Directory /workspace/17.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/17.pwrmgr_esc_clk_rst_malfunc.528647690
Short name T217
Test name
Test status
Simulation time 39238433 ps
CPU time 0.61 seconds
Started Mar 28 01:24:07 PM PDT 24
Finished Mar 28 01:24:07 PM PDT 24
Peak memory 197340 kb
Host smart-2549d6a6-8818-48ce-8e8e-fd53d6aefec8
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=528647690 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_ma
lfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_esc_clk_rst_
malfunc.528647690
Directory /workspace/17.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/17.pwrmgr_escalation_timeout.4076379300
Short name T375
Test name
Test status
Simulation time 1675078333 ps
CPU time 0.97 seconds
Started Mar 28 01:23:59 PM PDT 24
Finished Mar 28 01:24:00 PM PDT 24
Peak memory 197584 kb
Host smart-e3712505-156b-4f1e-936b-2f3916a173cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4076379300 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_escalation_timeout.4076379300
Directory /workspace/17.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/17.pwrmgr_global_esc.3367266036
Short name T749
Test name
Test status
Simulation time 31947016 ps
CPU time 0.64 seconds
Started Mar 28 01:23:59 PM PDT 24
Finished Mar 28 01:24:00 PM PDT 24
Peak memory 197280 kb
Host smart-6551911a-00d7-4532-bea6-8b07bfb65f1a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3367266036 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_global_esc.3367266036
Directory /workspace/17.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/17.pwrmgr_lowpower_invalid.3621401886
Short name T754
Test name
Test status
Simulation time 56837792 ps
CPU time 0.69 seconds
Started Mar 28 01:24:06 PM PDT 24
Finished Mar 28 01:24:07 PM PDT 24
Peak memory 200708 kb
Host smart-7a7b1136-2068-4a35-94ed-957baf73fd47
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3621401886 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_lowpower_inval
id.3621401886
Directory /workspace/17.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/17.pwrmgr_lowpower_wakeup_race.3299168498
Short name T779
Test name
Test status
Simulation time 358945922 ps
CPU time 0.96 seconds
Started Mar 28 01:23:54 PM PDT 24
Finished Mar 28 01:23:55 PM PDT 24
Peak memory 199040 kb
Host smart-6ca01c38-695b-49da-8973-5e455d612b70
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3299168498 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_lowpower_w
akeup_race.3299168498
Directory /workspace/17.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/17.pwrmgr_reset.972196125
Short name T231
Test name
Test status
Simulation time 109097568 ps
CPU time 0.94 seconds
Started Mar 28 01:24:06 PM PDT 24
Finished Mar 28 01:24:08 PM PDT 24
Peak memory 198744 kb
Host smart-24621188-c283-461c-9edb-f68b14c2059a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=972196125 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_reset.972196125
Directory /workspace/17.pwrmgr_reset/latest

Test location /workspace/coverage/default/17.pwrmgr_reset_invalid.865094839
Short name T179
Test name
Test status
Simulation time 116972714 ps
CPU time 0.96 seconds
Started Mar 28 01:24:01 PM PDT 24
Finished Mar 28 01:24:02 PM PDT 24
Peak memory 208824 kb
Host smart-3cf5ab79-4bbd-47b3-ad99-fa48a9694f3b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=865094839 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_reset_invalid.865094839
Directory /workspace/17.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/17.pwrmgr_sec_cm_ctrl_config_regwen.604980913
Short name T470
Test name
Test status
Simulation time 304022162 ps
CPU time 1.04 seconds
Started Mar 28 01:24:01 PM PDT 24
Finished Mar 28 01:24:03 PM PDT 24
Peak memory 199560 kb
Host smart-1fda948c-2d4f-427c-b0ac-42059c065577
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=604980913 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_c
onfig_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_sec_c
m_ctrl_config_regwen.604980913
Directory /workspace/17.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/17.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1383487079
Short name T370
Test name
Test status
Simulation time 1260930450 ps
CPU time 2.39 seconds
Started Mar 28 01:24:02 PM PDT 24
Finished Mar 28 01:24:04 PM PDT 24
Peak memory 200376 kb
Host smart-571591a3-b929-49c3-bcc5-36128600266c
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1383487079 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 17.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1383487079
Directory /workspace/17.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/17.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3215541761
Short name T342
Test name
Test status
Simulation time 1042747201 ps
CPU time 2.16 seconds
Started Mar 28 01:23:59 PM PDT 24
Finished Mar 28 01:24:02 PM PDT 24
Peak memory 200404 kb
Host smart-acbe9ac6-5cdd-4b80-b4ce-63f0f855310c
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3215541761 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 17.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3215541761
Directory /workspace/17.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/17.pwrmgr_sec_cm_rstmgr_intersig_mubi.2431300506
Short name T834
Test name
Test status
Simulation time 67199414 ps
CPU time 0.94 seconds
Started Mar 28 01:23:54 PM PDT 24
Finished Mar 28 01:23:55 PM PDT 24
Peak memory 198544 kb
Host smart-cf443d41-2657-4185-a41b-f3b5b6615548
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2431300506 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_sec_cm_rstmgr_intersig
_mubi.2431300506
Directory /workspace/17.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/17.pwrmgr_smoke.397329831
Short name T293
Test name
Test status
Simulation time 29767363 ps
CPU time 0.69 seconds
Started Mar 28 01:23:57 PM PDT 24
Finished Mar 28 01:23:58 PM PDT 24
Peak memory 198660 kb
Host smart-a8fc734d-21d5-4188-a437-908ac4fe76e0
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=397329831 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_smoke.397329831
Directory /workspace/17.pwrmgr_smoke/latest

Test location /workspace/coverage/default/17.pwrmgr_stress_all.2456408580
Short name T364
Test name
Test status
Simulation time 2433381685 ps
CPU time 3.5 seconds
Started Mar 28 01:23:53 PM PDT 24
Finished Mar 28 01:23:57 PM PDT 24
Peak memory 200772 kb
Host smart-a7d2e31f-356c-473e-a58f-c84f6fd294ae
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2456408580 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_stress_all.2456408580
Directory /workspace/17.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/17.pwrmgr_stress_all_with_rand_reset.2452989308
Short name T341
Test name
Test status
Simulation time 5402752548 ps
CPU time 17.84 seconds
Started Mar 28 01:23:57 PM PDT 24
Finished Mar 28 01:24:15 PM PDT 24
Peak memory 200780 kb
Host smart-32e1f9e8-a17f-4501-a413-01a48775fa97
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2452989308 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 17.pwrmgr_stress_all_with_rand_reset.2452989308
Directory /workspace/17.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.pwrmgr_wakeup.4087208302
Short name T349
Test name
Test status
Simulation time 86625634 ps
CPU time 0.89 seconds
Started Mar 28 01:23:54 PM PDT 24
Finished Mar 28 01:23:55 PM PDT 24
Peak memory 197812 kb
Host smart-7510313a-f9b2-41fe-87ff-8fa6a8cde3dd
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4087208302 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_wakeup.4087208302
Directory /workspace/17.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/17.pwrmgr_wakeup_reset.2349497601
Short name T912
Test name
Test status
Simulation time 237026397 ps
CPU time 1.12 seconds
Started Mar 28 01:24:01 PM PDT 24
Finished Mar 28 01:24:02 PM PDT 24
Peak memory 199312 kb
Host smart-0a7b198e-db82-4180-ab48-6082f1790751
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2349497601 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_wakeup_reset.2349497601
Directory /workspace/17.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/18.pwrmgr_aborted_low_power.1078626206
Short name T328
Test name
Test status
Simulation time 23623613 ps
CPU time 0.74 seconds
Started Mar 28 01:23:56 PM PDT 24
Finished Mar 28 01:23:56 PM PDT 24
Peak memory 198424 kb
Host smart-ab3311d1-88b7-4385-9a4c-527eefafa26d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1078626206 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_aborted_low_power.1078626206
Directory /workspace/18.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/18.pwrmgr_disable_rom_integrity_check.2186875412
Short name T789
Test name
Test status
Simulation time 96440618 ps
CPU time 0.71 seconds
Started Mar 28 01:24:11 PM PDT 24
Finished Mar 28 01:24:13 PM PDT 24
Peak memory 198300 kb
Host smart-5aa29a7e-86fb-41f6-b19e-0e1793309f30
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2186875412 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_dis
able_rom_integrity_check.2186875412
Directory /workspace/18.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/18.pwrmgr_esc_clk_rst_malfunc.403878591
Short name T204
Test name
Test status
Simulation time 45855288 ps
CPU time 0.59 seconds
Started Mar 28 01:24:12 PM PDT 24
Finished Mar 28 01:24:13 PM PDT 24
Peak memory 197392 kb
Host smart-4e666ad1-a914-4c21-9156-9b3efef939dd
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=403878591 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_ma
lfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_esc_clk_rst_
malfunc.403878591
Directory /workspace/18.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/18.pwrmgr_escalation_timeout.2698325325
Short name T983
Test name
Test status
Simulation time 164733317 ps
CPU time 0.97 seconds
Started Mar 28 01:24:14 PM PDT 24
Finished Mar 28 01:24:15 PM PDT 24
Peak memory 197484 kb
Host smart-824d5a1e-6743-46fa-8b2b-081c0229295f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2698325325 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_escalation_timeout.2698325325
Directory /workspace/18.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/18.pwrmgr_glitch.3680454145
Short name T636
Test name
Test status
Simulation time 35886978 ps
CPU time 0.71 seconds
Started Mar 28 01:24:15 PM PDT 24
Finished Mar 28 01:24:16 PM PDT 24
Peak memory 197492 kb
Host smart-761f5535-90e0-4b3c-a799-02ff5af60575
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3680454145 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_glitch.3680454145
Directory /workspace/18.pwrmgr_glitch/latest

Test location /workspace/coverage/default/18.pwrmgr_global_esc.1531148226
Short name T630
Test name
Test status
Simulation time 151782075 ps
CPU time 0.57 seconds
Started Mar 28 01:24:16 PM PDT 24
Finished Mar 28 01:24:17 PM PDT 24
Peak memory 197396 kb
Host smart-015dc9f7-3153-4f52-ac0c-4fc2f0c84850
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1531148226 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_global_esc.1531148226
Directory /workspace/18.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/18.pwrmgr_lowpower_invalid.3702585392
Short name T427
Test name
Test status
Simulation time 83142576 ps
CPU time 0.67 seconds
Started Mar 28 01:24:13 PM PDT 24
Finished Mar 28 01:24:14 PM PDT 24
Peak memory 200672 kb
Host smart-02da924f-544e-4418-93cf-e56c7e7a2c56
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3702585392 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_lowpower_inval
id.3702585392
Directory /workspace/18.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/18.pwrmgr_lowpower_wakeup_race.3779556361
Short name T898
Test name
Test status
Simulation time 169318806 ps
CPU time 0.87 seconds
Started Mar 28 01:23:59 PM PDT 24
Finished Mar 28 01:24:00 PM PDT 24
Peak memory 197740 kb
Host smart-3dad2dc3-16a9-4307-90ed-86168d0ea922
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3779556361 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_lowpower_w
akeup_race.3779556361
Directory /workspace/18.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/18.pwrmgr_reset.1962542323
Short name T691
Test name
Test status
Simulation time 58270072 ps
CPU time 0.94 seconds
Started Mar 28 01:23:54 PM PDT 24
Finished Mar 28 01:23:55 PM PDT 24
Peak memory 198260 kb
Host smart-4cfcd93a-828a-40a6-90e3-b6c3de542cb5
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1962542323 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_reset.1962542323
Directory /workspace/18.pwrmgr_reset/latest

Test location /workspace/coverage/default/18.pwrmgr_reset_invalid.1413498181
Short name T319
Test name
Test status
Simulation time 115689151 ps
CPU time 0.84 seconds
Started Mar 28 01:24:11 PM PDT 24
Finished Mar 28 01:24:13 PM PDT 24
Peak memory 208820 kb
Host smart-6c45178b-393e-4fe8-a9cb-1591fd8da587
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1413498181 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_reset_invalid.1413498181
Directory /workspace/18.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/18.pwrmgr_sec_cm_ctrl_config_regwen.3588843426
Short name T798
Test name
Test status
Simulation time 155011832 ps
CPU time 0.79 seconds
Started Mar 28 01:24:11 PM PDT 24
Finished Mar 28 01:24:13 PM PDT 24
Peak memory 199144 kb
Host smart-8c49d9a0-a0e2-4698-8b38-6ce3af6b3a8c
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3588843426 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_sec_
cm_ctrl_config_regwen.3588843426
Directory /workspace/18.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/18.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.586494615
Short name T549
Test name
Test status
Simulation time 1683270629 ps
CPU time 1.88 seconds
Started Mar 28 01:23:52 PM PDT 24
Finished Mar 28 01:23:55 PM PDT 24
Peak memory 200348 kb
Host smart-fd903f1d-69e0-4314-9aba-5eb02c6fe3f8
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=586494615 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 18.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.586494615
Directory /workspace/18.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/18.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1671458851
Short name T742
Test name
Test status
Simulation time 1698732218 ps
CPU time 2.18 seconds
Started Mar 28 01:24:14 PM PDT 24
Finished Mar 28 01:24:16 PM PDT 24
Peak memory 200564 kb
Host smart-6fecd6e6-5c0f-435e-8d6b-354f3a2883d9
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1671458851 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 18.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1671458851
Directory /workspace/18.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/18.pwrmgr_sec_cm_rstmgr_intersig_mubi.2624738959
Short name T776
Test name
Test status
Simulation time 75273632 ps
CPU time 0.92 seconds
Started Mar 28 01:24:14 PM PDT 24
Finished Mar 28 01:24:16 PM PDT 24
Peak memory 198576 kb
Host smart-426ac8e1-a1ae-4efd-89d6-b302f216f56c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2624738959 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_sec_cm_rstmgr_intersig
_mubi.2624738959
Directory /workspace/18.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/18.pwrmgr_smoke.2902133753
Short name T485
Test name
Test status
Simulation time 62664564 ps
CPU time 0.64 seconds
Started Mar 28 01:23:59 PM PDT 24
Finished Mar 28 01:23:59 PM PDT 24
Peak memory 197736 kb
Host smart-5b6e98dc-4294-4293-ad5f-c2c023fd3be0
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2902133753 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_smoke.2902133753
Directory /workspace/18.pwrmgr_smoke/latest

Test location /workspace/coverage/default/18.pwrmgr_stress_all.3241395493
Short name T977
Test name
Test status
Simulation time 2176586786 ps
CPU time 7.59 seconds
Started Mar 28 01:24:15 PM PDT 24
Finished Mar 28 01:24:23 PM PDT 24
Peak memory 200648 kb
Host smart-bcf5a6a8-b4af-4bbf-9768-e906c71663f8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3241395493 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_stress_all.3241395493
Directory /workspace/18.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/18.pwrmgr_stress_all_with_rand_reset.535424077
Short name T448
Test name
Test status
Simulation time 14025398083 ps
CPU time 22.24 seconds
Started Mar 28 01:24:13 PM PDT 24
Finished Mar 28 01:24:35 PM PDT 24
Peak memory 200876 kb
Host smart-8a34ab8d-182f-4bfc-90df-369a11a6cb70
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=535424077 -assert nopost
proc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 18.pwrmgr_stress_all_with_rand_reset.535424077
Directory /workspace/18.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.pwrmgr_wakeup.1245445263
Short name T301
Test name
Test status
Simulation time 85125362 ps
CPU time 0.85 seconds
Started Mar 28 01:24:03 PM PDT 24
Finished Mar 28 01:24:04 PM PDT 24
Peak memory 197672 kb
Host smart-509508b3-c650-4b37-bd4a-9042da027475
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1245445263 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_wakeup.1245445263
Directory /workspace/18.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/18.pwrmgr_wakeup_reset.2193391268
Short name T372
Test name
Test status
Simulation time 441215281 ps
CPU time 1.11 seconds
Started Mar 28 01:24:06 PM PDT 24
Finished Mar 28 01:24:08 PM PDT 24
Peak memory 199740 kb
Host smart-1c8888ff-86f2-43a3-bd0f-f36a5e8248b4
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2193391268 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_wakeup_reset.2193391268
Directory /workspace/18.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/19.pwrmgr_aborted_low_power.3452550264
Short name T368
Test name
Test status
Simulation time 28944943 ps
CPU time 0.98 seconds
Started Mar 28 01:24:15 PM PDT 24
Finished Mar 28 01:24:16 PM PDT 24
Peak memory 200144 kb
Host smart-0b670a16-5856-4288-af4c-d3fa8aaaeae4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3452550264 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_aborted_low_power.3452550264
Directory /workspace/19.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/19.pwrmgr_disable_rom_integrity_check.2033645268
Short name T356
Test name
Test status
Simulation time 54717126 ps
CPU time 0.82 seconds
Started Mar 28 01:24:18 PM PDT 24
Finished Mar 28 01:24:19 PM PDT 24
Peak memory 198520 kb
Host smart-35aa83b3-4c26-4253-842f-983fffea87b5
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2033645268 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_dis
able_rom_integrity_check.2033645268
Directory /workspace/19.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/19.pwrmgr_esc_clk_rst_malfunc.1647724042
Short name T538
Test name
Test status
Simulation time 43238971 ps
CPU time 0.59 seconds
Started Mar 28 01:24:16 PM PDT 24
Finished Mar 28 01:24:16 PM PDT 24
Peak memory 197424 kb
Host smart-f3d7a9ed-31d8-4b40-b77d-67e49724dcd9
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1647724042 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_esc_clk_rst
_malfunc.1647724042
Directory /workspace/19.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/19.pwrmgr_escalation_timeout.2727965545
Short name T495
Test name
Test status
Simulation time 1012590794 ps
CPU time 0.97 seconds
Started Mar 28 01:24:15 PM PDT 24
Finished Mar 28 01:24:17 PM PDT 24
Peak memory 197412 kb
Host smart-b6f3903e-3c44-4c95-a741-62dfe8ea1213
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2727965545 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_escalation_timeout.2727965545
Directory /workspace/19.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/19.pwrmgr_glitch.1377921987
Short name T444
Test name
Test status
Simulation time 48938115 ps
CPU time 0.61 seconds
Started Mar 28 01:24:16 PM PDT 24
Finished Mar 28 01:24:17 PM PDT 24
Peak memory 197416 kb
Host smart-6d0aa0f8-072c-41eb-8384-fdf777fc3d6b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1377921987 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_glitch.1377921987
Directory /workspace/19.pwrmgr_glitch/latest

Test location /workspace/coverage/default/19.pwrmgr_global_esc.499657425
Short name T640
Test name
Test status
Simulation time 48413859 ps
CPU time 0.67 seconds
Started Mar 28 01:24:15 PM PDT 24
Finished Mar 28 01:24:16 PM PDT 24
Peak memory 197440 kb
Host smart-bdb4ef82-719a-48ea-8465-11bbf11a9c59
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=499657425 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_global_esc.499657425
Directory /workspace/19.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/19.pwrmgr_lowpower_invalid.3148527531
Short name T404
Test name
Test status
Simulation time 68527616 ps
CPU time 0.68 seconds
Started Mar 28 01:24:17 PM PDT 24
Finished Mar 28 01:24:18 PM PDT 24
Peak memory 200748 kb
Host smart-c20a2540-9e1f-40e0-8cec-bad62b35479f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3148527531 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_lowpower_inval
id.3148527531
Directory /workspace/19.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/19.pwrmgr_lowpower_wakeup_race.2867254559
Short name T768
Test name
Test status
Simulation time 231017196 ps
CPU time 1.04 seconds
Started Mar 28 01:24:15 PM PDT 24
Finished Mar 28 01:24:16 PM PDT 24
Peak memory 198784 kb
Host smart-d507808c-b1aa-46cd-8a1d-6643c27a1124
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2867254559 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_lowpower_w
akeup_race.2867254559
Directory /workspace/19.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/19.pwrmgr_reset.2816580024
Short name T161
Test name
Test status
Simulation time 68866554 ps
CPU time 0.66 seconds
Started Mar 28 01:24:22 PM PDT 24
Finished Mar 28 01:24:22 PM PDT 24
Peak memory 198416 kb
Host smart-9c8d4ace-41fc-4c5e-b11e-44784a89b904
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2816580024 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_reset.2816580024
Directory /workspace/19.pwrmgr_reset/latest

Test location /workspace/coverage/default/19.pwrmgr_reset_invalid.1990497276
Short name T922
Test name
Test status
Simulation time 119079771 ps
CPU time 0.84 seconds
Started Mar 28 01:24:16 PM PDT 24
Finished Mar 28 01:24:17 PM PDT 24
Peak memory 208824 kb
Host smart-f21b89b9-75f6-4237-bef8-3929c1b2e486
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1990497276 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_reset_invalid.1990497276
Directory /workspace/19.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/19.pwrmgr_sec_cm_ctrl_config_regwen.979212068
Short name T824
Test name
Test status
Simulation time 123078708 ps
CPU time 0.91 seconds
Started Mar 28 01:24:16 PM PDT 24
Finished Mar 28 01:24:17 PM PDT 24
Peak memory 199068 kb
Host smart-7782f383-c2a3-4dbc-bb36-a7787fed9eba
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=979212068 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_c
onfig_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_sec_c
m_ctrl_config_regwen.979212068
Directory /workspace/19.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/19.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3740918978
Short name T419
Test name
Test status
Simulation time 1047190584 ps
CPU time 2.12 seconds
Started Mar 28 01:24:13 PM PDT 24
Finished Mar 28 01:24:15 PM PDT 24
Peak memory 200548 kb
Host smart-fdeadc59-7f69-4b50-888b-8d9440ea742a
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3740918978 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 19.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3740918978
Directory /workspace/19.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/19.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.50044793
Short name T823
Test name
Test status
Simulation time 782636623 ps
CPU time 3.32 seconds
Started Mar 28 01:24:16 PM PDT 24
Finished Mar 28 01:24:19 PM PDT 24
Peak memory 200620 kb
Host smart-6e88dd0e-addf-41bd-b864-a88a7ba3a359
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50044793 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 19.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.50044793
Directory /workspace/19.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/19.pwrmgr_sec_cm_rstmgr_intersig_mubi.1442455751
Short name T561
Test name
Test status
Simulation time 140276400 ps
CPU time 0.9 seconds
Started Mar 28 01:24:15 PM PDT 24
Finished Mar 28 01:24:16 PM PDT 24
Peak memory 198548 kb
Host smart-f2fe70d6-d92f-4009-9c93-4b5b04fd796c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1442455751 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_sec_cm_rstmgr_intersig
_mubi.1442455751
Directory /workspace/19.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/19.pwrmgr_smoke.1184392487
Short name T502
Test name
Test status
Simulation time 132061211 ps
CPU time 0.64 seconds
Started Mar 28 01:24:13 PM PDT 24
Finished Mar 28 01:24:14 PM PDT 24
Peak memory 197848 kb
Host smart-3fed4d6f-d845-454a-b89b-3a0057b1d714
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1184392487 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_smoke.1184392487
Directory /workspace/19.pwrmgr_smoke/latest

Test location /workspace/coverage/default/19.pwrmgr_stress_all.3397780750
Short name T80
Test name
Test status
Simulation time 3415881889 ps
CPU time 4.7 seconds
Started Mar 28 01:24:16 PM PDT 24
Finished Mar 28 01:24:21 PM PDT 24
Peak memory 200708 kb
Host smart-a09e585c-d89c-4c21-b2e6-cc246926ffe3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3397780750 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_stress_all.3397780750
Directory /workspace/19.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/19.pwrmgr_stress_all_with_rand_reset.1689250605
Short name T65
Test name
Test status
Simulation time 7107760002 ps
CPU time 26.1 seconds
Started Mar 28 01:24:16 PM PDT 24
Finished Mar 28 01:24:42 PM PDT 24
Peak memory 200832 kb
Host smart-14afd83e-2c19-435a-82f7-e5c137018203
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1689250605 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 19.pwrmgr_stress_all_with_rand_reset.1689250605
Directory /workspace/19.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.pwrmgr_wakeup.488158468
Short name T594
Test name
Test status
Simulation time 428821090 ps
CPU time 0.96 seconds
Started Mar 28 01:24:22 PM PDT 24
Finished Mar 28 01:24:23 PM PDT 24
Peak memory 199040 kb
Host smart-14075417-b7ca-44ef-a61f-473344a1da89
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=488158468 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_wakeup.488158468
Directory /workspace/19.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/19.pwrmgr_wakeup_reset.2066184889
Short name T340
Test name
Test status
Simulation time 214412787 ps
CPU time 1.18 seconds
Started Mar 28 01:24:15 PM PDT 24
Finished Mar 28 01:24:16 PM PDT 24
Peak memory 199304 kb
Host smart-bcd7b6ba-8812-4a18-bd91-6907a76f5fb9
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2066184889 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_wakeup_reset.2066184889
Directory /workspace/19.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/2.pwrmgr_aborted_low_power.3833006489
Short name T78
Test name
Test status
Simulation time 46821357 ps
CPU time 1 seconds
Started Mar 28 01:22:01 PM PDT 24
Finished Mar 28 01:22:02 PM PDT 24
Peak memory 199700 kb
Host smart-656de6f0-2b58-40eb-b14e-ebf7caab6ecc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3833006489 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_aborted_low_power.3833006489
Directory /workspace/2.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/2.pwrmgr_disable_rom_integrity_check.4135710165
Short name T961
Test name
Test status
Simulation time 135068416 ps
CPU time 0.73 seconds
Started Mar 28 01:22:18 PM PDT 24
Finished Mar 28 01:22:20 PM PDT 24
Peak memory 198388 kb
Host smart-81996f0f-3b73-4541-a0a4-80cdb122e7d1
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4135710165 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_disa
ble_rom_integrity_check.4135710165
Directory /workspace/2.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/2.pwrmgr_esc_clk_rst_malfunc.3430708618
Short name T70
Test name
Test status
Simulation time 37498449 ps
CPU time 0.61 seconds
Started Mar 28 01:22:00 PM PDT 24
Finished Mar 28 01:22:01 PM PDT 24
Peak memory 197372 kb
Host smart-b03cc195-3b7c-4fcf-89b6-3d7b8d1d7154
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3430708618 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_esc_clk_rst_
malfunc.3430708618
Directory /workspace/2.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/2.pwrmgr_escalation_timeout.1000088217
Short name T869
Test name
Test status
Simulation time 608776815 ps
CPU time 0.95 seconds
Started Mar 28 01:22:00 PM PDT 24
Finished Mar 28 01:22:01 PM PDT 24
Peak memory 197420 kb
Host smart-517dfd12-ea98-436e-8d44-74f4a1fc9edb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1000088217 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_escalation_timeout.1000088217
Directory /workspace/2.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/2.pwrmgr_glitch.2115546461
Short name T272
Test name
Test status
Simulation time 29387384 ps
CPU time 0.65 seconds
Started Mar 28 01:22:15 PM PDT 24
Finished Mar 28 01:22:15 PM PDT 24
Peak memory 196704 kb
Host smart-60e7d8c7-2bb1-4ad3-84f1-7a582edee609
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2115546461 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_glitch.2115546461
Directory /workspace/2.pwrmgr_glitch/latest

Test location /workspace/coverage/default/2.pwrmgr_global_esc.1265707802
Short name T223
Test name
Test status
Simulation time 63523709 ps
CPU time 0.69 seconds
Started Mar 28 01:22:04 PM PDT 24
Finished Mar 28 01:22:05 PM PDT 24
Peak memory 197744 kb
Host smart-e9336e5d-7eb6-4811-b6bb-09cf825ce1ec
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1265707802 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_global_esc.1265707802
Directory /workspace/2.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/2.pwrmgr_lowpower_invalid.1816859815
Short name T264
Test name
Test status
Simulation time 43787655 ps
CPU time 0.73 seconds
Started Mar 28 01:22:18 PM PDT 24
Finished Mar 28 01:22:19 PM PDT 24
Peak memory 200724 kb
Host smart-bc28f4bb-5c37-4a06-93d2-e69df84ea216
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1816859815 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_lowpower_invali
d.1816859815
Directory /workspace/2.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/2.pwrmgr_lowpower_wakeup_race.867131798
Short name T377
Test name
Test status
Simulation time 30591270 ps
CPU time 0.67 seconds
Started Mar 28 01:22:03 PM PDT 24
Finished Mar 28 01:22:03 PM PDT 24
Peak memory 197620 kb
Host smart-4674a14c-5d06-43a2-9147-e7374d67986b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=867131798 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeu
p_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_lowpower_wak
eup_race.867131798
Directory /workspace/2.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/2.pwrmgr_reset.2598707620
Short name T947
Test name
Test status
Simulation time 57195035 ps
CPU time 0.89 seconds
Started Mar 28 01:22:00 PM PDT 24
Finished Mar 28 01:22:01 PM PDT 24
Peak memory 198480 kb
Host smart-ea1a379b-1a41-4e49-83ac-133dd1f57018
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2598707620 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_reset.2598707620
Directory /workspace/2.pwrmgr_reset/latest

Test location /workspace/coverage/default/2.pwrmgr_reset_invalid.1713254459
Short name T457
Test name
Test status
Simulation time 108861307 ps
CPU time 1.09 seconds
Started Mar 28 01:22:18 PM PDT 24
Finished Mar 28 01:22:20 PM PDT 24
Peak memory 208864 kb
Host smart-d3a77994-ca57-4e7f-b8a8-b046243ef7c9
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1713254459 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_reset_invalid.1713254459
Directory /workspace/2.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/2.pwrmgr_sec_cm.1744214721
Short name T3
Test name
Test status
Simulation time 654682538 ps
CPU time 2.09 seconds
Started Mar 28 01:22:20 PM PDT 24
Finished Mar 28 01:22:22 PM PDT 24
Peak memory 217584 kb
Host smart-a30be6f6-c72d-4836-985d-04900f64af6d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1744214721 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_sec_cm.1744214721
Directory /workspace/2.pwrmgr_sec_cm/latest

Test location /workspace/coverage/default/2.pwrmgr_sec_cm_ctrl_config_regwen.622603097
Short name T710
Test name
Test status
Simulation time 116704708 ps
CPU time 0.77 seconds
Started Mar 28 01:22:03 PM PDT 24
Finished Mar 28 01:22:04 PM PDT 24
Peak memory 198424 kb
Host smart-f02d74c4-9f87-4b5a-8c3b-9641ff1f647c
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=622603097 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_c
onfig_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_sec_cm
_ctrl_config_regwen.622603097
Directory /workspace/2.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/2.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3034489522
Short name T130
Test name
Test status
Simulation time 1415775290 ps
CPU time 2.19 seconds
Started Mar 28 01:22:00 PM PDT 24
Finished Mar 28 01:22:02 PM PDT 24
Peak memory 200516 kb
Host smart-df2eae7c-d747-48cb-95f5-d726976de28a
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3034489522 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 2.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3034489522
Directory /workspace/2.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/2.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.393616298
Short name T707
Test name
Test status
Simulation time 888177142 ps
CPU time 2.65 seconds
Started Mar 28 01:22:00 PM PDT 24
Finished Mar 28 01:22:03 PM PDT 24
Peak memory 200580 kb
Host smart-81200db1-9a8d-46e6-b83c-e180aa0ec2c2
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=393616298 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 2.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.393616298
Directory /workspace/2.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/2.pwrmgr_sec_cm_rstmgr_intersig_mubi.3430668022
Short name T632
Test name
Test status
Simulation time 130683857 ps
CPU time 0.89 seconds
Started Mar 28 01:22:00 PM PDT 24
Finished Mar 28 01:22:02 PM PDT 24
Peak memory 198600 kb
Host smart-c376c2dd-a633-40b6-bcba-25c678b9f3c0
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3430668022 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_sec_cm_rstmgr_intersig_
mubi.3430668022
Directory /workspace/2.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/2.pwrmgr_smoke.1260957076
Short name T5
Test name
Test status
Simulation time 53243066 ps
CPU time 0.61 seconds
Started Mar 28 01:22:07 PM PDT 24
Finished Mar 28 01:22:07 PM PDT 24
Peak memory 197764 kb
Host smart-ba151672-1ea9-4bdf-80cf-e6d1b860ae3d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1260957076 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_smoke.1260957076
Directory /workspace/2.pwrmgr_smoke/latest

Test location /workspace/coverage/default/2.pwrmgr_stress_all.2531650162
Short name T155
Test name
Test status
Simulation time 43210842 ps
CPU time 0.72 seconds
Started Mar 28 01:22:18 PM PDT 24
Finished Mar 28 01:22:19 PM PDT 24
Peak memory 198552 kb
Host smart-1914b3ba-4c9a-4d22-831e-2156fb90fbf0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2531650162 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_stress_all.2531650162
Directory /workspace/2.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/2.pwrmgr_stress_all_with_rand_reset.1304408571
Short name T110
Test name
Test status
Simulation time 14578498119 ps
CPU time 19.89 seconds
Started Mar 28 01:22:16 PM PDT 24
Finished Mar 28 01:22:36 PM PDT 24
Peak memory 200820 kb
Host smart-77a5085a-ea47-4b3b-bb69-7dc16de6d62b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1304408571 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 2.pwrmgr_stress_all_with_rand_reset.1304408571
Directory /workspace/2.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.pwrmgr_wakeup.2366576017
Short name T715
Test name
Test status
Simulation time 214395421 ps
CPU time 0.9 seconds
Started Mar 28 01:22:01 PM PDT 24
Finished Mar 28 01:22:02 PM PDT 24
Peak memory 197868 kb
Host smart-eee50cd2-0814-44d2-8c38-b4fa8ae0d65d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2366576017 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_wakeup.2366576017
Directory /workspace/2.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/2.pwrmgr_wakeup_reset.1371575831
Short name T516
Test name
Test status
Simulation time 656392028 ps
CPU time 0.92 seconds
Started Mar 28 01:22:01 PM PDT 24
Finished Mar 28 01:22:02 PM PDT 24
Peak memory 199340 kb
Host smart-fff23163-d3cf-4ea0-a72d-1ccf7535ae8c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1371575831 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_wakeup_reset.1371575831
Directory /workspace/2.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/20.pwrmgr_aborted_low_power.3858538820
Short name T591
Test name
Test status
Simulation time 28663345 ps
CPU time 0.92 seconds
Started Mar 28 01:24:16 PM PDT 24
Finished Mar 28 01:24:17 PM PDT 24
Peak memory 200216 kb
Host smart-06e22313-ac12-42e7-8083-ce2dde27b9a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3858538820 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_aborted_low_power.3858538820
Directory /workspace/20.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/20.pwrmgr_disable_rom_integrity_check.2365973448
Short name T792
Test name
Test status
Simulation time 58488380 ps
CPU time 0.79 seconds
Started Mar 28 01:24:16 PM PDT 24
Finished Mar 28 01:24:17 PM PDT 24
Peak memory 197860 kb
Host smart-1d3148e1-e50d-4164-86d3-b18cb1242205
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2365973448 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_dis
able_rom_integrity_check.2365973448
Directory /workspace/20.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/20.pwrmgr_esc_clk_rst_malfunc.28281260
Short name T281
Test name
Test status
Simulation time 39979590 ps
CPU time 0.63 seconds
Started Mar 28 01:24:20 PM PDT 24
Finished Mar 28 01:24:21 PM PDT 24
Peak memory 197380 kb
Host smart-bbdddc87-9207-4569-95e8-26a45b98de01
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28281260 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_mal
func_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_esc_clk_rst_m
alfunc.28281260
Directory /workspace/20.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/20.pwrmgr_escalation_timeout.1445363781
Short name T546
Test name
Test status
Simulation time 700523895 ps
CPU time 0.95 seconds
Started Mar 28 01:24:15 PM PDT 24
Finished Mar 28 01:24:16 PM PDT 24
Peak memory 197460 kb
Host smart-39f34e39-8d9a-4b91-a53b-de2d16188af9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1445363781 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_escalation_timeout.1445363781
Directory /workspace/20.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/20.pwrmgr_glitch.725841538
Short name T259
Test name
Test status
Simulation time 41634323 ps
CPU time 0.68 seconds
Started Mar 28 01:24:17 PM PDT 24
Finished Mar 28 01:24:18 PM PDT 24
Peak memory 197392 kb
Host smart-c2777360-8707-431f-8fbd-0fa73be76945
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=725841538 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_glitch.725841538
Directory /workspace/20.pwrmgr_glitch/latest

Test location /workspace/coverage/default/20.pwrmgr_global_esc.17894935
Short name T589
Test name
Test status
Simulation time 40111126 ps
CPU time 0.65 seconds
Started Mar 28 01:24:20 PM PDT 24
Finished Mar 28 01:24:21 PM PDT 24
Peak memory 197448 kb
Host smart-90562a27-8f2c-448e-9f40-20743aa2316b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17894935 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_global_esc.17894935
Directory /workspace/20.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/20.pwrmgr_lowpower_invalid.3387120074
Short name T34
Test name
Test status
Simulation time 120983728 ps
CPU time 0.67 seconds
Started Mar 28 01:24:16 PM PDT 24
Finished Mar 28 01:24:17 PM PDT 24
Peak memory 200748 kb
Host smart-c811c28c-8fc3-48d7-bea9-73e42d119143
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3387120074 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_lowpower_inval
id.3387120074
Directory /workspace/20.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/20.pwrmgr_lowpower_wakeup_race.602212917
Short name T381
Test name
Test status
Simulation time 129609862 ps
CPU time 0.95 seconds
Started Mar 28 01:24:15 PM PDT 24
Finished Mar 28 01:24:17 PM PDT 24
Peak memory 198372 kb
Host smart-a93d8e22-906a-4066-9cc0-233aad43b59e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=602212917 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeu
p_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_lowpower_wa
keup_race.602212917
Directory /workspace/20.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/20.pwrmgr_reset.1099953092
Short name T725
Test name
Test status
Simulation time 49212040 ps
CPU time 0.66 seconds
Started Mar 28 01:24:16 PM PDT 24
Finished Mar 28 01:24:17 PM PDT 24
Peak memory 197548 kb
Host smart-4a425972-bb5b-4151-8c1d-e152a70dd078
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1099953092 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_reset.1099953092
Directory /workspace/20.pwrmgr_reset/latest

Test location /workspace/coverage/default/20.pwrmgr_reset_invalid.903841523
Short name T518
Test name
Test status
Simulation time 110132242 ps
CPU time 0.91 seconds
Started Mar 28 01:24:15 PM PDT 24
Finished Mar 28 01:24:16 PM PDT 24
Peak memory 208908 kb
Host smart-06a9d469-08b9-4527-84f7-ac5c6d8f4064
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=903841523 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_reset_invalid.903841523
Directory /workspace/20.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/20.pwrmgr_sec_cm_ctrl_config_regwen.3607083858
Short name T453
Test name
Test status
Simulation time 177916392 ps
CPU time 0.77 seconds
Started Mar 28 01:24:19 PM PDT 24
Finished Mar 28 01:24:20 PM PDT 24
Peak memory 198760 kb
Host smart-4aedab7a-c389-46eb-815e-d3915cf5bd35
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3607083858 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_sec_
cm_ctrl_config_regwen.3607083858
Directory /workspace/20.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/20.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2747358063
Short name T627
Test name
Test status
Simulation time 979103083 ps
CPU time 2.68 seconds
Started Mar 28 01:24:17 PM PDT 24
Finished Mar 28 01:24:20 PM PDT 24
Peak memory 200312 kb
Host smart-e56374ac-ae37-4c57-8ec4-e96552081a16
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2747358063 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 20.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2747358063
Directory /workspace/20.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/20.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1377884632
Short name T689
Test name
Test status
Simulation time 930607792 ps
CPU time 2.68 seconds
Started Mar 28 01:24:13 PM PDT 24
Finished Mar 28 01:24:16 PM PDT 24
Peak memory 200592 kb
Host smart-ce4ddf2d-ffce-49b6-8377-1149053d4b3e
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1377884632 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 20.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1377884632
Directory /workspace/20.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/20.pwrmgr_sec_cm_rstmgr_intersig_mubi.1243602240
Short name T903
Test name
Test status
Simulation time 112482358 ps
CPU time 0.84 seconds
Started Mar 28 01:24:19 PM PDT 24
Finished Mar 28 01:24:21 PM PDT 24
Peak memory 198856 kb
Host smart-3a73a624-ce3c-44e6-bae9-d6cbd040938e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1243602240 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_sec_cm_rstmgr_intersig
_mubi.1243602240
Directory /workspace/20.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/20.pwrmgr_smoke.4225329323
Short name T926
Test name
Test status
Simulation time 32071099 ps
CPU time 0.67 seconds
Started Mar 28 01:24:17 PM PDT 24
Finished Mar 28 01:24:18 PM PDT 24
Peak memory 198656 kb
Host smart-bc9b4d91-595e-429a-80f3-d7902e706559
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4225329323 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_smoke.4225329323
Directory /workspace/20.pwrmgr_smoke/latest

Test location /workspace/coverage/default/20.pwrmgr_stress_all.2811401371
Short name T795
Test name
Test status
Simulation time 2434916053 ps
CPU time 3.63 seconds
Started Mar 28 01:24:15 PM PDT 24
Finished Mar 28 01:24:19 PM PDT 24
Peak memory 200720 kb
Host smart-2433e696-ba60-4189-a983-6b06f9dd04b3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2811401371 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_stress_all.2811401371
Directory /workspace/20.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/20.pwrmgr_stress_all_with_rand_reset.3749675838
Short name T112
Test name
Test status
Simulation time 7475984424 ps
CPU time 27.94 seconds
Started Mar 28 01:24:16 PM PDT 24
Finished Mar 28 01:24:44 PM PDT 24
Peak memory 200792 kb
Host smart-3e620f8a-f133-4e53-9c26-764dbf1ff1ab
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3749675838 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 20.pwrmgr_stress_all_with_rand_reset.3749675838
Directory /workspace/20.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.pwrmgr_wakeup.108328386
Short name T274
Test name
Test status
Simulation time 58279887 ps
CPU time 0.74 seconds
Started Mar 28 01:24:16 PM PDT 24
Finished Mar 28 01:24:17 PM PDT 24
Peak memory 197640 kb
Host smart-973aac39-ba27-4e5c-9764-8e50334a8913
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108328386 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_wakeup.108328386
Directory /workspace/20.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/20.pwrmgr_wakeup_reset.4112429755
Short name T712
Test name
Test status
Simulation time 587273443 ps
CPU time 0.96 seconds
Started Mar 28 01:24:15 PM PDT 24
Finished Mar 28 01:24:17 PM PDT 24
Peak memory 200428 kb
Host smart-79dc3cff-98b6-4841-9d6e-e5958643e418
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4112429755 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_wakeup_reset.4112429755
Directory /workspace/20.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/21.pwrmgr_aborted_low_power.207431114
Short name T77
Test name
Test status
Simulation time 37548465 ps
CPU time 0.64 seconds
Started Mar 28 01:24:30 PM PDT 24
Finished Mar 28 01:24:30 PM PDT 24
Peak memory 197820 kb
Host smart-d213114c-0a9c-48f0-8280-b72f26007353
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=207431114 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_aborted_low_power.207431114
Directory /workspace/21.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/21.pwrmgr_disable_rom_integrity_check.1133234707
Short name T917
Test name
Test status
Simulation time 82576401 ps
CPU time 0.7 seconds
Started Mar 28 01:24:28 PM PDT 24
Finished Mar 28 01:24:28 PM PDT 24
Peak memory 198404 kb
Host smart-c6a78f4a-5390-4d21-a0a9-e6dd504d9c3e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1133234707 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_dis
able_rom_integrity_check.1133234707
Directory /workspace/21.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/21.pwrmgr_esc_clk_rst_malfunc.2584023696
Short name T765
Test name
Test status
Simulation time 37228402 ps
CPU time 0.59 seconds
Started Mar 28 01:24:31 PM PDT 24
Finished Mar 28 01:24:31 PM PDT 24
Peak memory 196668 kb
Host smart-5200cb80-2f51-4197-919a-32cdca20952b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2584023696 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_esc_clk_rst
_malfunc.2584023696
Directory /workspace/21.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/21.pwrmgr_escalation_timeout.638286814
Short name T507
Test name
Test status
Simulation time 302383668 ps
CPU time 0.95 seconds
Started Mar 28 01:24:30 PM PDT 24
Finished Mar 28 01:24:31 PM PDT 24
Peak memory 197456 kb
Host smart-ec9011a9-ec71-450e-93a7-4af0e63c40f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=638286814 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_escalation_timeout.638286814
Directory /workspace/21.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/21.pwrmgr_glitch.2680630108
Short name T751
Test name
Test status
Simulation time 46707598 ps
CPU time 0.6 seconds
Started Mar 28 01:24:29 PM PDT 24
Finished Mar 28 01:24:30 PM PDT 24
Peak memory 197468 kb
Host smart-189b0c22-5719-4199-a8d2-02754d6a329d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2680630108 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_glitch.2680630108
Directory /workspace/21.pwrmgr_glitch/latest

Test location /workspace/coverage/default/21.pwrmgr_global_esc.1981701500
Short name T246
Test name
Test status
Simulation time 38593051 ps
CPU time 0.63 seconds
Started Mar 28 01:24:30 PM PDT 24
Finished Mar 28 01:24:31 PM PDT 24
Peak memory 197456 kb
Host smart-51657e0c-682e-4ad7-9aa1-8c92c68ee0d2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1981701500 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_global_esc.1981701500
Directory /workspace/21.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/21.pwrmgr_lowpower_invalid.1315954237
Short name T182
Test name
Test status
Simulation time 44655631 ps
CPU time 0.71 seconds
Started Mar 28 01:24:30 PM PDT 24
Finished Mar 28 01:24:31 PM PDT 24
Peak memory 200496 kb
Host smart-53522231-baae-41c5-9c2c-409fdcdb11c5
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1315954237 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_lowpower_inval
id.1315954237
Directory /workspace/21.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/21.pwrmgr_lowpower_wakeup_race.3189527307
Short name T488
Test name
Test status
Simulation time 150608867 ps
CPU time 0.87 seconds
Started Mar 28 01:24:14 PM PDT 24
Finished Mar 28 01:24:15 PM PDT 24
Peak memory 197712 kb
Host smart-f8078dde-4d6b-40f6-82f7-332c4e6e6068
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3189527307 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_lowpower_w
akeup_race.3189527307
Directory /workspace/21.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/21.pwrmgr_reset.2462135910
Short name T682
Test name
Test status
Simulation time 84854179 ps
CPU time 0.99 seconds
Started Mar 28 01:24:15 PM PDT 24
Finished Mar 28 01:24:16 PM PDT 24
Peak memory 199328 kb
Host smart-bed1a243-7a20-4018-9205-b124da97ebf3
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2462135910 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_reset.2462135910
Directory /workspace/21.pwrmgr_reset/latest

Test location /workspace/coverage/default/21.pwrmgr_reset_invalid.4211124421
Short name T458
Test name
Test status
Simulation time 117608292 ps
CPU time 0.95 seconds
Started Mar 28 01:24:28 PM PDT 24
Finished Mar 28 01:24:29 PM PDT 24
Peak memory 208792 kb
Host smart-36b4ef4e-6fcd-4a6e-9a45-4562ebea90e6
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4211124421 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_reset_invalid.4211124421
Directory /workspace/21.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/21.pwrmgr_sec_cm_ctrl_config_regwen.2441843520
Short name T466
Test name
Test status
Simulation time 241173687 ps
CPU time 1.15 seconds
Started Mar 28 01:24:28 PM PDT 24
Finished Mar 28 01:24:29 PM PDT 24
Peak memory 200220 kb
Host smart-b8546e91-5429-42cc-8ec9-5d09a58905b6
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2441843520 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_sec_
cm_ctrl_config_regwen.2441843520
Directory /workspace/21.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/21.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3813906115
Short name T279
Test name
Test status
Simulation time 985838502 ps
CPU time 2.12 seconds
Started Mar 28 01:24:36 PM PDT 24
Finished Mar 28 01:24:38 PM PDT 24
Peak memory 200400 kb
Host smart-f7477a81-15d8-4613-8265-97fb7b8097ad
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3813906115 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 21.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3813906115
Directory /workspace/21.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/21.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.4012434291
Short name T430
Test name
Test status
Simulation time 1155131331 ps
CPU time 2.3 seconds
Started Mar 28 01:24:28 PM PDT 24
Finished Mar 28 01:24:31 PM PDT 24
Peak memory 200488 kb
Host smart-01f3d242-1a04-41ac-aef4-1cacbf8a0440
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4012434291 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 21.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.4012434291
Directory /workspace/21.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/21.pwrmgr_sec_cm_rstmgr_intersig_mubi.3239609885
Short name T174
Test name
Test status
Simulation time 100443901 ps
CPU time 0.89 seconds
Started Mar 28 01:24:32 PM PDT 24
Finished Mar 28 01:24:33 PM PDT 24
Peak memory 198628 kb
Host smart-4e867b9f-76ae-42e1-9c44-1b7ebe96cba2
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3239609885 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_sec_cm_rstmgr_intersig
_mubi.3239609885
Directory /workspace/21.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/21.pwrmgr_smoke.3302554636
Short name T696
Test name
Test status
Simulation time 66528237 ps
CPU time 0.62 seconds
Started Mar 28 01:24:12 PM PDT 24
Finished Mar 28 01:24:13 PM PDT 24
Peak memory 197784 kb
Host smart-a7ad5361-1882-4a71-8317-89461ab48fe9
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3302554636 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_smoke.3302554636
Directory /workspace/21.pwrmgr_smoke/latest

Test location /workspace/coverage/default/21.pwrmgr_stress_all.4205507821
Short name T508
Test name
Test status
Simulation time 936281201 ps
CPU time 2.1 seconds
Started Mar 28 01:24:31 PM PDT 24
Finished Mar 28 01:24:34 PM PDT 24
Peak memory 200524 kb
Host smart-2ec7d36c-673d-42da-b509-fea709dab657
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4205507821 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_stress_all.4205507821
Directory /workspace/21.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/21.pwrmgr_stress_all_with_rand_reset.3191954526
Short name T41
Test name
Test status
Simulation time 8983930698 ps
CPU time 36.27 seconds
Started Mar 28 01:24:30 PM PDT 24
Finished Mar 28 01:25:07 PM PDT 24
Peak memory 200856 kb
Host smart-84a44255-b583-492a-939b-3c5899903dd0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3191954526 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 21.pwrmgr_stress_all_with_rand_reset.3191954526
Directory /workspace/21.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.pwrmgr_wakeup.2854393705
Short name T256
Test name
Test status
Simulation time 88716312 ps
CPU time 0.7 seconds
Started Mar 28 01:24:27 PM PDT 24
Finished Mar 28 01:24:28 PM PDT 24
Peak memory 198352 kb
Host smart-ce1cf020-eaed-4ec1-af08-dbeafef52eae
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2854393705 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_wakeup.2854393705
Directory /workspace/21.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/21.pwrmgr_wakeup_reset.398117098
Short name T197
Test name
Test status
Simulation time 343366116 ps
CPU time 1.05 seconds
Started Mar 28 01:24:31 PM PDT 24
Finished Mar 28 01:24:32 PM PDT 24
Peak memory 200452 kb
Host smart-bdfef17d-091b-4773-8881-341e8fb931a4
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=398117098 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_wakeup_reset.398117098
Directory /workspace/21.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/22.pwrmgr_aborted_low_power.104555429
Short name T784
Test name
Test status
Simulation time 50757017 ps
CPU time 0.79 seconds
Started Mar 28 01:24:29 PM PDT 24
Finished Mar 28 01:24:30 PM PDT 24
Peak memory 198256 kb
Host smart-5ed2dc99-cc94-4f08-bab5-70eba38fcf48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=104555429 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_aborted_low_power.104555429
Directory /workspace/22.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/22.pwrmgr_disable_rom_integrity_check.1933376148
Short name T960
Test name
Test status
Simulation time 152052714 ps
CPU time 0.71 seconds
Started Mar 28 01:24:29 PM PDT 24
Finished Mar 28 01:24:29 PM PDT 24
Peak memory 198080 kb
Host smart-b4aabc73-1ee5-4d00-97fe-48981c88203d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1933376148 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_dis
able_rom_integrity_check.1933376148
Directory /workspace/22.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/22.pwrmgr_esc_clk_rst_malfunc.363025617
Short name T510
Test name
Test status
Simulation time 28511506 ps
CPU time 0.67 seconds
Started Mar 28 01:24:30 PM PDT 24
Finished Mar 28 01:24:31 PM PDT 24
Peak memory 197296 kb
Host smart-9a570eba-7b21-41f8-9a7b-fdfe7b9233fa
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=363025617 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_ma
lfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_esc_clk_rst_
malfunc.363025617
Directory /workspace/22.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/22.pwrmgr_escalation_timeout.2468958942
Short name T422
Test name
Test status
Simulation time 166680999 ps
CPU time 1.06 seconds
Started Mar 28 01:24:30 PM PDT 24
Finished Mar 28 01:24:31 PM PDT 24
Peak memory 197396 kb
Host smart-af04e517-e366-4943-b8ce-a01053feecca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2468958942 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_escalation_timeout.2468958942
Directory /workspace/22.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/22.pwrmgr_glitch.587463981
Short name T959
Test name
Test status
Simulation time 82062647 ps
CPU time 0.63 seconds
Started Mar 28 01:24:32 PM PDT 24
Finished Mar 28 01:24:32 PM PDT 24
Peak memory 196756 kb
Host smart-cdc8b8b8-6bfc-4b93-b198-678448bbe14a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=587463981 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_glitch.587463981
Directory /workspace/22.pwrmgr_glitch/latest

Test location /workspace/coverage/default/22.pwrmgr_global_esc.3761518936
Short name T567
Test name
Test status
Simulation time 35118095 ps
CPU time 0.64 seconds
Started Mar 28 01:24:30 PM PDT 24
Finished Mar 28 01:24:30 PM PDT 24
Peak memory 197812 kb
Host smart-3683d7da-fb35-4226-b57f-988948b4daee
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3761518936 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_global_esc.3761518936
Directory /workspace/22.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/22.pwrmgr_lowpower_invalid.4244434671
Short name T849
Test name
Test status
Simulation time 45257595 ps
CPU time 0.74 seconds
Started Mar 28 01:24:29 PM PDT 24
Finished Mar 28 01:24:30 PM PDT 24
Peak memory 200592 kb
Host smart-47f4149f-82ec-4425-bd5d-af9790f0ba6c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4244434671 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_lowpower_inval
id.4244434671
Directory /workspace/22.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/22.pwrmgr_lowpower_wakeup_race.4011912654
Short name T261
Test name
Test status
Simulation time 362835577 ps
CPU time 0.98 seconds
Started Mar 28 01:24:31 PM PDT 24
Finished Mar 28 01:24:32 PM PDT 24
Peak memory 199120 kb
Host smart-c7293d9b-256b-40b7-8de4-e9834580de84
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4011912654 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_lowpower_w
akeup_race.4011912654
Directory /workspace/22.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/22.pwrmgr_reset.2362329507
Short name T743
Test name
Test status
Simulation time 216016527 ps
CPU time 0.69 seconds
Started Mar 28 01:24:30 PM PDT 24
Finished Mar 28 01:24:31 PM PDT 24
Peak memory 197836 kb
Host smart-d19ffea4-15c5-4bb0-ba50-35d408481387
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2362329507 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_reset.2362329507
Directory /workspace/22.pwrmgr_reset/latest

Test location /workspace/coverage/default/22.pwrmgr_reset_invalid.574517833
Short name T581
Test name
Test status
Simulation time 106009049 ps
CPU time 1.06 seconds
Started Mar 28 01:24:30 PM PDT 24
Finished Mar 28 01:24:32 PM PDT 24
Peak memory 208876 kb
Host smart-2102e8a6-e3e6-4d49-932d-278535ffe0ed
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=574517833 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_reset_invalid.574517833
Directory /workspace/22.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/22.pwrmgr_sec_cm_ctrl_config_regwen.3175914952
Short name T654
Test name
Test status
Simulation time 438304129 ps
CPU time 1.09 seconds
Started Mar 28 01:24:28 PM PDT 24
Finished Mar 28 01:24:30 PM PDT 24
Peak memory 200284 kb
Host smart-63faf7f1-4ba5-4e2f-ae78-73ec004f69c3
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3175914952 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_sec_
cm_ctrl_config_regwen.3175914952
Directory /workspace/22.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/22.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2432133109
Short name T244
Test name
Test status
Simulation time 1199891381 ps
CPU time 2.39 seconds
Started Mar 28 01:24:31 PM PDT 24
Finished Mar 28 01:24:34 PM PDT 24
Peak memory 200576 kb
Host smart-9e09e2dd-7d07-4e25-946f-18f44969f142
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2432133109 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 22.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2432133109
Directory /workspace/22.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/22.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3529488890
Short name T817
Test name
Test status
Simulation time 1286011482 ps
CPU time 2.38 seconds
Started Mar 28 01:24:31 PM PDT 24
Finished Mar 28 01:24:33 PM PDT 24
Peak memory 200596 kb
Host smart-6342dbd1-149f-4ccb-8fbe-4805c7cd7bb9
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3529488890 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 22.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3529488890
Directory /workspace/22.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/22.pwrmgr_sec_cm_rstmgr_intersig_mubi.2181761790
Short name T262
Test name
Test status
Simulation time 190133722 ps
CPU time 0.85 seconds
Started Mar 28 01:24:28 PM PDT 24
Finished Mar 28 01:24:29 PM PDT 24
Peak memory 198372 kb
Host smart-3e516245-c3ad-446a-a129-7299b240b066
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2181761790 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_sec_cm_rstmgr_intersig
_mubi.2181761790
Directory /workspace/22.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/22.pwrmgr_smoke.3133085899
Short name T962
Test name
Test status
Simulation time 39732042 ps
CPU time 0.66 seconds
Started Mar 28 01:24:29 PM PDT 24
Finished Mar 28 01:24:29 PM PDT 24
Peak memory 197816 kb
Host smart-4adc3b26-b1d7-42df-9435-84d73ddefb6d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3133085899 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_smoke.3133085899
Directory /workspace/22.pwrmgr_smoke/latest

Test location /workspace/coverage/default/22.pwrmgr_stress_all.2824800256
Short name T726
Test name
Test status
Simulation time 2142242607 ps
CPU time 7.42 seconds
Started Mar 28 01:24:32 PM PDT 24
Finished Mar 28 01:24:39 PM PDT 24
Peak memory 200616 kb
Host smart-1cff680a-07bc-4524-8ea0-5ea71a3c70a5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2824800256 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_stress_all.2824800256
Directory /workspace/22.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/22.pwrmgr_stress_all_with_rand_reset.2141030049
Short name T40
Test name
Test status
Simulation time 12613409850 ps
CPU time 24.48 seconds
Started Mar 28 01:24:32 PM PDT 24
Finished Mar 28 01:24:56 PM PDT 24
Peak memory 200860 kb
Host smart-29b580de-d1a8-4297-87c5-f52ca9edeccd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2141030049 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 22.pwrmgr_stress_all_with_rand_reset.2141030049
Directory /workspace/22.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.pwrmgr_wakeup.2348021598
Short name T396
Test name
Test status
Simulation time 127121638 ps
CPU time 0.71 seconds
Started Mar 28 01:24:31 PM PDT 24
Finished Mar 28 01:24:31 PM PDT 24
Peak memory 197612 kb
Host smart-523b02d2-6736-40b6-8f5a-a962b14b44cf
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2348021598 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_wakeup.2348021598
Directory /workspace/22.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/22.pwrmgr_wakeup_reset.358140425
Short name T247
Test name
Test status
Simulation time 190955146 ps
CPU time 0.84 seconds
Started Mar 28 01:24:33 PM PDT 24
Finished Mar 28 01:24:34 PM PDT 24
Peak memory 198952 kb
Host smart-9be13920-4a5f-4682-8419-98f065297a16
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=358140425 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_wakeup_reset.358140425
Directory /workspace/22.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/23.pwrmgr_aborted_low_power.121481719
Short name T323
Test name
Test status
Simulation time 67938855 ps
CPU time 0.82 seconds
Started Mar 28 01:24:30 PM PDT 24
Finished Mar 28 01:24:31 PM PDT 24
Peak memory 199340 kb
Host smart-d58f3cb6-849e-491f-87f3-5949eb76e8ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=121481719 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_aborted_low_power.121481719
Directory /workspace/23.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/23.pwrmgr_esc_clk_rst_malfunc.1190513995
Short name T238
Test name
Test status
Simulation time 64204559 ps
CPU time 0.61 seconds
Started Mar 28 01:24:33 PM PDT 24
Finished Mar 28 01:24:34 PM PDT 24
Peak memory 197352 kb
Host smart-19fb1eca-a590-4191-aca1-4bf4676cc3ef
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1190513995 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_esc_clk_rst
_malfunc.1190513995
Directory /workspace/23.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/23.pwrmgr_escalation_timeout.1680190679
Short name T948
Test name
Test status
Simulation time 692858765 ps
CPU time 1 seconds
Started Mar 28 01:24:33 PM PDT 24
Finished Mar 28 01:24:34 PM PDT 24
Peak memory 197752 kb
Host smart-a909a415-5708-462d-bbbd-b844e110003a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1680190679 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_escalation_timeout.1680190679
Directory /workspace/23.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/23.pwrmgr_glitch.878014799
Short name T753
Test name
Test status
Simulation time 32123111 ps
CPU time 0.64 seconds
Started Mar 28 01:24:30 PM PDT 24
Finished Mar 28 01:24:31 PM PDT 24
Peak memory 197492 kb
Host smart-85f4c7a8-b2df-4738-b409-aeb6da8bb149
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=878014799 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_glitch.878014799
Directory /workspace/23.pwrmgr_glitch/latest

Test location /workspace/coverage/default/23.pwrmgr_global_esc.4058828913
Short name T814
Test name
Test status
Simulation time 46161775 ps
CPU time 0.63 seconds
Started Mar 28 01:24:31 PM PDT 24
Finished Mar 28 01:24:32 PM PDT 24
Peak memory 197392 kb
Host smart-2781fb55-4838-454e-b32e-35c2677bcf09
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4058828913 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_global_esc.4058828913
Directory /workspace/23.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/23.pwrmgr_lowpower_invalid.3670569933
Short name T628
Test name
Test status
Simulation time 54861130 ps
CPU time 0.71 seconds
Started Mar 28 01:24:33 PM PDT 24
Finished Mar 28 01:24:34 PM PDT 24
Peak memory 200736 kb
Host smart-51c30314-1e8f-4869-a7af-683b975ea904
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3670569933 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_lowpower_inval
id.3670569933
Directory /workspace/23.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/23.pwrmgr_lowpower_wakeup_race.142704595
Short name T196
Test name
Test status
Simulation time 23344645 ps
CPU time 0.66 seconds
Started Mar 28 01:24:28 PM PDT 24
Finished Mar 28 01:24:29 PM PDT 24
Peak memory 198372 kb
Host smart-90e1d290-6cd3-4431-9088-e857a00233ae
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=142704595 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeu
p_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_lowpower_wa
keup_race.142704595
Directory /workspace/23.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/23.pwrmgr_reset.4280443239
Short name T118
Test name
Test status
Simulation time 64303249 ps
CPU time 0.87 seconds
Started Mar 28 01:24:32 PM PDT 24
Finished Mar 28 01:24:33 PM PDT 24
Peak memory 198020 kb
Host smart-7f68c63e-5f48-44e6-99ff-cd62bc52613d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4280443239 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_reset.4280443239
Directory /workspace/23.pwrmgr_reset/latest

Test location /workspace/coverage/default/23.pwrmgr_reset_invalid.3069989246
Short name T936
Test name
Test status
Simulation time 177428698 ps
CPU time 0.81 seconds
Started Mar 28 01:24:31 PM PDT 24
Finished Mar 28 01:24:32 PM PDT 24
Peak memory 208896 kb
Host smart-97ed3ea3-46cb-4e99-a824-64a53dfb0e8e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3069989246 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_reset_invalid.3069989246
Directory /workspace/23.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/23.pwrmgr_sec_cm_ctrl_config_regwen.2070905816
Short name T870
Test name
Test status
Simulation time 183266687 ps
CPU time 0.83 seconds
Started Mar 28 01:24:31 PM PDT 24
Finished Mar 28 01:24:32 PM PDT 24
Peak memory 198440 kb
Host smart-d2cdc35e-43d8-4767-874d-43c86bf3b8f5
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2070905816 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_sec_
cm_ctrl_config_regwen.2070905816
Directory /workspace/23.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/23.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2935551669
Short name T863
Test name
Test status
Simulation time 882775116 ps
CPU time 2.89 seconds
Started Mar 28 01:24:29 PM PDT 24
Finished Mar 28 01:24:32 PM PDT 24
Peak memory 200576 kb
Host smart-977e9436-8e1f-4a0c-9058-f98d1f092f20
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2935551669 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 23.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2935551669
Directory /workspace/23.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/23.pwrmgr_sec_cm_rstmgr_intersig_mubi.492910915
Short name T152
Test name
Test status
Simulation time 54470022 ps
CPU time 0.91 seconds
Started Mar 28 01:24:30 PM PDT 24
Finished Mar 28 01:24:32 PM PDT 24
Peak memory 198420 kb
Host smart-e3319585-0a69-4abe-8694-56c5116b62fe
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=492910915 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_sec_cm_rstmgr_intersig_
mubi.492910915
Directory /workspace/23.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/23.pwrmgr_smoke.1392506943
Short name T181
Test name
Test status
Simulation time 51581883 ps
CPU time 0.6 seconds
Started Mar 28 01:24:27 PM PDT 24
Finished Mar 28 01:24:27 PM PDT 24
Peak memory 197848 kb
Host smart-300da6e9-1a48-4157-bd41-4543aef58c79
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1392506943 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_smoke.1392506943
Directory /workspace/23.pwrmgr_smoke/latest

Test location /workspace/coverage/default/23.pwrmgr_stress_all.1515411597
Short name T929
Test name
Test status
Simulation time 3652009595 ps
CPU time 6.05 seconds
Started Mar 28 01:24:34 PM PDT 24
Finished Mar 28 01:24:40 PM PDT 24
Peak memory 200612 kb
Host smart-2c8cb3a5-0425-414a-a3c2-cd904f72e6fb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1515411597 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_stress_all.1515411597
Directory /workspace/23.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/23.pwrmgr_stress_all_with_rand_reset.1371578350
Short name T36
Test name
Test status
Simulation time 8091593261 ps
CPU time 25.98 seconds
Started Mar 28 01:24:32 PM PDT 24
Finished Mar 28 01:24:58 PM PDT 24
Peak memory 200892 kb
Host smart-68d5c38c-6a51-4805-92df-28ed0c2c5907
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1371578350 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 23.pwrmgr_stress_all_with_rand_reset.1371578350
Directory /workspace/23.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.pwrmgr_wakeup.2596826283
Short name T525
Test name
Test status
Simulation time 136952715 ps
CPU time 0.82 seconds
Started Mar 28 01:24:31 PM PDT 24
Finished Mar 28 01:24:32 PM PDT 24
Peak memory 197616 kb
Host smart-313a45c8-e35c-4e3a-9862-d97ffa5ba668
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2596826283 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_wakeup.2596826283
Directory /workspace/23.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/23.pwrmgr_wakeup_reset.3932430530
Short name T858
Test name
Test status
Simulation time 402540350 ps
CPU time 1 seconds
Started Mar 28 01:24:30 PM PDT 24
Finished Mar 28 01:24:32 PM PDT 24
Peak memory 199372 kb
Host smart-4970e65d-75a1-4f19-ae03-2f6ccccc843a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3932430530 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_wakeup_reset.3932430530
Directory /workspace/23.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/24.pwrmgr_aborted_low_power.2062744351
Short name T367
Test name
Test status
Simulation time 26622474 ps
CPU time 0.72 seconds
Started Mar 28 01:24:33 PM PDT 24
Finished Mar 28 01:24:34 PM PDT 24
Peak memory 197796 kb
Host smart-c353dd8a-aac1-489a-a988-8278327120da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2062744351 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_aborted_low_power.2062744351
Directory /workspace/24.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/24.pwrmgr_disable_rom_integrity_check.2066142525
Short name T307
Test name
Test status
Simulation time 88747307 ps
CPU time 0.75 seconds
Started Mar 28 01:24:36 PM PDT 24
Finished Mar 28 01:24:37 PM PDT 24
Peak memory 198800 kb
Host smart-b6dedf8b-eb78-4c42-9486-72caf4bb9701
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2066142525 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_dis
able_rom_integrity_check.2066142525
Directory /workspace/24.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/24.pwrmgr_esc_clk_rst_malfunc.3090440171
Short name T12
Test name
Test status
Simulation time 39124987 ps
CPU time 0.59 seconds
Started Mar 28 01:24:30 PM PDT 24
Finished Mar 28 01:24:30 PM PDT 24
Peak memory 197396 kb
Host smart-4c2ffb07-d62e-4ad9-903a-49b9659b799c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3090440171 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_esc_clk_rst
_malfunc.3090440171
Directory /workspace/24.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/24.pwrmgr_escalation_timeout.853515512
Short name T950
Test name
Test status
Simulation time 167040758 ps
CPU time 0.99 seconds
Started Mar 28 01:24:36 PM PDT 24
Finished Mar 28 01:24:37 PM PDT 24
Peak memory 196756 kb
Host smart-4e8f9957-23c9-4f0a-9fe2-4927a0cd6cc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=853515512 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_escalation_timeout.853515512
Directory /workspace/24.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/24.pwrmgr_glitch.3303679547
Short name T536
Test name
Test status
Simulation time 43922081 ps
CPU time 0.58 seconds
Started Mar 28 01:24:33 PM PDT 24
Finished Mar 28 01:24:34 PM PDT 24
Peak memory 196708 kb
Host smart-cb77f3b1-e3cd-4280-ae68-708075b49778
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3303679547 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_glitch.3303679547
Directory /workspace/24.pwrmgr_glitch/latest

Test location /workspace/coverage/default/24.pwrmgr_global_esc.899411956
Short name T602
Test name
Test status
Simulation time 38030542 ps
CPU time 0.6 seconds
Started Mar 28 01:24:36 PM PDT 24
Finished Mar 28 01:24:37 PM PDT 24
Peak memory 196788 kb
Host smart-9d592643-abe0-4305-9c94-639ee51d8f7e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=899411956 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_global_esc.899411956
Directory /workspace/24.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/24.pwrmgr_lowpower_invalid.3372093021
Short name T731
Test name
Test status
Simulation time 82043845 ps
CPU time 0.67 seconds
Started Mar 28 01:24:47 PM PDT 24
Finished Mar 28 01:24:48 PM PDT 24
Peak memory 200744 kb
Host smart-7ab5b699-4693-47e4-bb18-a04291729735
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3372093021 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_lowpower_inval
id.3372093021
Directory /workspace/24.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/24.pwrmgr_lowpower_wakeup_race.2708134475
Short name T888
Test name
Test status
Simulation time 139170967 ps
CPU time 0.78 seconds
Started Mar 28 01:24:31 PM PDT 24
Finished Mar 28 01:24:32 PM PDT 24
Peak memory 197748 kb
Host smart-579e9a1c-a3c5-4b66-9ff4-7fdeadce6411
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2708134475 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_lowpower_w
akeup_race.2708134475
Directory /workspace/24.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/24.pwrmgr_reset.3941226396
Short name T553
Test name
Test status
Simulation time 76327482 ps
CPU time 1.01 seconds
Started Mar 28 01:24:36 PM PDT 24
Finished Mar 28 01:24:37 PM PDT 24
Peak memory 199408 kb
Host smart-a953cccc-6fa4-49bf-b2e0-73967da9463e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3941226396 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_reset.3941226396
Directory /workspace/24.pwrmgr_reset/latest

Test location /workspace/coverage/default/24.pwrmgr_reset_invalid.1552708611
Short name T178
Test name
Test status
Simulation time 185607004 ps
CPU time 0.8 seconds
Started Mar 28 01:24:45 PM PDT 24
Finished Mar 28 01:24:47 PM PDT 24
Peak memory 208756 kb
Host smart-a8cff873-eee1-4e6f-b3fd-74ad1bc2df76
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1552708611 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_reset_invalid.1552708611
Directory /workspace/24.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/24.pwrmgr_sec_cm_ctrl_config_regwen.1648607299
Short name T674
Test name
Test status
Simulation time 294552628 ps
CPU time 1.4 seconds
Started Mar 28 01:24:31 PM PDT 24
Finished Mar 28 01:24:33 PM PDT 24
Peak memory 200260 kb
Host smart-f8705698-ae72-4f91-ae9c-cd0225133502
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1648607299 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_sec_
cm_ctrl_config_regwen.1648607299
Directory /workspace/24.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/24.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3577517725
Short name T572
Test name
Test status
Simulation time 1171439931 ps
CPU time 2.26 seconds
Started Mar 28 01:24:33 PM PDT 24
Finished Mar 28 01:24:35 PM PDT 24
Peak memory 200404 kb
Host smart-5cf5c2e2-6856-4d6e-933d-c4b7f972fa97
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3577517725 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 24.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3577517725
Directory /workspace/24.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/24.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1150679090
Short name T418
Test name
Test status
Simulation time 1190010561 ps
CPU time 2.22 seconds
Started Mar 28 01:24:33 PM PDT 24
Finished Mar 28 01:24:35 PM PDT 24
Peak memory 200456 kb
Host smart-caa11401-98d4-4540-9861-0cd0663ee303
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1150679090 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 24.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1150679090
Directory /workspace/24.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/24.pwrmgr_sec_cm_rstmgr_intersig_mubi.2193396158
Short name T896
Test name
Test status
Simulation time 102631830 ps
CPU time 0.8 seconds
Started Mar 28 01:24:33 PM PDT 24
Finished Mar 28 01:24:34 PM PDT 24
Peak memory 198564 kb
Host smart-210a3267-2c6c-422a-a613-f10a2481ed14
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2193396158 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_sec_cm_rstmgr_intersig
_mubi.2193396158
Directory /workspace/24.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/24.pwrmgr_smoke.3821218903
Short name T873
Test name
Test status
Simulation time 28805820 ps
CPU time 0.71 seconds
Started Mar 28 01:24:33 PM PDT 24
Finished Mar 28 01:24:34 PM PDT 24
Peak memory 198676 kb
Host smart-67349507-540c-49ff-a8e6-f8761d9de778
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3821218903 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_smoke.3821218903
Directory /workspace/24.pwrmgr_smoke/latest

Test location /workspace/coverage/default/24.pwrmgr_stress_all.3878716359
Short name T2
Test name
Test status
Simulation time 485070731 ps
CPU time 1.94 seconds
Started Mar 28 01:24:48 PM PDT 24
Finished Mar 28 01:24:50 PM PDT 24
Peak memory 200544 kb
Host smart-67f8b88c-bd94-493d-bab4-e5773cee304a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3878716359 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_stress_all.3878716359
Directory /workspace/24.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/24.pwrmgr_stress_all_with_rand_reset.497764444
Short name T114
Test name
Test status
Simulation time 6386379788 ps
CPU time 7.98 seconds
Started Mar 28 01:24:50 PM PDT 24
Finished Mar 28 01:24:58 PM PDT 24
Peak memory 200868 kb
Host smart-253eb98a-b8d9-4a89-9615-aed71a1ff752
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=497764444 -assert nopost
proc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 24.pwrmgr_stress_all_with_rand_reset.497764444
Directory /workspace/24.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.pwrmgr_wakeup.2095918085
Short name T175
Test name
Test status
Simulation time 129823399 ps
CPU time 0.92 seconds
Started Mar 28 01:24:33 PM PDT 24
Finished Mar 28 01:24:34 PM PDT 24
Peak memory 198420 kb
Host smart-8990c43d-d2e3-4e67-a0a4-4d16b903334a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2095918085 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_wakeup.2095918085
Directory /workspace/24.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/24.pwrmgr_wakeup_reset.981142175
Short name T723
Test name
Test status
Simulation time 110334107 ps
CPU time 0.72 seconds
Started Mar 28 01:24:30 PM PDT 24
Finished Mar 28 01:24:31 PM PDT 24
Peak memory 198432 kb
Host smart-ccd9e91e-b97d-4415-98c1-44ce4bb7714b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=981142175 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_wakeup_reset.981142175
Directory /workspace/24.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/25.pwrmgr_aborted_low_power.3381186957
Short name T360
Test name
Test status
Simulation time 31053408 ps
CPU time 0.68 seconds
Started Mar 28 01:24:45 PM PDT 24
Finished Mar 28 01:24:47 PM PDT 24
Peak memory 198360 kb
Host smart-a5de2082-562a-47a0-8fd4-17e7f3611d96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3381186957 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_aborted_low_power.3381186957
Directory /workspace/25.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/25.pwrmgr_disable_rom_integrity_check.1968817293
Short name T573
Test name
Test status
Simulation time 48346649 ps
CPU time 0.82 seconds
Started Mar 28 01:24:51 PM PDT 24
Finished Mar 28 01:24:52 PM PDT 24
Peak memory 198492 kb
Host smart-892f67d2-6a08-4908-8965-03d4bcd14e76
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1968817293 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_dis
able_rom_integrity_check.1968817293
Directory /workspace/25.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/25.pwrmgr_esc_clk_rst_malfunc.2999217371
Short name T199
Test name
Test status
Simulation time 40562841 ps
CPU time 0.61 seconds
Started Mar 28 01:24:45 PM PDT 24
Finished Mar 28 01:24:47 PM PDT 24
Peak memory 197384 kb
Host smart-240bc1e2-0cfb-4f31-8c58-27a999e3f744
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2999217371 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_esc_clk_rst
_malfunc.2999217371
Directory /workspace/25.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/25.pwrmgr_glitch.1675141799
Short name T582
Test name
Test status
Simulation time 48599627 ps
CPU time 0.68 seconds
Started Mar 28 01:24:47 PM PDT 24
Finished Mar 28 01:24:48 PM PDT 24
Peak memory 196684 kb
Host smart-660484b9-b9d2-4d5d-838f-855fc6b4bbf3
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1675141799 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_glitch.1675141799
Directory /workspace/25.pwrmgr_glitch/latest

Test location /workspace/coverage/default/25.pwrmgr_global_esc.2190695023
Short name T987
Test name
Test status
Simulation time 24865376 ps
CPU time 0.63 seconds
Started Mar 28 01:24:47 PM PDT 24
Finished Mar 28 01:24:48 PM PDT 24
Peak memory 197464 kb
Host smart-feae9a65-c5f9-4123-84ce-84ce5bb66cdc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2190695023 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_global_esc.2190695023
Directory /workspace/25.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/25.pwrmgr_lowpower_invalid.2349652557
Short name T793
Test name
Test status
Simulation time 43676810 ps
CPU time 0.69 seconds
Started Mar 28 01:24:46 PM PDT 24
Finished Mar 28 01:24:47 PM PDT 24
Peak memory 200784 kb
Host smart-64e4ece6-0eda-4e15-8a7e-240a6b95e02f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2349652557 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_lowpower_inval
id.2349652557
Directory /workspace/25.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/25.pwrmgr_lowpower_wakeup_race.249700223
Short name T440
Test name
Test status
Simulation time 48181847 ps
CPU time 0.71 seconds
Started Mar 28 01:24:44 PM PDT 24
Finished Mar 28 01:24:45 PM PDT 24
Peak memory 197624 kb
Host smart-672c362d-1e49-4b51-901d-8dc27439dfe1
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=249700223 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeu
p_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_lowpower_wa
keup_race.249700223
Directory /workspace/25.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/25.pwrmgr_reset.1550802230
Short name T252
Test name
Test status
Simulation time 272033777 ps
CPU time 0.86 seconds
Started Mar 28 01:24:46 PM PDT 24
Finished Mar 28 01:24:47 PM PDT 24
Peak memory 199180 kb
Host smart-5d950506-cacf-4aa3-9a08-a92b2fc54404
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1550802230 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_reset.1550802230
Directory /workspace/25.pwrmgr_reset/latest

Test location /workspace/coverage/default/25.pwrmgr_sec_cm_ctrl_config_regwen.2210946358
Short name T570
Test name
Test status
Simulation time 560105336 ps
CPU time 1.02 seconds
Started Mar 28 01:24:50 PM PDT 24
Finished Mar 28 01:24:51 PM PDT 24
Peak memory 199268 kb
Host smart-497fb56e-28c6-49a9-939f-55587b06fd45
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2210946358 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_sec_
cm_ctrl_config_regwen.2210946358
Directory /workspace/25.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/25.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3844993439
Short name T503
Test name
Test status
Simulation time 1060391889 ps
CPU time 2.24 seconds
Started Mar 28 01:24:50 PM PDT 24
Finished Mar 28 01:24:53 PM PDT 24
Peak memory 200612 kb
Host smart-8d7b72de-f818-4f4d-841b-d8ef6304acb3
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3844993439 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 25.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3844993439
Directory /workspace/25.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/25.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1154879604
Short name T169
Test name
Test status
Simulation time 785385132 ps
CPU time 3.26 seconds
Started Mar 28 01:24:47 PM PDT 24
Finished Mar 28 01:24:50 PM PDT 24
Peak memory 200452 kb
Host smart-da450bc9-3bf3-4e3d-ae6a-a58617be18f1
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1154879604 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 25.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1154879604
Directory /workspace/25.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/25.pwrmgr_sec_cm_rstmgr_intersig_mubi.3959324553
Short name T390
Test name
Test status
Simulation time 162639172 ps
CPU time 0.88 seconds
Started Mar 28 01:24:45 PM PDT 24
Finished Mar 28 01:24:47 PM PDT 24
Peak memory 198656 kb
Host smart-384c4920-f145-4fda-925a-22beebe87016
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3959324553 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_sec_cm_rstmgr_intersig
_mubi.3959324553
Directory /workspace/25.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/25.pwrmgr_smoke.1560709918
Short name T652
Test name
Test status
Simulation time 33550164 ps
CPU time 0.68 seconds
Started Mar 28 01:24:47 PM PDT 24
Finished Mar 28 01:24:48 PM PDT 24
Peak memory 198652 kb
Host smart-7554b700-5541-4410-adc1-e94514cae5bb
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1560709918 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_smoke.1560709918
Directory /workspace/25.pwrmgr_smoke/latest

Test location /workspace/coverage/default/25.pwrmgr_stress_all.1220300827
Short name T318
Test name
Test status
Simulation time 681369131 ps
CPU time 2.41 seconds
Started Mar 28 01:24:49 PM PDT 24
Finished Mar 28 01:24:52 PM PDT 24
Peak memory 200576 kb
Host smart-c8cb0d2f-8775-4d20-93d2-e85f1083cb35
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1220300827 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_stress_all.1220300827
Directory /workspace/25.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/25.pwrmgr_stress_all_with_rand_reset.3728391539
Short name T579
Test name
Test status
Simulation time 7196026715 ps
CPU time 7.67 seconds
Started Mar 28 01:24:44 PM PDT 24
Finished Mar 28 01:24:53 PM PDT 24
Peak memory 200864 kb
Host smart-643d276b-0a53-4b65-8b24-e330bce2b545
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3728391539 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 25.pwrmgr_stress_all_with_rand_reset.3728391539
Directory /workspace/25.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.pwrmgr_wakeup.1635953980
Short name T219
Test name
Test status
Simulation time 260310757 ps
CPU time 1.3 seconds
Started Mar 28 01:24:49 PM PDT 24
Finished Mar 28 01:24:50 PM PDT 24
Peak memory 199052 kb
Host smart-62580353-5da8-4d04-9f80-ad6323a7fb69
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1635953980 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_wakeup.1635953980
Directory /workspace/25.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/25.pwrmgr_wakeup_reset.2689878
Short name T498
Test name
Test status
Simulation time 322422694 ps
CPU time 1.46 seconds
Started Mar 28 01:24:46 PM PDT 24
Finished Mar 28 01:24:48 PM PDT 24
Peak memory 200452 kb
Host smart-473b34b3-5044-4250-b49f-fae9e409d396
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2689878 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_wakeup_reset.2689878
Directory /workspace/25.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/26.pwrmgr_aborted_low_power.790507316
Short name T84
Test name
Test status
Simulation time 44558936 ps
CPU time 0.86 seconds
Started Mar 28 01:24:43 PM PDT 24
Finished Mar 28 01:24:44 PM PDT 24
Peak memory 199636 kb
Host smart-5f7f498d-2a45-4429-88fb-a498d7a1f62d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=790507316 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_aborted_low_power.790507316
Directory /workspace/26.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/26.pwrmgr_disable_rom_integrity_check.1387539097
Short name T876
Test name
Test status
Simulation time 58562238 ps
CPU time 0.9 seconds
Started Mar 28 01:24:46 PM PDT 24
Finished Mar 28 01:24:47 PM PDT 24
Peak memory 199420 kb
Host smart-c2bec2da-49e2-4b04-8296-60a991f405b6
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1387539097 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_dis
able_rom_integrity_check.1387539097
Directory /workspace/26.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/26.pwrmgr_esc_clk_rst_malfunc.1797056034
Short name T537
Test name
Test status
Simulation time 38666161 ps
CPU time 0.62 seconds
Started Mar 28 01:24:48 PM PDT 24
Finished Mar 28 01:24:49 PM PDT 24
Peak memory 197408 kb
Host smart-49dfe145-bec0-4051-a918-bc376f4f28ca
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1797056034 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_esc_clk_rst
_malfunc.1797056034
Directory /workspace/26.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/26.pwrmgr_escalation_timeout.1417156310
Short name T206
Test name
Test status
Simulation time 639887830 ps
CPU time 0.98 seconds
Started Mar 28 01:24:47 PM PDT 24
Finished Mar 28 01:24:48 PM PDT 24
Peak memory 197460 kb
Host smart-1855e288-d80a-49ff-9c86-99ea13b9ef5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1417156310 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_escalation_timeout.1417156310
Directory /workspace/26.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/26.pwrmgr_glitch.2590408455
Short name T839
Test name
Test status
Simulation time 49411218 ps
CPU time 0.65 seconds
Started Mar 28 01:24:44 PM PDT 24
Finished Mar 28 01:24:46 PM PDT 24
Peak memory 196768 kb
Host smart-8c21298f-22cb-492e-a5cf-0519983f4acd
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2590408455 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_glitch.2590408455
Directory /workspace/26.pwrmgr_glitch/latest

Test location /workspace/coverage/default/26.pwrmgr_global_esc.4195484117
Short name T872
Test name
Test status
Simulation time 136365845 ps
CPU time 0.57 seconds
Started Mar 28 01:24:51 PM PDT 24
Finished Mar 28 01:24:52 PM PDT 24
Peak memory 197784 kb
Host smart-40913e53-9a6f-4fba-a841-df5a4716400a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4195484117 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_global_esc.4195484117
Directory /workspace/26.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/26.pwrmgr_lowpower_invalid.4077207478
Short name T705
Test name
Test status
Simulation time 55894789 ps
CPU time 0.66 seconds
Started Mar 28 01:24:46 PM PDT 24
Finished Mar 28 01:24:47 PM PDT 24
Peak memory 200756 kb
Host smart-ccd8058a-bb5b-461f-a925-128bd6d619d4
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4077207478 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_lowpower_inval
id.4077207478
Directory /workspace/26.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/26.pwrmgr_lowpower_wakeup_race.2525337302
Short name T629
Test name
Test status
Simulation time 63797927 ps
CPU time 0.74 seconds
Started Mar 28 01:24:52 PM PDT 24
Finished Mar 28 01:24:53 PM PDT 24
Peak memory 197524 kb
Host smart-78294cd4-fd83-45cc-9da7-03965baa6fcd
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2525337302 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_lowpower_w
akeup_race.2525337302
Directory /workspace/26.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/26.pwrmgr_reset.2387240471
Short name T376
Test name
Test status
Simulation time 60317693 ps
CPU time 0.85 seconds
Started Mar 28 01:24:48 PM PDT 24
Finished Mar 28 01:24:49 PM PDT 24
Peak memory 198408 kb
Host smart-a4295afb-ec29-4e9a-a11b-dd6baee8dd6b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2387240471 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_reset.2387240471
Directory /workspace/26.pwrmgr_reset/latest

Test location /workspace/coverage/default/26.pwrmgr_reset_invalid.10280947
Short name T387
Test name
Test status
Simulation time 163367900 ps
CPU time 0.81 seconds
Started Mar 28 01:24:46 PM PDT 24
Finished Mar 28 01:24:47 PM PDT 24
Peak memory 208840 kb
Host smart-11d8a31e-6c66-428b-a002-15c423b6e263
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10280947 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_reset_invalid.10280947
Directory /workspace/26.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/26.pwrmgr_sec_cm_ctrl_config_regwen.2054412268
Short name T248
Test name
Test status
Simulation time 264005095 ps
CPU time 1.37 seconds
Started Mar 28 01:24:43 PM PDT 24
Finished Mar 28 01:24:45 PM PDT 24
Peak memory 200308 kb
Host smart-d997f4ed-0ee2-4074-98d6-e4ba977fd9b6
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2054412268 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_sec_
cm_ctrl_config_regwen.2054412268
Directory /workspace/26.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/26.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3025516650
Short name T769
Test name
Test status
Simulation time 847191350 ps
CPU time 3.08 seconds
Started Mar 28 01:24:44 PM PDT 24
Finished Mar 28 01:24:48 PM PDT 24
Peak memory 200536 kb
Host smart-efedb5c7-d2c0-454f-9c96-c01f7eea36ad
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3025516650 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 26.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3025516650
Directory /workspace/26.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/26.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2008355538
Short name T687
Test name
Test status
Simulation time 849870357 ps
CPU time 3.29 seconds
Started Mar 28 01:24:47 PM PDT 24
Finished Mar 28 01:24:50 PM PDT 24
Peak memory 200588 kb
Host smart-ce18da9c-0178-4750-a8b6-aef18b965754
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2008355538 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 26.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2008355538
Directory /workspace/26.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/26.pwrmgr_sec_cm_rstmgr_intersig_mubi.590439034
Short name T531
Test name
Test status
Simulation time 53890732 ps
CPU time 0.93 seconds
Started Mar 28 01:24:47 PM PDT 24
Finished Mar 28 01:24:48 PM PDT 24
Peak memory 198544 kb
Host smart-f5f31072-4cf2-4b27-960f-96ae953e4108
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=590439034 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_sec_cm_rstmgr_intersig_
mubi.590439034
Directory /workspace/26.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/26.pwrmgr_smoke.4290703963
Short name T221
Test name
Test status
Simulation time 42647349 ps
CPU time 0.63 seconds
Started Mar 28 01:24:49 PM PDT 24
Finished Mar 28 01:24:50 PM PDT 24
Peak memory 197712 kb
Host smart-04a2ade2-bee4-4c69-8b5f-24afc2db3d4e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4290703963 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_smoke.4290703963
Directory /workspace/26.pwrmgr_smoke/latest

Test location /workspace/coverage/default/26.pwrmgr_stress_all.2419546082
Short name T611
Test name
Test status
Simulation time 2330057833 ps
CPU time 3.85 seconds
Started Mar 28 01:24:49 PM PDT 24
Finished Mar 28 01:24:53 PM PDT 24
Peak memory 200636 kb
Host smart-251b4164-f1e4-4f1a-b90c-9ee0f791c886
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2419546082 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_stress_all.2419546082
Directory /workspace/26.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/26.pwrmgr_stress_all_with_rand_reset.3495594689
Short name T39
Test name
Test status
Simulation time 10297227573 ps
CPU time 34.76 seconds
Started Mar 28 01:24:44 PM PDT 24
Finished Mar 28 01:25:20 PM PDT 24
Peak memory 200680 kb
Host smart-d0b3b3f9-74b3-4559-ab05-05c54580d20f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3495594689 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 26.pwrmgr_stress_all_with_rand_reset.3495594689
Directory /workspace/26.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.pwrmgr_wakeup.2986344364
Short name T315
Test name
Test status
Simulation time 104502430 ps
CPU time 0.9 seconds
Started Mar 28 01:24:51 PM PDT 24
Finished Mar 28 01:24:52 PM PDT 24
Peak memory 198404 kb
Host smart-69dd1c46-ad7a-4b51-a0cc-065bdf076272
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2986344364 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_wakeup.2986344364
Directory /workspace/26.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/26.pwrmgr_wakeup_reset.1340621828
Short name T599
Test name
Test status
Simulation time 134280273 ps
CPU time 0.84 seconds
Started Mar 28 01:24:46 PM PDT 24
Finished Mar 28 01:24:47 PM PDT 24
Peak memory 198692 kb
Host smart-321cf8a2-e3e7-45d5-be0f-8c186014c63d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1340621828 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_wakeup_reset.1340621828
Directory /workspace/26.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/27.pwrmgr_aborted_low_power.3859316273
Short name T601
Test name
Test status
Simulation time 43554487 ps
CPU time 0.96 seconds
Started Mar 28 01:24:45 PM PDT 24
Finished Mar 28 01:24:46 PM PDT 24
Peak memory 199616 kb
Host smart-1453e658-3965-4097-862b-992c545db800
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3859316273 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_aborted_low_power.3859316273
Directory /workspace/27.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/27.pwrmgr_disable_rom_integrity_check.3320764100
Short name T474
Test name
Test status
Simulation time 77074861 ps
CPU time 0.73 seconds
Started Mar 28 01:25:07 PM PDT 24
Finished Mar 28 01:25:08 PM PDT 24
Peak memory 198448 kb
Host smart-eac6c47d-5775-437f-89a6-dce623c49bbc
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3320764100 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_dis
able_rom_integrity_check.3320764100
Directory /workspace/27.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/27.pwrmgr_esc_clk_rst_malfunc.2710908532
Short name T965
Test name
Test status
Simulation time 30650379 ps
CPU time 0.66 seconds
Started Mar 28 01:25:04 PM PDT 24
Finished Mar 28 01:25:05 PM PDT 24
Peak memory 197276 kb
Host smart-8ebcf32e-5c2c-474c-9680-d8f382de811a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2710908532 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_esc_clk_rst
_malfunc.2710908532
Directory /workspace/27.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/27.pwrmgr_escalation_timeout.1067401320
Short name T176
Test name
Test status
Simulation time 210532767 ps
CPU time 1.05 seconds
Started Mar 28 01:25:04 PM PDT 24
Finished Mar 28 01:25:05 PM PDT 24
Peak memory 197468 kb
Host smart-a7a128ba-df80-40b2-8537-1bcb717953c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1067401320 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_escalation_timeout.1067401320
Directory /workspace/27.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/27.pwrmgr_glitch.3012767625
Short name T282
Test name
Test status
Simulation time 129889618 ps
CPU time 0.59 seconds
Started Mar 28 01:25:05 PM PDT 24
Finished Mar 28 01:25:06 PM PDT 24
Peak memory 196772 kb
Host smart-a31a0083-35ad-47dc-9446-17a21342b006
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3012767625 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_glitch.3012767625
Directory /workspace/27.pwrmgr_glitch/latest

Test location /workspace/coverage/default/27.pwrmgr_global_esc.1761974231
Short name T650
Test name
Test status
Simulation time 73049683 ps
CPU time 0.6 seconds
Started Mar 28 01:25:04 PM PDT 24
Finished Mar 28 01:25:05 PM PDT 24
Peak memory 197728 kb
Host smart-97468003-07b6-4923-94fe-0d3b7cf94754
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1761974231 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_global_esc.1761974231
Directory /workspace/27.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/27.pwrmgr_lowpower_invalid.1721771221
Short name T225
Test name
Test status
Simulation time 69912028 ps
CPU time 0.72 seconds
Started Mar 28 01:25:03 PM PDT 24
Finished Mar 28 01:25:04 PM PDT 24
Peak memory 200752 kb
Host smart-7f38765b-f548-4c45-9786-4a3b1addc59b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1721771221 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_lowpower_inval
id.1721771221
Directory /workspace/27.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/27.pwrmgr_lowpower_wakeup_race.2237969053
Short name T709
Test name
Test status
Simulation time 106574034 ps
CPU time 0.91 seconds
Started Mar 28 01:24:47 PM PDT 24
Finished Mar 28 01:24:48 PM PDT 24
Peak memory 198944 kb
Host smart-bd697fef-8751-4eed-9469-de289e479a62
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2237969053 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_lowpower_w
akeup_race.2237969053
Directory /workspace/27.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/27.pwrmgr_reset.3297432001
Short name T686
Test name
Test status
Simulation time 41235974 ps
CPU time 0.82 seconds
Started Mar 28 01:24:48 PM PDT 24
Finished Mar 28 01:24:49 PM PDT 24
Peak memory 198532 kb
Host smart-0e457d23-a5b8-4f16-8614-28bfb98f6dc2
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3297432001 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_reset.3297432001
Directory /workspace/27.pwrmgr_reset/latest

Test location /workspace/coverage/default/27.pwrmgr_reset_invalid.858279562
Short name T646
Test name
Test status
Simulation time 169334745 ps
CPU time 0.82 seconds
Started Mar 28 01:25:03 PM PDT 24
Finished Mar 28 01:25:04 PM PDT 24
Peak memory 208896 kb
Host smart-a1109850-fe0b-41aa-9b48-264aa33c9dd1
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=858279562 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_reset_invalid.858279562
Directory /workspace/27.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/27.pwrmgr_sec_cm_ctrl_config_regwen.3809898115
Short name T633
Test name
Test status
Simulation time 66109294 ps
CPU time 0.68 seconds
Started Mar 28 01:25:05 PM PDT 24
Finished Mar 28 01:25:05 PM PDT 24
Peak memory 198696 kb
Host smart-b6ef3785-cef5-442d-bd1b-3143bfd89f0e
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3809898115 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_sec_
cm_ctrl_config_regwen.3809898115
Directory /workspace/27.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/27.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3751721731
Short name T806
Test name
Test status
Simulation time 1017045748 ps
CPU time 2.17 seconds
Started Mar 28 01:24:48 PM PDT 24
Finished Mar 28 01:24:50 PM PDT 24
Peak memory 200516 kb
Host smart-1fe64489-851d-4544-a3f1-16ea7c0fd4e5
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3751721731 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 27.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3751721731
Directory /workspace/27.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/27.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3005942801
Short name T410
Test name
Test status
Simulation time 891942643 ps
CPU time 3.33 seconds
Started Mar 28 01:24:48 PM PDT 24
Finished Mar 28 01:24:51 PM PDT 24
Peak memory 200556 kb
Host smart-f4536b1d-0cfb-46dc-84ff-b1d5f57cd8b1
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3005942801 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 27.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3005942801
Directory /workspace/27.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/27.pwrmgr_sec_cm_rstmgr_intersig_mubi.410090814
Short name T563
Test name
Test status
Simulation time 67830481 ps
CPU time 0.83 seconds
Started Mar 28 01:25:05 PM PDT 24
Finished Mar 28 01:25:06 PM PDT 24
Peak memory 198540 kb
Host smart-396f3c54-4c8e-465e-a309-c520bad6b8d0
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=410090814 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_sec_cm_rstmgr_intersig_
mubi.410090814
Directory /workspace/27.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/27.pwrmgr_smoke.816879726
Short name T639
Test name
Test status
Simulation time 31662334 ps
CPU time 0.67 seconds
Started Mar 28 01:24:49 PM PDT 24
Finished Mar 28 01:24:49 PM PDT 24
Peak memory 198604 kb
Host smart-060643c2-90e3-47e7-aca3-71d843d04d8a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=816879726 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_smoke.816879726
Directory /workspace/27.pwrmgr_smoke/latest

Test location /workspace/coverage/default/27.pwrmgr_stress_all.3272794236
Short name T511
Test name
Test status
Simulation time 1259844398 ps
CPU time 1.65 seconds
Started Mar 28 01:25:03 PM PDT 24
Finished Mar 28 01:25:05 PM PDT 24
Peak memory 200600 kb
Host smart-b5399e30-c958-4126-ba5e-1f2f6a17df66
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3272794236 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_stress_all.3272794236
Directory /workspace/27.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/27.pwrmgr_stress_all_with_rand_reset.830914056
Short name T269
Test name
Test status
Simulation time 5246335351 ps
CPU time 8.88 seconds
Started Mar 28 01:25:04 PM PDT 24
Finished Mar 28 01:25:13 PM PDT 24
Peak memory 200824 kb
Host smart-0bbe09ff-9332-4e53-b01b-01644a5f399d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=830914056 -assert nopost
proc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 27.pwrmgr_stress_all_with_rand_reset.830914056
Directory /workspace/27.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.pwrmgr_wakeup.2433942563
Short name T889
Test name
Test status
Simulation time 269645422 ps
CPU time 1.3 seconds
Started Mar 28 01:24:49 PM PDT 24
Finished Mar 28 01:24:50 PM PDT 24
Peak memory 199020 kb
Host smart-aa4b8f45-5f39-420c-a2fc-46940a8b9240
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2433942563 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_wakeup.2433942563
Directory /workspace/27.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/27.pwrmgr_wakeup_reset.444099471
Short name T672
Test name
Test status
Simulation time 281307640 ps
CPU time 1.42 seconds
Started Mar 28 01:24:45 PM PDT 24
Finished Mar 28 01:24:46 PM PDT 24
Peak memory 200508 kb
Host smart-efe8f723-1478-46da-b10d-67e6adb40bf5
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=444099471 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_wakeup_reset.444099471
Directory /workspace/27.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/28.pwrmgr_aborted_low_power.482233821
Short name T435
Test name
Test status
Simulation time 20745786 ps
CPU time 0.7 seconds
Started Mar 28 01:25:07 PM PDT 24
Finished Mar 28 01:25:08 PM PDT 24
Peak memory 197892 kb
Host smart-f3c3f66d-ecba-42d2-817a-5d16e9c15584
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=482233821 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_aborted_low_power.482233821
Directory /workspace/28.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/28.pwrmgr_disable_rom_integrity_check.4149614659
Short name T127
Test name
Test status
Simulation time 66016545 ps
CPU time 0.86 seconds
Started Mar 28 01:25:05 PM PDT 24
Finished Mar 28 01:25:06 PM PDT 24
Peak memory 198512 kb
Host smart-756c8083-eaf1-412b-b5ae-5c13895633a6
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4149614659 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_dis
able_rom_integrity_check.4149614659
Directory /workspace/28.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/28.pwrmgr_esc_clk_rst_malfunc.3486131372
Short name T11
Test name
Test status
Simulation time 29773513 ps
CPU time 0.64 seconds
Started Mar 28 01:25:07 PM PDT 24
Finished Mar 28 01:25:08 PM PDT 24
Peak memory 197364 kb
Host smart-9213b371-2b62-4d9a-8e22-941da08115d3
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3486131372 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_esc_clk_rst
_malfunc.3486131372
Directory /workspace/28.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/28.pwrmgr_escalation_timeout.3161292629
Short name T163
Test name
Test status
Simulation time 332394736 ps
CPU time 0.95 seconds
Started Mar 28 01:25:07 PM PDT 24
Finished Mar 28 01:25:08 PM PDT 24
Peak memory 197764 kb
Host smart-0743ccc7-a4b7-49bc-939e-21a6e6cc72a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3161292629 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_escalation_timeout.3161292629
Directory /workspace/28.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/28.pwrmgr_glitch.3484362139
Short name T902
Test name
Test status
Simulation time 99171875 ps
CPU time 0.57 seconds
Started Mar 28 01:25:07 PM PDT 24
Finished Mar 28 01:25:08 PM PDT 24
Peak memory 196576 kb
Host smart-9eada93a-c2e9-4d3d-914a-92c4bbd5f2ed
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3484362139 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_glitch.3484362139
Directory /workspace/28.pwrmgr_glitch/latest

Test location /workspace/coverage/default/28.pwrmgr_global_esc.3185311520
Short name T788
Test name
Test status
Simulation time 53923210 ps
CPU time 0.62 seconds
Started Mar 28 01:25:07 PM PDT 24
Finished Mar 28 01:25:08 PM PDT 24
Peak memory 197380 kb
Host smart-bce8a889-f831-4da2-975c-b77360cf00e0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3185311520 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_global_esc.3185311520
Directory /workspace/28.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/28.pwrmgr_lowpower_invalid.3143472472
Short name T778
Test name
Test status
Simulation time 75592213 ps
CPU time 0.71 seconds
Started Mar 28 01:25:10 PM PDT 24
Finished Mar 28 01:25:11 PM PDT 24
Peak memory 200760 kb
Host smart-a63ad9e0-cb08-4aef-9a8c-54f44d3b7734
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3143472472 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_lowpower_inval
id.3143472472
Directory /workspace/28.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/28.pwrmgr_lowpower_wakeup_race.754180192
Short name T326
Test name
Test status
Simulation time 333305110 ps
CPU time 0.98 seconds
Started Mar 28 01:25:06 PM PDT 24
Finished Mar 28 01:25:07 PM PDT 24
Peak memory 198996 kb
Host smart-a28e9b57-2e00-4431-b8f0-3cc34eb0d762
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=754180192 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeu
p_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_lowpower_wa
keup_race.754180192
Directory /workspace/28.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/28.pwrmgr_reset.1613129899
Short name T590
Test name
Test status
Simulation time 89837256 ps
CPU time 1 seconds
Started Mar 28 01:25:05 PM PDT 24
Finished Mar 28 01:25:06 PM PDT 24
Peak memory 199376 kb
Host smart-63569856-dbe6-44ac-a119-1e03cbe917cc
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1613129899 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_reset.1613129899
Directory /workspace/28.pwrmgr_reset/latest

Test location /workspace/coverage/default/28.pwrmgr_reset_invalid.3612941130
Short name T804
Test name
Test status
Simulation time 113036594 ps
CPU time 0.88 seconds
Started Mar 28 01:25:05 PM PDT 24
Finished Mar 28 01:25:06 PM PDT 24
Peak memory 208884 kb
Host smart-dd5d119f-5a82-420f-8155-f7f880c447c7
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3612941130 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_reset_invalid.3612941130
Directory /workspace/28.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/28.pwrmgr_sec_cm_ctrl_config_regwen.2552689585
Short name T186
Test name
Test status
Simulation time 196969437 ps
CPU time 1.01 seconds
Started Mar 28 01:25:08 PM PDT 24
Finished Mar 28 01:25:09 PM PDT 24
Peak memory 200108 kb
Host smart-4ee1e09a-a92f-439b-bfde-a1c2da4ca841
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2552689585 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_sec_
cm_ctrl_config_regwen.2552689585
Directory /workspace/28.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/28.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.806494769
Short name T473
Test name
Test status
Simulation time 1859573372 ps
CPU time 2.06 seconds
Started Mar 28 01:25:07 PM PDT 24
Finished Mar 28 01:25:09 PM PDT 24
Peak memory 200336 kb
Host smart-77934931-027d-4300-9a79-ea1f1903bb04
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=806494769 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 28.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.806494769
Directory /workspace/28.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/28.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1052350685
Short name T919
Test name
Test status
Simulation time 782367274 ps
CPU time 2.92 seconds
Started Mar 28 01:25:07 PM PDT 24
Finished Mar 28 01:25:10 PM PDT 24
Peak memory 200524 kb
Host smart-c33bc867-e53d-435f-9bbd-a3bf294d134d
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1052350685 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 28.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1052350685
Directory /workspace/28.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/28.pwrmgr_sec_cm_rstmgr_intersig_mubi.4022678479
Short name T317
Test name
Test status
Simulation time 73273792 ps
CPU time 0.98 seconds
Started Mar 28 01:25:07 PM PDT 24
Finished Mar 28 01:25:08 PM PDT 24
Peak memory 198920 kb
Host smart-3ca3d2fc-b898-43a3-9dc3-545914ce08dc
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4022678479 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_sec_cm_rstmgr_intersig
_mubi.4022678479
Directory /workspace/28.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/28.pwrmgr_smoke.1582457766
Short name T545
Test name
Test status
Simulation time 37205131 ps
CPU time 0.69 seconds
Started Mar 28 01:25:06 PM PDT 24
Finished Mar 28 01:25:06 PM PDT 24
Peak memory 198616 kb
Host smart-13973ccc-df96-4bcc-b49e-e9badac10761
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1582457766 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_smoke.1582457766
Directory /workspace/28.pwrmgr_smoke/latest

Test location /workspace/coverage/default/28.pwrmgr_stress_all.2631757986
Short name T322
Test name
Test status
Simulation time 1229322444 ps
CPU time 5.05 seconds
Started Mar 28 01:25:10 PM PDT 24
Finished Mar 28 01:25:15 PM PDT 24
Peak memory 200588 kb
Host smart-fb0884e1-d8ff-4723-90a9-d71291cab210
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2631757986 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_stress_all.2631757986
Directory /workspace/28.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/28.pwrmgr_stress_all_with_rand_reset.2314895794
Short name T122
Test name
Test status
Simulation time 9826569861 ps
CPU time 10.13 seconds
Started Mar 28 01:25:07 PM PDT 24
Finished Mar 28 01:25:17 PM PDT 24
Peak memory 200728 kb
Host smart-9e1e26c0-1541-4a74-8119-9f76e7b9a06a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2314895794 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 28.pwrmgr_stress_all_with_rand_reset.2314895794
Directory /workspace/28.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.pwrmgr_wakeup.977640619
Short name T559
Test name
Test status
Simulation time 71310781 ps
CPU time 0.63 seconds
Started Mar 28 01:25:06 PM PDT 24
Finished Mar 28 01:25:06 PM PDT 24
Peak memory 197508 kb
Host smart-681df007-4047-489c-8dfb-cb91c050bb77
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=977640619 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_wakeup.977640619
Directory /workspace/28.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/28.pwrmgr_wakeup_reset.1569177922
Short name T62
Test name
Test status
Simulation time 305279364 ps
CPU time 0.97 seconds
Started Mar 28 01:25:05 PM PDT 24
Finished Mar 28 01:25:06 PM PDT 24
Peak memory 199432 kb
Host smart-b7c4983c-0ac8-486e-8c08-397437c643bf
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1569177922 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_wakeup_reset.1569177922
Directory /workspace/28.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/29.pwrmgr_aborted_low_power.600321487
Short name T255
Test name
Test status
Simulation time 22186230 ps
CPU time 0.74 seconds
Started Mar 28 01:25:08 PM PDT 24
Finished Mar 28 01:25:09 PM PDT 24
Peak memory 197724 kb
Host smart-17161b02-9d9c-40ee-97b1-86c06b0707e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=600321487 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_aborted_low_power.600321487
Directory /workspace/29.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/29.pwrmgr_disable_rom_integrity_check.2421373929
Short name T126
Test name
Test status
Simulation time 92866110 ps
CPU time 0.73 seconds
Started Mar 28 01:25:08 PM PDT 24
Finished Mar 28 01:25:09 PM PDT 24
Peak memory 198380 kb
Host smart-76f0b232-2fb7-4103-bb51-12a47b1c3267
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2421373929 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_dis
able_rom_integrity_check.2421373929
Directory /workspace/29.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/29.pwrmgr_esc_clk_rst_malfunc.3375844011
Short name T966
Test name
Test status
Simulation time 29781266 ps
CPU time 0.68 seconds
Started Mar 28 01:25:10 PM PDT 24
Finished Mar 28 01:25:11 PM PDT 24
Peak memory 197316 kb
Host smart-ff3e4bb0-8c62-4d7c-974a-b050390bec4f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3375844011 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_esc_clk_rst
_malfunc.3375844011
Directory /workspace/29.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/29.pwrmgr_escalation_timeout.3084250938
Short name T967
Test name
Test status
Simulation time 430582147 ps
CPU time 1.03 seconds
Started Mar 28 01:25:08 PM PDT 24
Finished Mar 28 01:25:09 PM PDT 24
Peak memory 197404 kb
Host smart-21133ecd-8a5c-4915-a1c0-a69300e720f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3084250938 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_escalation_timeout.3084250938
Directory /workspace/29.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/29.pwrmgr_glitch.2608423642
Short name T443
Test name
Test status
Simulation time 58785273 ps
CPU time 0.67 seconds
Started Mar 28 01:25:10 PM PDT 24
Finished Mar 28 01:25:11 PM PDT 24
Peak memory 196700 kb
Host smart-4c557031-94eb-458f-b741-96c9ccc1e936
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2608423642 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_glitch.2608423642
Directory /workspace/29.pwrmgr_glitch/latest

Test location /workspace/coverage/default/29.pwrmgr_global_esc.79233805
Short name T892
Test name
Test status
Simulation time 53663794 ps
CPU time 0.61 seconds
Started Mar 28 01:25:05 PM PDT 24
Finished Mar 28 01:25:06 PM PDT 24
Peak memory 197740 kb
Host smart-0137d029-bec1-47e3-8a69-98c11a378985
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79233805 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_global_esc.79233805
Directory /workspace/29.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/29.pwrmgr_lowpower_invalid.2513256217
Short name T809
Test name
Test status
Simulation time 46585699 ps
CPU time 0.68 seconds
Started Mar 28 01:25:09 PM PDT 24
Finished Mar 28 01:25:10 PM PDT 24
Peak memory 200672 kb
Host smart-d52cfbe9-8a7d-4539-9c37-418bdb539da8
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2513256217 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_lowpower_inval
id.2513256217
Directory /workspace/29.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/29.pwrmgr_lowpower_wakeup_race.3918061068
Short name T71
Test name
Test status
Simulation time 217329302 ps
CPU time 1.21 seconds
Started Mar 28 01:25:10 PM PDT 24
Finished Mar 28 01:25:12 PM PDT 24
Peak memory 199028 kb
Host smart-08984cf2-3d47-4e86-ae21-36f0c7676d0a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3918061068 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_lowpower_w
akeup_race.3918061068
Directory /workspace/29.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/29.pwrmgr_reset.1624197870
Short name T620
Test name
Test status
Simulation time 53494009 ps
CPU time 0.86 seconds
Started Mar 28 01:25:06 PM PDT 24
Finished Mar 28 01:25:07 PM PDT 24
Peak memory 198540 kb
Host smart-e0fae1b3-ec82-4de3-af03-9a587add770b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1624197870 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_reset.1624197870
Directory /workspace/29.pwrmgr_reset/latest

Test location /workspace/coverage/default/29.pwrmgr_reset_invalid.1975341066
Short name T598
Test name
Test status
Simulation time 145552120 ps
CPU time 0.87 seconds
Started Mar 28 01:25:05 PM PDT 24
Finished Mar 28 01:25:06 PM PDT 24
Peak memory 208756 kb
Host smart-911ca7a8-f2de-4a86-86f3-c50c67bb1c1b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1975341066 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_reset_invalid.1975341066
Directory /workspace/29.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/29.pwrmgr_sec_cm_ctrl_config_regwen.1639060628
Short name T497
Test name
Test status
Simulation time 106755207 ps
CPU time 0.84 seconds
Started Mar 28 01:25:10 PM PDT 24
Finished Mar 28 01:25:11 PM PDT 24
Peak memory 198144 kb
Host smart-50af81b3-6ebb-48f7-ad81-1eacb25bec2e
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1639060628 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_sec_
cm_ctrl_config_regwen.1639060628
Directory /workspace/29.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/29.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1367360265
Short name T951
Test name
Test status
Simulation time 1282883264 ps
CPU time 2.33 seconds
Started Mar 28 01:25:08 PM PDT 24
Finished Mar 28 01:25:11 PM PDT 24
Peak memory 200220 kb
Host smart-f29b52d4-9dcf-494c-b902-56e8c36cbaaf
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1367360265 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 29.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1367360265
Directory /workspace/29.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/29.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1612471114
Short name T528
Test name
Test status
Simulation time 1101119398 ps
CPU time 2.23 seconds
Started Mar 28 01:25:08 PM PDT 24
Finished Mar 28 01:25:11 PM PDT 24
Peak memory 200492 kb
Host smart-0fb2ed84-843d-442c-8921-1c120722fc61
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1612471114 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 29.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1612471114
Directory /workspace/29.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/29.pwrmgr_sec_cm_rstmgr_intersig_mubi.1586487679
Short name T158
Test name
Test status
Simulation time 51771593 ps
CPU time 0.93 seconds
Started Mar 28 01:25:09 PM PDT 24
Finished Mar 28 01:25:10 PM PDT 24
Peak memory 198672 kb
Host smart-4b6654dc-5aa9-4715-a7f2-6f60408275c3
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1586487679 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_sec_cm_rstmgr_intersig
_mubi.1586487679
Directory /workspace/29.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/29.pwrmgr_smoke.2335231963
Short name T523
Test name
Test status
Simulation time 34372725 ps
CPU time 0.64 seconds
Started Mar 28 01:25:10 PM PDT 24
Finished Mar 28 01:25:11 PM PDT 24
Peak memory 198608 kb
Host smart-d2dc71da-151f-4c8b-9a8b-e261c5bb6283
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2335231963 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_smoke.2335231963
Directory /workspace/29.pwrmgr_smoke/latest

Test location /workspace/coverage/default/29.pwrmgr_stress_all.958703782
Short name T479
Test name
Test status
Simulation time 1657745572 ps
CPU time 3.76 seconds
Started Mar 28 01:25:05 PM PDT 24
Finished Mar 28 01:25:09 PM PDT 24
Peak memory 200436 kb
Host smart-63f526b0-4c30-4279-b63a-0b6018b8f597
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=958703782 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_stress_all.958703782
Directory /workspace/29.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/29.pwrmgr_stress_all_with_rand_reset.3880906169
Short name T125
Test name
Test status
Simulation time 5554753427 ps
CPU time 7.37 seconds
Started Mar 28 01:25:10 PM PDT 24
Finished Mar 28 01:25:17 PM PDT 24
Peak memory 200748 kb
Host smart-d647ebc1-9923-48b6-9736-2b1ecb5a99d1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3880906169 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 29.pwrmgr_stress_all_with_rand_reset.3880906169
Directory /workspace/29.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.pwrmgr_wakeup.1952200554
Short name T548
Test name
Test status
Simulation time 100059361 ps
CPU time 0.8 seconds
Started Mar 28 01:25:06 PM PDT 24
Finished Mar 28 01:25:07 PM PDT 24
Peak memory 197816 kb
Host smart-e386f130-3904-40d5-ad9c-1ab67e35ff79
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1952200554 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_wakeup.1952200554
Directory /workspace/29.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/29.pwrmgr_wakeup_reset.1296208961
Short name T732
Test name
Test status
Simulation time 366545140 ps
CPU time 1.19 seconds
Started Mar 28 01:25:05 PM PDT 24
Finished Mar 28 01:25:07 PM PDT 24
Peak memory 200364 kb
Host smart-ea43c269-94ea-49d8-99ea-970929b85a07
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1296208961 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_wakeup_reset.1296208961
Directory /workspace/29.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/3.pwrmgr_aborted_low_power.3477232574
Short name T350
Test name
Test status
Simulation time 28933423 ps
CPU time 0.79 seconds
Started Mar 28 01:22:18 PM PDT 24
Finished Mar 28 01:22:20 PM PDT 24
Peak memory 198384 kb
Host smart-9905eed6-dccb-4491-874b-523bd4d4cdb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3477232574 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_aborted_low_power.3477232574
Directory /workspace/3.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/3.pwrmgr_disable_rom_integrity_check.2718795452
Short name T610
Test name
Test status
Simulation time 77264678 ps
CPU time 0.69 seconds
Started Mar 28 01:22:18 PM PDT 24
Finished Mar 28 01:22:19 PM PDT 24
Peak memory 198560 kb
Host smart-c7cdf6c9-cd9b-4058-9d21-8b185f3305f1
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2718795452 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_disa
ble_rom_integrity_check.2718795452
Directory /workspace/3.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/3.pwrmgr_esc_clk_rst_malfunc.2012026331
Short name T354
Test name
Test status
Simulation time 41625418 ps
CPU time 0.59 seconds
Started Mar 28 01:22:17 PM PDT 24
Finished Mar 28 01:22:18 PM PDT 24
Peak memory 197424 kb
Host smart-a85f7fcc-3fdc-4f59-8e24-871493da003d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2012026331 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_esc_clk_rst_
malfunc.2012026331
Directory /workspace/3.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/3.pwrmgr_escalation_timeout.3007383444
Short name T189
Test name
Test status
Simulation time 313699611 ps
CPU time 1.02 seconds
Started Mar 28 01:22:18 PM PDT 24
Finished Mar 28 01:22:19 PM PDT 24
Peak memory 197716 kb
Host smart-6dd93df0-744d-48cf-8591-2eb7655b0ec0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3007383444 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_escalation_timeout.3007383444
Directory /workspace/3.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/3.pwrmgr_glitch.277452111
Short name T15
Test name
Test status
Simulation time 51914711 ps
CPU time 0.66 seconds
Started Mar 28 01:22:17 PM PDT 24
Finished Mar 28 01:22:17 PM PDT 24
Peak memory 197436 kb
Host smart-17b62bd2-a73c-4132-a6e9-92e5786a3c22
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=277452111 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_glitch.277452111
Directory /workspace/3.pwrmgr_glitch/latest

Test location /workspace/coverage/default/3.pwrmgr_global_esc.1107291911
Short name T500
Test name
Test status
Simulation time 42635130 ps
CPU time 0.68 seconds
Started Mar 28 01:22:18 PM PDT 24
Finished Mar 28 01:22:20 PM PDT 24
Peak memory 197424 kb
Host smart-ef3e4e8e-17b0-479b-93b2-1ad7cfecc626
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1107291911 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_global_esc.1107291911
Directory /workspace/3.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/3.pwrmgr_lowpower_invalid.782385850
Short name T622
Test name
Test status
Simulation time 47969959 ps
CPU time 0.66 seconds
Started Mar 28 01:22:17 PM PDT 24
Finished Mar 28 01:22:17 PM PDT 24
Peak memory 200628 kb
Host smart-7778b4a3-3944-4b1e-a603-b55e0c620a6e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=782385850 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inval
id_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_lowpower_invalid
.782385850
Directory /workspace/3.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/3.pwrmgr_lowpower_wakeup_race.4226641243
Short name T877
Test name
Test status
Simulation time 263849687 ps
CPU time 0.81 seconds
Started Mar 28 01:22:17 PM PDT 24
Finished Mar 28 01:22:18 PM PDT 24
Peak memory 197780 kb
Host smart-cab9f243-e7b6-4681-aab1-420aec9545f4
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4226641243 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_lowpower_wa
keup_race.4226641243
Directory /workspace/3.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/3.pwrmgr_reset.912331135
Short name T304
Test name
Test status
Simulation time 117187066 ps
CPU time 0.94 seconds
Started Mar 28 01:22:18 PM PDT 24
Finished Mar 28 01:22:19 PM PDT 24
Peak memory 199368 kb
Host smart-b4692469-6862-4bde-ae36-c53424bb7fdf
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=912331135 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_reset.912331135
Directory /workspace/3.pwrmgr_reset/latest

Test location /workspace/coverage/default/3.pwrmgr_reset_invalid.4078792364
Short name T758
Test name
Test status
Simulation time 245076886 ps
CPU time 0.8 seconds
Started Mar 28 01:22:16 PM PDT 24
Finished Mar 28 01:22:16 PM PDT 24
Peak memory 208808 kb
Host smart-d7e84c78-3d73-40fb-97c4-63170701d9ee
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4078792364 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_reset_invalid.4078792364
Directory /workspace/3.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/3.pwrmgr_sec_cm.3778028228
Short name T23
Test name
Test status
Simulation time 928134380 ps
CPU time 1.56 seconds
Started Mar 28 01:22:17 PM PDT 24
Finished Mar 28 01:22:19 PM PDT 24
Peak memory 218360 kb
Host smart-74d52ffd-7982-4c2e-99e0-61500944f626
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3778028228 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_sec_cm.3778028228
Directory /workspace/3.pwrmgr_sec_cm/latest

Test location /workspace/coverage/default/3.pwrmgr_sec_cm_ctrl_config_regwen.184177381
Short name T565
Test name
Test status
Simulation time 119297073 ps
CPU time 0.71 seconds
Started Mar 28 01:22:18 PM PDT 24
Finished Mar 28 01:22:19 PM PDT 24
Peak memory 198376 kb
Host smart-eb69312b-f206-4d51-ab64-c31a6e2df405
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=184177381 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_c
onfig_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_sec_cm
_ctrl_config_regwen.184177381
Directory /workspace/3.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/3.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2583583784
Short name T605
Test name
Test status
Simulation time 822400401 ps
CPU time 2.28 seconds
Started Mar 28 01:22:16 PM PDT 24
Finished Mar 28 01:22:18 PM PDT 24
Peak memory 200632 kb
Host smart-716930ce-7cfa-41d2-ba0d-de2092ff4ae7
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2583583784 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 3.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2583583784
Directory /workspace/3.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/3.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.587092156
Short name T711
Test name
Test status
Simulation time 805840430 ps
CPU time 3.29 seconds
Started Mar 28 01:22:18 PM PDT 24
Finished Mar 28 01:22:21 PM PDT 24
Peak memory 200268 kb
Host smart-f8273000-8eb7-4c04-abcf-1f1bff14e760
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=587092156 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 3.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.587092156
Directory /workspace/3.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/3.pwrmgr_sec_cm_rstmgr_intersig_mubi.4021497662
Short name T524
Test name
Test status
Simulation time 94534217 ps
CPU time 0.82 seconds
Started Mar 28 01:22:16 PM PDT 24
Finished Mar 28 01:22:17 PM PDT 24
Peak memory 198400 kb
Host smart-c61732f6-2afd-4336-bc08-20a9c0b03cc2
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4021497662 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_sec_cm_rstmgr_intersig_
mubi.4021497662
Directory /workspace/3.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/3.pwrmgr_smoke.875860983
Short name T706
Test name
Test status
Simulation time 62873640 ps
CPU time 0.67 seconds
Started Mar 28 01:22:18 PM PDT 24
Finished Mar 28 01:22:19 PM PDT 24
Peak memory 197656 kb
Host smart-55e16a1f-2735-46aa-a144-310168f5019a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=875860983 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_smoke.875860983
Directory /workspace/3.pwrmgr_smoke/latest

Test location /workspace/coverage/default/3.pwrmgr_stress_all.1736445872
Short name T266
Test name
Test status
Simulation time 1084994236 ps
CPU time 2.76 seconds
Started Mar 28 01:22:16 PM PDT 24
Finished Mar 28 01:22:19 PM PDT 24
Peak memory 200512 kb
Host smart-1f105da9-839f-4429-b5bc-420205b69a81
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1736445872 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_stress_all.1736445872
Directory /workspace/3.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/3.pwrmgr_wakeup.613824468
Short name T901
Test name
Test status
Simulation time 113604940 ps
CPU time 0.91 seconds
Started Mar 28 01:22:18 PM PDT 24
Finished Mar 28 01:22:19 PM PDT 24
Peak memory 198388 kb
Host smart-6c1beaf2-919d-46e0-9054-49f92c063f4f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=613824468 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_wakeup.613824468
Directory /workspace/3.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/3.pwrmgr_wakeup_reset.3067100448
Short name T835
Test name
Test status
Simulation time 146973354 ps
CPU time 0.96 seconds
Started Mar 28 01:22:18 PM PDT 24
Finished Mar 28 01:22:20 PM PDT 24
Peak memory 198580 kb
Host smart-98c774ee-7313-4a3a-be32-0b95d1568cb9
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3067100448 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_wakeup_reset.3067100448
Directory /workspace/3.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/30.pwrmgr_aborted_low_power.583911605
Short name T781
Test name
Test status
Simulation time 31839680 ps
CPU time 0.95 seconds
Started Mar 28 01:25:25 PM PDT 24
Finished Mar 28 01:25:27 PM PDT 24
Peak memory 199624 kb
Host smart-05d14cae-4d49-4df7-95ab-d5dd02ffe0a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=583911605 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_aborted_low_power.583911605
Directory /workspace/30.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/30.pwrmgr_disable_rom_integrity_check.4231372560
Short name T992
Test name
Test status
Simulation time 73526703 ps
CPU time 0.76 seconds
Started Mar 28 01:25:24 PM PDT 24
Finished Mar 28 01:25:25 PM PDT 24
Peak memory 197928 kb
Host smart-aa67289d-05dc-489c-8dff-c1343972e50f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4231372560 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_dis
able_rom_integrity_check.4231372560
Directory /workspace/30.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/30.pwrmgr_esc_clk_rst_malfunc.2290480100
Short name T224
Test name
Test status
Simulation time 47848891 ps
CPU time 0.59 seconds
Started Mar 28 01:25:22 PM PDT 24
Finished Mar 28 01:25:23 PM PDT 24
Peak memory 196652 kb
Host smart-fa9a3dd9-9809-4572-a53e-3808994e734a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2290480100 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_esc_clk_rst
_malfunc.2290480100
Directory /workspace/30.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/30.pwrmgr_escalation_timeout.237316242
Short name T522
Test name
Test status
Simulation time 566528003 ps
CPU time 0.99 seconds
Started Mar 28 01:25:25 PM PDT 24
Finished Mar 28 01:25:27 PM PDT 24
Peak memory 197412 kb
Host smart-f9643333-d2e8-47c1-a757-ab7e18e1ba33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=237316242 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_escalation_timeout.237316242
Directory /workspace/30.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/30.pwrmgr_glitch.2127229848
Short name T766
Test name
Test status
Simulation time 39930628 ps
CPU time 0.59 seconds
Started Mar 28 01:25:25 PM PDT 24
Finished Mar 28 01:25:26 PM PDT 24
Peak memory 197404 kb
Host smart-25da069b-ab60-4876-a2f0-4282a27bcd7c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2127229848 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_glitch.2127229848
Directory /workspace/30.pwrmgr_glitch/latest

Test location /workspace/coverage/default/30.pwrmgr_global_esc.4066674665
Short name T576
Test name
Test status
Simulation time 34937292 ps
CPU time 0.65 seconds
Started Mar 28 01:25:23 PM PDT 24
Finished Mar 28 01:25:24 PM PDT 24
Peak memory 197440 kb
Host smart-146db844-a1e4-4231-a3d9-7bf2a7d7f695
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4066674665 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_global_esc.4066674665
Directory /workspace/30.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/30.pwrmgr_lowpower_invalid.1068745608
Short name T603
Test name
Test status
Simulation time 43176680 ps
CPU time 0.72 seconds
Started Mar 28 01:25:24 PM PDT 24
Finished Mar 28 01:25:25 PM PDT 24
Peak memory 200752 kb
Host smart-e5881a5d-01bd-40eb-baea-e4fd038011a1
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1068745608 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_lowpower_inval
id.1068745608
Directory /workspace/30.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/30.pwrmgr_lowpower_wakeup_race.724705962
Short name T945
Test name
Test status
Simulation time 222147875 ps
CPU time 0.84 seconds
Started Mar 28 01:25:24 PM PDT 24
Finished Mar 28 01:25:25 PM PDT 24
Peak memory 197744 kb
Host smart-6640970b-ffc1-41ef-b0c7-af651fa6972a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=724705962 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeu
p_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_lowpower_wa
keup_race.724705962
Directory /workspace/30.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/30.pwrmgr_reset.683235035
Short name T762
Test name
Test status
Simulation time 62506893 ps
CPU time 0.93 seconds
Started Mar 28 01:25:29 PM PDT 24
Finished Mar 28 01:25:30 PM PDT 24
Peak memory 197904 kb
Host smart-24629a7e-da0b-4d3c-b478-9d743d45ad8b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=683235035 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_reset.683235035
Directory /workspace/30.pwrmgr_reset/latest

Test location /workspace/coverage/default/30.pwrmgr_reset_invalid.1409149566
Short name T624
Test name
Test status
Simulation time 115609717 ps
CPU time 0.88 seconds
Started Mar 28 01:25:25 PM PDT 24
Finished Mar 28 01:25:27 PM PDT 24
Peak memory 208744 kb
Host smart-38162726-2d34-49b3-81d7-a3eddbcf3515
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1409149566 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_reset_invalid.1409149566
Directory /workspace/30.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/30.pwrmgr_sec_cm_ctrl_config_regwen.3902905906
Short name T860
Test name
Test status
Simulation time 152167917 ps
CPU time 0.82 seconds
Started Mar 28 01:25:24 PM PDT 24
Finished Mar 28 01:25:25 PM PDT 24
Peak memory 199024 kb
Host smart-3d400288-8652-4bac-9eb2-164810f5d5bd
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3902905906 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_sec_
cm_ctrl_config_regwen.3902905906
Directory /workspace/30.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/30.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3886999931
Short name T482
Test name
Test status
Simulation time 886663497 ps
CPU time 2.87 seconds
Started Mar 28 01:25:23 PM PDT 24
Finished Mar 28 01:25:27 PM PDT 24
Peak memory 200440 kb
Host smart-581bab58-1381-4713-8fa6-490d9339f222
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3886999931 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 30.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3886999931
Directory /workspace/30.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/30.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.512467620
Short name T335
Test name
Test status
Simulation time 917121260 ps
CPU time 3.42 seconds
Started Mar 28 01:25:23 PM PDT 24
Finished Mar 28 01:25:27 PM PDT 24
Peak memory 200452 kb
Host smart-7fb8ed9c-b915-486b-a9dc-c5ebadc5da53
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=512467620 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 30.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.512467620
Directory /workspace/30.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/30.pwrmgr_sec_cm_rstmgr_intersig_mubi.3465833289
Short name T970
Test name
Test status
Simulation time 85870907 ps
CPU time 0.85 seconds
Started Mar 28 01:25:25 PM PDT 24
Finished Mar 28 01:25:27 PM PDT 24
Peak memory 198660 kb
Host smart-6e447197-877d-4af6-9f9d-af8768dc97d3
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3465833289 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_sec_cm_rstmgr_intersig
_mubi.3465833289
Directory /workspace/30.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/30.pwrmgr_smoke.3985084375
Short name T288
Test name
Test status
Simulation time 32351198 ps
CPU time 0.68 seconds
Started Mar 28 01:25:07 PM PDT 24
Finished Mar 28 01:25:08 PM PDT 24
Peak memory 197864 kb
Host smart-0afca207-1ef3-43b7-b930-1640ecf36bac
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3985084375 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_smoke.3985084375
Directory /workspace/30.pwrmgr_smoke/latest

Test location /workspace/coverage/default/30.pwrmgr_stress_all.1944060219
Short name T908
Test name
Test status
Simulation time 2140339813 ps
CPU time 7.81 seconds
Started Mar 28 01:25:21 PM PDT 24
Finished Mar 28 01:25:29 PM PDT 24
Peak memory 200640 kb
Host smart-e6d40312-64ea-4886-bef6-1362d5bf3627
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1944060219 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_stress_all.1944060219
Directory /workspace/30.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/30.pwrmgr_stress_all_with_rand_reset.3546624244
Short name T568
Test name
Test status
Simulation time 3791158876 ps
CPU time 7.4 seconds
Started Mar 28 01:25:22 PM PDT 24
Finished Mar 28 01:25:29 PM PDT 24
Peak memory 200900 kb
Host smart-8b3e7ba5-8962-44f2-b729-5fa93752fec2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3546624244 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 30.pwrmgr_stress_all_with_rand_reset.3546624244
Directory /workspace/30.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.pwrmgr_wakeup.748138750
Short name T634
Test name
Test status
Simulation time 144127918 ps
CPU time 0.98 seconds
Started Mar 28 01:25:22 PM PDT 24
Finished Mar 28 01:25:23 PM PDT 24
Peak memory 197800 kb
Host smart-7912d6ab-3783-4d98-b974-2d9af90a6e21
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=748138750 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_wakeup.748138750
Directory /workspace/30.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/30.pwrmgr_wakeup_reset.511772088
Short name T303
Test name
Test status
Simulation time 324226192 ps
CPU time 1.33 seconds
Started Mar 28 01:25:22 PM PDT 24
Finished Mar 28 01:25:24 PM PDT 24
Peak memory 200444 kb
Host smart-f3e413a0-1f03-4f56-a20f-d1e07fa285d8
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=511772088 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_wakeup_reset.511772088
Directory /workspace/30.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/31.pwrmgr_aborted_low_power.3752766402
Short name T760
Test name
Test status
Simulation time 28815728 ps
CPU time 0.99 seconds
Started Mar 28 01:25:25 PM PDT 24
Finished Mar 28 01:25:26 PM PDT 24
Peak memory 200220 kb
Host smart-78e066f4-796a-4669-83c8-0d828fd0cf19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3752766402 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_aborted_low_power.3752766402
Directory /workspace/31.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/31.pwrmgr_disable_rom_integrity_check.1136249142
Short name T533
Test name
Test status
Simulation time 65685315 ps
CPU time 0.88 seconds
Started Mar 28 01:25:25 PM PDT 24
Finished Mar 28 01:25:27 PM PDT 24
Peak memory 198476 kb
Host smart-1ab1c0dd-08b9-49fd-b3ff-5d0dbc185ea3
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1136249142 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_dis
able_rom_integrity_check.1136249142
Directory /workspace/31.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/31.pwrmgr_esc_clk_rst_malfunc.1154445512
Short name T883
Test name
Test status
Simulation time 34061006 ps
CPU time 0.63 seconds
Started Mar 28 01:25:24 PM PDT 24
Finished Mar 28 01:25:25 PM PDT 24
Peak memory 197368 kb
Host smart-927d0e21-6597-491a-80ef-91960abf9219
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1154445512 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_esc_clk_rst
_malfunc.1154445512
Directory /workspace/31.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/31.pwrmgr_escalation_timeout.4291816782
Short name T520
Test name
Test status
Simulation time 160131342 ps
CPU time 0.97 seconds
Started Mar 28 01:25:25 PM PDT 24
Finished Mar 28 01:25:27 PM PDT 24
Peak memory 197440 kb
Host smart-f299d214-51f4-4323-8f04-32a9b4131560
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4291816782 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_escalation_timeout.4291816782
Directory /workspace/31.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/31.pwrmgr_glitch.164360865
Short name T200
Test name
Test status
Simulation time 70252818 ps
CPU time 0.62 seconds
Started Mar 28 01:25:32 PM PDT 24
Finished Mar 28 01:25:33 PM PDT 24
Peak memory 197400 kb
Host smart-35711bd4-86db-46cf-a1fc-1fbc4cedff2a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=164360865 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_glitch.164360865
Directory /workspace/31.pwrmgr_glitch/latest

Test location /workspace/coverage/default/31.pwrmgr_global_esc.2306983189
Short name T297
Test name
Test status
Simulation time 31718150 ps
CPU time 0.61 seconds
Started Mar 28 01:25:32 PM PDT 24
Finished Mar 28 01:25:33 PM PDT 24
Peak memory 197424 kb
Host smart-284b0361-dd39-4e09-baf8-c2949da772d5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2306983189 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_global_esc.2306983189
Directory /workspace/31.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/31.pwrmgr_lowpower_invalid.667768275
Short name T336
Test name
Test status
Simulation time 84330555 ps
CPU time 0.7 seconds
Started Mar 28 01:25:31 PM PDT 24
Finished Mar 28 01:25:32 PM PDT 24
Peak memory 200632 kb
Host smart-aee8ee6e-0a6d-403d-a149-6adc0e1ed180
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=667768275 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inval
id_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_lowpower_invali
d.667768275
Directory /workspace/31.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/31.pwrmgr_lowpower_wakeup_race.2462192734
Short name T666
Test name
Test status
Simulation time 269402479 ps
CPU time 0.7 seconds
Started Mar 28 01:25:26 PM PDT 24
Finished Mar 28 01:25:27 PM PDT 24
Peak memory 197608 kb
Host smart-08542d2c-9ce3-489b-823f-70362414c0e1
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2462192734 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_lowpower_w
akeup_race.2462192734
Directory /workspace/31.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/31.pwrmgr_reset.4043538188
Short name T153
Test name
Test status
Simulation time 117296717 ps
CPU time 0.88 seconds
Started Mar 28 01:25:24 PM PDT 24
Finished Mar 28 01:25:25 PM PDT 24
Peak memory 199096 kb
Host smart-06811d7a-d370-4196-a798-8bbecb54f59b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4043538188 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_reset.4043538188
Directory /workspace/31.pwrmgr_reset/latest

Test location /workspace/coverage/default/31.pwrmgr_reset_invalid.577532839
Short name T31
Test name
Test status
Simulation time 120829557 ps
CPU time 0.89 seconds
Started Mar 28 01:25:30 PM PDT 24
Finished Mar 28 01:25:31 PM PDT 24
Peak memory 208836 kb
Host smart-1638a322-ce92-4744-bf4c-a2cc4a5e8377
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=577532839 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_reset_invalid.577532839
Directory /workspace/31.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/31.pwrmgr_sec_cm_ctrl_config_regwen.2259795335
Short name T933
Test name
Test status
Simulation time 259166996 ps
CPU time 1.08 seconds
Started Mar 28 01:25:30 PM PDT 24
Finished Mar 28 01:25:31 PM PDT 24
Peak memory 199496 kb
Host smart-48068902-0bee-4344-8517-e290aaf868b0
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2259795335 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_sec_
cm_ctrl_config_regwen.2259795335
Directory /workspace/31.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/31.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.780937071
Short name T469
Test name
Test status
Simulation time 1424754748 ps
CPU time 1.98 seconds
Started Mar 28 01:25:32 PM PDT 24
Finished Mar 28 01:25:34 PM PDT 24
Peak memory 200504 kb
Host smart-cb4451f6-2059-4b7b-b751-82db0aec81be
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=780937071 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 31.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.780937071
Directory /workspace/31.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/31.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.31293582
Short name T882
Test name
Test status
Simulation time 773957225 ps
CPU time 3.04 seconds
Started Mar 28 01:25:29 PM PDT 24
Finished Mar 28 01:25:32 PM PDT 24
Peak memory 200528 kb
Host smart-99bd5cb9-f598-482b-8975-2cf01d66600f
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31293582 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 31.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.31293582
Directory /workspace/31.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/31.pwrmgr_sec_cm_rstmgr_intersig_mubi.3725466118
Short name T773
Test name
Test status
Simulation time 73894527 ps
CPU time 0.92 seconds
Started Mar 28 01:25:22 PM PDT 24
Finished Mar 28 01:25:23 PM PDT 24
Peak memory 198728 kb
Host smart-4663471d-c84d-41d4-8fd7-9bb88e12fe41
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3725466118 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_sec_cm_rstmgr_intersig
_mubi.3725466118
Directory /workspace/31.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/31.pwrmgr_smoke.388810315
Short name T235
Test name
Test status
Simulation time 175560464 ps
CPU time 0.63 seconds
Started Mar 28 01:25:24 PM PDT 24
Finished Mar 28 01:25:25 PM PDT 24
Peak memory 197736 kb
Host smart-16dfebeb-eb3f-4165-a5c8-ef0cbe4d1f29
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=388810315 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_smoke.388810315
Directory /workspace/31.pwrmgr_smoke/latest

Test location /workspace/coverage/default/31.pwrmgr_stress_all.3295065363
Short name T298
Test name
Test status
Simulation time 1538719707 ps
CPU time 2.54 seconds
Started Mar 28 01:25:33 PM PDT 24
Finished Mar 28 01:25:36 PM PDT 24
Peak memory 200616 kb
Host smart-d025c228-bd86-4762-b62d-1d23293fb08a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3295065363 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_stress_all.3295065363
Directory /workspace/31.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/31.pwrmgr_stress_all_with_rand_reset.3473307129
Short name T19
Test name
Test status
Simulation time 7917111013 ps
CPU time 11.75 seconds
Started Mar 28 01:25:25 PM PDT 24
Finished Mar 28 01:25:37 PM PDT 24
Peak memory 200844 kb
Host smart-ac7754e8-b9f6-4750-a181-b08b70b591f0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3473307129 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 31.pwrmgr_stress_all_with_rand_reset.3473307129
Directory /workspace/31.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.pwrmgr_wakeup.2532989829
Short name T263
Test name
Test status
Simulation time 635504938 ps
CPU time 0.94 seconds
Started Mar 28 01:25:25 PM PDT 24
Finished Mar 28 01:25:27 PM PDT 24
Peak memory 198788 kb
Host smart-037ecc9f-5e02-42a8-ae03-991058a427b9
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2532989829 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_wakeup.2532989829
Directory /workspace/31.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/31.pwrmgr_wakeup_reset.3835498366
Short name T569
Test name
Test status
Simulation time 286895458 ps
CPU time 1 seconds
Started Mar 28 01:25:30 PM PDT 24
Finished Mar 28 01:25:31 PM PDT 24
Peak memory 200432 kb
Host smart-36d38e62-4ec0-42ee-b680-7bf109d23475
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3835498366 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_wakeup_reset.3835498366
Directory /workspace/31.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/32.pwrmgr_aborted_low_power.1009965911
Short name T571
Test name
Test status
Simulation time 109372849 ps
CPU time 0.89 seconds
Started Mar 28 01:25:34 PM PDT 24
Finished Mar 28 01:25:36 PM PDT 24
Peak memory 199368 kb
Host smart-bca973d8-7a19-49a8-9e38-ebc703a37ffd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1009965911 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_aborted_low_power.1009965911
Directory /workspace/32.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/32.pwrmgr_disable_rom_integrity_check.3531547842
Short name T147
Test name
Test status
Simulation time 70837052 ps
CPU time 0.77 seconds
Started Mar 28 01:25:32 PM PDT 24
Finished Mar 28 01:25:33 PM PDT 24
Peak memory 198464 kb
Host smart-02e74b78-14de-4180-8591-1f2e5193ce63
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3531547842 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_dis
able_rom_integrity_check.3531547842
Directory /workspace/32.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/32.pwrmgr_esc_clk_rst_malfunc.2393102652
Short name T164
Test name
Test status
Simulation time 38395446 ps
CPU time 0.6 seconds
Started Mar 28 01:25:33 PM PDT 24
Finished Mar 28 01:25:34 PM PDT 24
Peak memory 197396 kb
Host smart-32af5eee-0312-4c74-8498-bc743b3ffb06
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2393102652 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_esc_clk_rst
_malfunc.2393102652
Directory /workspace/32.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/32.pwrmgr_escalation_timeout.1519537358
Short name T529
Test name
Test status
Simulation time 628239229 ps
CPU time 0.98 seconds
Started Mar 28 01:25:33 PM PDT 24
Finished Mar 28 01:25:35 PM PDT 24
Peak memory 197464 kb
Host smart-90c49b0b-c7b2-488d-83dd-79be129e56ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1519537358 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_escalation_timeout.1519537358
Directory /workspace/32.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/32.pwrmgr_glitch.3107351158
Short name T184
Test name
Test status
Simulation time 33140711 ps
CPU time 0.64 seconds
Started Mar 28 01:25:32 PM PDT 24
Finished Mar 28 01:25:33 PM PDT 24
Peak memory 196704 kb
Host smart-d6f98069-12fc-44a8-a17a-3d6b285c6f1a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3107351158 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_glitch.3107351158
Directory /workspace/32.pwrmgr_glitch/latest

Test location /workspace/coverage/default/32.pwrmgr_global_esc.2064235761
Short name T914
Test name
Test status
Simulation time 58407449 ps
CPU time 0.62 seconds
Started Mar 28 01:25:34 PM PDT 24
Finished Mar 28 01:25:35 PM PDT 24
Peak memory 197448 kb
Host smart-60cea055-0437-4bfb-a746-0d1cf1c17002
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2064235761 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_global_esc.2064235761
Directory /workspace/32.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/32.pwrmgr_lowpower_invalid.4147643013
Short name T941
Test name
Test status
Simulation time 119731111 ps
CPU time 0.69 seconds
Started Mar 28 01:25:33 PM PDT 24
Finished Mar 28 01:25:34 PM PDT 24
Peak memory 200748 kb
Host smart-636750dd-291e-4755-8aa6-51cf31fd178e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4147643013 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_lowpower_inval
id.4147643013
Directory /workspace/32.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/32.pwrmgr_lowpower_wakeup_race.4102514010
Short name T119
Test name
Test status
Simulation time 327725607 ps
CPU time 0.92 seconds
Started Mar 28 01:25:33 PM PDT 24
Finished Mar 28 01:25:34 PM PDT 24
Peak memory 199020 kb
Host smart-d459d567-ba82-4807-b03e-9047415b5c71
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4102514010 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_lowpower_w
akeup_race.4102514010
Directory /workspace/32.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/32.pwrmgr_reset.2038475512
Short name T552
Test name
Test status
Simulation time 51920659 ps
CPU time 0.77 seconds
Started Mar 28 01:25:26 PM PDT 24
Finished Mar 28 01:25:28 PM PDT 24
Peak memory 198544 kb
Host smart-e6c5927e-441e-446d-8383-a72542219734
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2038475512 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_reset.2038475512
Directory /workspace/32.pwrmgr_reset/latest

Test location /workspace/coverage/default/32.pwrmgr_reset_invalid.2304147499
Short name T253
Test name
Test status
Simulation time 163311285 ps
CPU time 0.84 seconds
Started Mar 28 01:25:35 PM PDT 24
Finished Mar 28 01:25:36 PM PDT 24
Peak memory 208740 kb
Host smart-ee7cea12-8640-4ddb-bed4-f5b95e8c3891
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2304147499 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_reset_invalid.2304147499
Directory /workspace/32.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/32.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.110897032
Short name T580
Test name
Test status
Simulation time 917273446 ps
CPU time 2.41 seconds
Started Mar 28 01:25:31 PM PDT 24
Finished Mar 28 01:25:33 PM PDT 24
Peak memory 200444 kb
Host smart-9af61474-3367-452c-a532-8c402b7efad9
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110897032 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 32.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.110897032
Directory /workspace/32.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/32.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1149744855
Short name T618
Test name
Test status
Simulation time 1174275733 ps
CPU time 2.28 seconds
Started Mar 28 01:25:31 PM PDT 24
Finished Mar 28 01:25:33 PM PDT 24
Peak memory 200532 kb
Host smart-bdaf34c7-7759-433f-a036-129b49ed8dc1
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1149744855 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 32.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1149744855
Directory /workspace/32.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/32.pwrmgr_sec_cm_rstmgr_intersig_mubi.2029343645
Short name T329
Test name
Test status
Simulation time 68907269 ps
CPU time 0.82 seconds
Started Mar 28 01:25:31 PM PDT 24
Finished Mar 28 01:25:32 PM PDT 24
Peak memory 198560 kb
Host smart-73d9e387-06a5-4fb2-8e65-6057d6015f20
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2029343645 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_sec_cm_rstmgr_intersig
_mubi.2029343645
Directory /workspace/32.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/32.pwrmgr_smoke.1319713219
Short name T242
Test name
Test status
Simulation time 43217783 ps
CPU time 0.66 seconds
Started Mar 28 01:25:31 PM PDT 24
Finished Mar 28 01:25:32 PM PDT 24
Peak memory 198552 kb
Host smart-4fc309a4-5d85-4c38-8d36-98b703d12529
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1319713219 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_smoke.1319713219
Directory /workspace/32.pwrmgr_smoke/latest

Test location /workspace/coverage/default/32.pwrmgr_stress_all.3960102603
Short name T805
Test name
Test status
Simulation time 5047297440 ps
CPU time 2.33 seconds
Started Mar 28 01:25:35 PM PDT 24
Finished Mar 28 01:25:38 PM PDT 24
Peak memory 200604 kb
Host smart-744a5eb2-2e1f-4704-8f83-66cd37a1681e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3960102603 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_stress_all.3960102603
Directory /workspace/32.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/32.pwrmgr_stress_all_with_rand_reset.416671129
Short name T64
Test name
Test status
Simulation time 9807078363 ps
CPU time 34.4 seconds
Started Mar 28 01:25:32 PM PDT 24
Finished Mar 28 01:26:07 PM PDT 24
Peak memory 200724 kb
Host smart-17223cbe-fd8a-4b80-a874-126d31b49a0a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=416671129 -assert nopost
proc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 32.pwrmgr_stress_all_with_rand_reset.416671129
Directory /workspace/32.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.pwrmgr_wakeup.3887424308
Short name T554
Test name
Test status
Simulation time 63026568 ps
CPU time 0.77 seconds
Started Mar 28 01:25:35 PM PDT 24
Finished Mar 28 01:25:36 PM PDT 24
Peak memory 197584 kb
Host smart-934f24a1-3c95-4095-b30a-8fcc67ddd4da
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3887424308 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_wakeup.3887424308
Directory /workspace/32.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/32.pwrmgr_wakeup_reset.2695537635
Short name T578
Test name
Test status
Simulation time 351161127 ps
CPU time 1.16 seconds
Started Mar 28 01:25:33 PM PDT 24
Finished Mar 28 01:25:34 PM PDT 24
Peak memory 200276 kb
Host smart-e4d7d656-2f33-48a5-9d8b-590c3cb8a5b0
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2695537635 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_wakeup_reset.2695537635
Directory /workspace/32.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/33.pwrmgr_aborted_low_power.805543060
Short name T540
Test name
Test status
Simulation time 108468495 ps
CPU time 0.79 seconds
Started Mar 28 01:25:33 PM PDT 24
Finished Mar 28 01:25:34 PM PDT 24
Peak memory 199268 kb
Host smart-be49f8a9-d3b0-4e36-be67-6e56db853999
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=805543060 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_aborted_low_power.805543060
Directory /workspace/33.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/33.pwrmgr_disable_rom_integrity_check.3779331628
Short name T989
Test name
Test status
Simulation time 55459054 ps
CPU time 0.83 seconds
Started Mar 28 01:25:24 PM PDT 24
Finished Mar 28 01:25:25 PM PDT 24
Peak memory 198524 kb
Host smart-eba5a6f3-ce49-4e1a-a34f-3344aa7fd45c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3779331628 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_dis
able_rom_integrity_check.3779331628
Directory /workspace/33.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/33.pwrmgr_esc_clk_rst_malfunc.2972090194
Short name T659
Test name
Test status
Simulation time 37208017 ps
CPU time 0.6 seconds
Started Mar 28 01:25:34 PM PDT 24
Finished Mar 28 01:25:35 PM PDT 24
Peak memory 197360 kb
Host smart-027c53ad-56fe-435c-a9e3-203efd923d40
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2972090194 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_esc_clk_rst
_malfunc.2972090194
Directory /workspace/33.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/33.pwrmgr_escalation_timeout.1377877308
Short name T162
Test name
Test status
Simulation time 752029514 ps
CPU time 0.95 seconds
Started Mar 28 01:25:31 PM PDT 24
Finished Mar 28 01:25:32 PM PDT 24
Peak memory 197700 kb
Host smart-382e940a-3c19-4c4b-b38c-774cb941080a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1377877308 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_escalation_timeout.1377877308
Directory /workspace/33.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/33.pwrmgr_glitch.1568909001
Short name T879
Test name
Test status
Simulation time 100071670 ps
CPU time 0.63 seconds
Started Mar 28 01:25:28 PM PDT 24
Finished Mar 28 01:25:29 PM PDT 24
Peak memory 196716 kb
Host smart-beaa7280-b8b9-40f0-9c7b-c542ea12e6c0
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1568909001 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_glitch.1568909001
Directory /workspace/33.pwrmgr_glitch/latest

Test location /workspace/coverage/default/33.pwrmgr_global_esc.1764657425
Short name T701
Test name
Test status
Simulation time 228865078 ps
CPU time 0.61 seconds
Started Mar 28 01:25:34 PM PDT 24
Finished Mar 28 01:25:35 PM PDT 24
Peak memory 197428 kb
Host smart-3fd9625b-5a52-40bc-a7a3-0e55c6da41b6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1764657425 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_global_esc.1764657425
Directory /workspace/33.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/33.pwrmgr_lowpower_invalid.1697685765
Short name T818
Test name
Test status
Simulation time 54567183 ps
CPU time 0.69 seconds
Started Mar 28 01:25:30 PM PDT 24
Finished Mar 28 01:25:30 PM PDT 24
Peak memory 200708 kb
Host smart-2e86f228-b0f4-4753-8bf7-681cfead4499
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1697685765 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_lowpower_inval
id.1697685765
Directory /workspace/33.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/33.pwrmgr_lowpower_wakeup_race.99969755
Short name T750
Test name
Test status
Simulation time 57736262 ps
CPU time 0.71 seconds
Started Mar 28 01:25:33 PM PDT 24
Finished Mar 28 01:25:34 PM PDT 24
Peak memory 197852 kb
Host smart-d80c458b-bb38-43f1-9c04-ee2d8a497352
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99969755 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup
_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_lowpower_wak
eup_race.99969755
Directory /workspace/33.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/33.pwrmgr_reset.2803798399
Short name T290
Test name
Test status
Simulation time 53958551 ps
CPU time 0.88 seconds
Started Mar 28 01:25:35 PM PDT 24
Finished Mar 28 01:25:36 PM PDT 24
Peak memory 198568 kb
Host smart-398e53b2-2745-4a87-9207-fcd2b7546dbc
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2803798399 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_reset.2803798399
Directory /workspace/33.pwrmgr_reset/latest

Test location /workspace/coverage/default/33.pwrmgr_reset_invalid.769804048
Short name T642
Test name
Test status
Simulation time 125707374 ps
CPU time 0.92 seconds
Started Mar 28 01:25:24 PM PDT 24
Finished Mar 28 01:25:25 PM PDT 24
Peak memory 208816 kb
Host smart-ff3f29f1-ad7a-4e35-99b9-e4f071e96299
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=769804048 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_reset_invalid.769804048
Directory /workspace/33.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/33.pwrmgr_sec_cm_ctrl_config_regwen.2381028749
Short name T190
Test name
Test status
Simulation time 106964926 ps
CPU time 0.67 seconds
Started Mar 28 01:25:33 PM PDT 24
Finished Mar 28 01:25:35 PM PDT 24
Peak memory 198420 kb
Host smart-faab475a-9f27-4ab1-9e36-83d11587ca41
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2381028749 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_sec_
cm_ctrl_config_regwen.2381028749
Directory /workspace/33.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/33.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3976990088
Short name T230
Test name
Test status
Simulation time 849968847 ps
CPU time 3.11 seconds
Started Mar 28 01:25:37 PM PDT 24
Finished Mar 28 01:25:40 PM PDT 24
Peak memory 200564 kb
Host smart-aafb3210-f3b6-4889-9678-70d2e90a2721
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3976990088 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 33.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3976990088
Directory /workspace/33.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/33.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3939120651
Short name T27
Test name
Test status
Simulation time 1309600368 ps
CPU time 2.25 seconds
Started Mar 28 01:25:37 PM PDT 24
Finished Mar 28 01:25:40 PM PDT 24
Peak memory 200552 kb
Host smart-a03a8c22-453d-475d-9d87-1e683dad0b5f
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3939120651 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 33.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3939120651
Directory /workspace/33.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/33.pwrmgr_sec_cm_rstmgr_intersig_mubi.25040292
Short name T116
Test name
Test status
Simulation time 161035017 ps
CPU time 0.86 seconds
Started Mar 28 01:25:34 PM PDT 24
Finished Mar 28 01:25:35 PM PDT 24
Peak memory 198644 kb
Host smart-d1c8bd68-3d30-44e1-92de-a3f2fa7c6d20
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25040292 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_sec_cm_rstmgr_intersig_m
ubi.25040292
Directory /workspace/33.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/33.pwrmgr_smoke.2077669459
Short name T334
Test name
Test status
Simulation time 30266897 ps
CPU time 0.66 seconds
Started Mar 28 01:25:32 PM PDT 24
Finished Mar 28 01:25:33 PM PDT 24
Peak memory 197696 kb
Host smart-bd3880df-06cc-4df6-8521-d813bd898aa9
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2077669459 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_smoke.2077669459
Directory /workspace/33.pwrmgr_smoke/latest

Test location /workspace/coverage/default/33.pwrmgr_stress_all_with_rand_reset.3457342961
Short name T66
Test name
Test status
Simulation time 4834185925 ps
CPU time 6.7 seconds
Started Mar 28 01:25:25 PM PDT 24
Finished Mar 28 01:25:32 PM PDT 24
Peak memory 200892 kb
Host smart-1780e1ae-ff96-45d7-87bb-e14b92ff2613
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3457342961 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 33.pwrmgr_stress_all_with_rand_reset.3457342961
Directory /workspace/33.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.pwrmgr_wakeup.49875489
Short name T864
Test name
Test status
Simulation time 91343423 ps
CPU time 0.71 seconds
Started Mar 28 01:25:33 PM PDT 24
Finished Mar 28 01:25:34 PM PDT 24
Peak memory 198440 kb
Host smart-ea2eec1e-b4b9-44c1-bcc1-c19cf7b02c0f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49875489 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_wakeup.49875489
Directory /workspace/33.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/34.pwrmgr_aborted_low_power.903640554
Short name T314
Test name
Test status
Simulation time 533854759 ps
CPU time 0.87 seconds
Started Mar 28 01:25:33 PM PDT 24
Finished Mar 28 01:25:34 PM PDT 24
Peak memory 199376 kb
Host smart-67d8f3fc-69d7-4bcc-95aa-98e027ede44f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=903640554 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_aborted_low_power.903640554
Directory /workspace/34.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/34.pwrmgr_disable_rom_integrity_check.1286444727
Short name T20
Test name
Test status
Simulation time 109292352 ps
CPU time 0.7 seconds
Started Mar 28 01:25:33 PM PDT 24
Finished Mar 28 01:25:34 PM PDT 24
Peak memory 198016 kb
Host smart-b0a7d7a6-c2c3-4a5f-9b1f-943fbf8306df
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1286444727 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_dis
able_rom_integrity_check.1286444727
Directory /workspace/34.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/34.pwrmgr_esc_clk_rst_malfunc.3003258139
Short name T391
Test name
Test status
Simulation time 29001749 ps
CPU time 0.64 seconds
Started Mar 28 01:25:24 PM PDT 24
Finished Mar 28 01:25:25 PM PDT 24
Peak memory 197348 kb
Host smart-962c37b0-1303-433d-935e-a55cd0d35a2d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3003258139 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_esc_clk_rst
_malfunc.3003258139
Directory /workspace/34.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/34.pwrmgr_escalation_timeout.2439612295
Short name T980
Test name
Test status
Simulation time 167879755 ps
CPU time 0.96 seconds
Started Mar 28 01:25:26 PM PDT 24
Finished Mar 28 01:25:27 PM PDT 24
Peak memory 197460 kb
Host smart-7508c98f-f4ee-47a4-8890-eddbd57454c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2439612295 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_escalation_timeout.2439612295
Directory /workspace/34.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/34.pwrmgr_glitch.1833536025
Short name T321
Test name
Test status
Simulation time 58149614 ps
CPU time 0.61 seconds
Started Mar 28 01:25:27 PM PDT 24
Finished Mar 28 01:25:28 PM PDT 24
Peak memory 197424 kb
Host smart-2f907197-6cdf-47d8-b6d7-75a7398d34d8
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1833536025 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_glitch.1833536025
Directory /workspace/34.pwrmgr_glitch/latest

Test location /workspace/coverage/default/34.pwrmgr_global_esc.1459138920
Short name T685
Test name
Test status
Simulation time 54545110 ps
CPU time 0.6 seconds
Started Mar 28 01:25:26 PM PDT 24
Finished Mar 28 01:25:27 PM PDT 24
Peak memory 197448 kb
Host smart-7907c435-766b-4ead-902c-89a166cc3341
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1459138920 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_global_esc.1459138920
Directory /workspace/34.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/34.pwrmgr_lowpower_invalid.1832264965
Short name T25
Test name
Test status
Simulation time 208924573 ps
CPU time 0.69 seconds
Started Mar 28 01:25:35 PM PDT 24
Finished Mar 28 01:25:35 PM PDT 24
Peak memory 200760 kb
Host smart-df12b918-c22a-4711-b830-e1b4a2728a67
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1832264965 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_lowpower_inval
id.1832264965
Directory /workspace/34.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/34.pwrmgr_lowpower_wakeup_race.3992720242
Short name T359
Test name
Test status
Simulation time 288881970 ps
CPU time 0.89 seconds
Started Mar 28 01:25:29 PM PDT 24
Finished Mar 28 01:25:30 PM PDT 24
Peak memory 198960 kb
Host smart-a25a1d80-8289-46e7-a752-2a36a54db020
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3992720242 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_lowpower_w
akeup_race.3992720242
Directory /workspace/34.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/34.pwrmgr_reset.4277699149
Short name T653
Test name
Test status
Simulation time 132012672 ps
CPU time 0.79 seconds
Started Mar 28 01:25:30 PM PDT 24
Finished Mar 28 01:25:31 PM PDT 24
Peak memory 198516 kb
Host smart-de0318fe-3a60-4b6a-a4c3-1ac684d71517
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4277699149 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_reset.4277699149
Directory /workspace/34.pwrmgr_reset/latest

Test location /workspace/coverage/default/34.pwrmgr_reset_invalid.1522871751
Short name T171
Test name
Test status
Simulation time 160853840 ps
CPU time 0.81 seconds
Started Mar 28 01:25:33 PM PDT 24
Finished Mar 28 01:25:34 PM PDT 24
Peak memory 208664 kb
Host smart-5fca2a90-8108-45bd-9a1f-ac411292be35
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1522871751 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_reset_invalid.1522871751
Directory /workspace/34.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/34.pwrmgr_sec_cm_ctrl_config_regwen.3536795549
Short name T910
Test name
Test status
Simulation time 221374246 ps
CPU time 0.9 seconds
Started Mar 28 01:25:32 PM PDT 24
Finished Mar 28 01:25:33 PM PDT 24
Peak memory 199384 kb
Host smart-ee66a4c0-a9c2-4321-8088-d81283875826
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3536795549 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_sec_
cm_ctrl_config_regwen.3536795549
Directory /workspace/34.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/34.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2839221258
Short name T363
Test name
Test status
Simulation time 822048676 ps
CPU time 2.82 seconds
Started Mar 28 01:25:25 PM PDT 24
Finished Mar 28 01:25:28 PM PDT 24
Peak memory 200520 kb
Host smart-0655deb6-163b-4488-8c16-450cce2937a0
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2839221258 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 34.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2839221258
Directory /workspace/34.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/34.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3007818621
Short name T842
Test name
Test status
Simulation time 794035234 ps
CPU time 3.03 seconds
Started Mar 28 01:25:25 PM PDT 24
Finished Mar 28 01:25:28 PM PDT 24
Peak memory 200636 kb
Host smart-3a40de2b-9c48-4b21-85f6-9681ba4ccc4c
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3007818621 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 34.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3007818621
Directory /workspace/34.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/34.pwrmgr_sec_cm_rstmgr_intersig_mubi.3498387700
Short name T239
Test name
Test status
Simulation time 76398271 ps
CPU time 1.01 seconds
Started Mar 28 01:25:24 PM PDT 24
Finished Mar 28 01:25:25 PM PDT 24
Peak memory 198960 kb
Host smart-48e69e18-c8ff-4966-bbbc-5c028343826e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3498387700 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_sec_cm_rstmgr_intersig
_mubi.3498387700
Directory /workspace/34.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/34.pwrmgr_smoke.2875582474
Short name T222
Test name
Test status
Simulation time 74626386 ps
CPU time 0.65 seconds
Started Mar 28 01:25:29 PM PDT 24
Finished Mar 28 01:25:30 PM PDT 24
Peak memory 197804 kb
Host smart-899e7c7d-00c0-4b0a-90cd-ffc83b1994e8
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2875582474 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_smoke.2875582474
Directory /workspace/34.pwrmgr_smoke/latest

Test location /workspace/coverage/default/34.pwrmgr_stress_all.4265509659
Short name T921
Test name
Test status
Simulation time 448770021 ps
CPU time 1.11 seconds
Started Mar 28 01:25:35 PM PDT 24
Finished Mar 28 01:25:36 PM PDT 24
Peak memory 200136 kb
Host smart-2f6b2d9f-9db9-4e44-94cb-e1d3b4419446
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4265509659 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_stress_all.4265509659
Directory /workspace/34.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/34.pwrmgr_stress_all_with_rand_reset.4262936659
Short name T441
Test name
Test status
Simulation time 9565718729 ps
CPU time 15.65 seconds
Started Mar 28 01:25:32 PM PDT 24
Finished Mar 28 01:25:49 PM PDT 24
Peak memory 200816 kb
Host smart-9ad34acb-a994-4e67-9d31-941e8440efb4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4262936659 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 34.pwrmgr_stress_all_with_rand_reset.4262936659
Directory /workspace/34.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.pwrmgr_wakeup.3573626152
Short name T185
Test name
Test status
Simulation time 250751688 ps
CPU time 0.93 seconds
Started Mar 28 01:25:30 PM PDT 24
Finished Mar 28 01:25:31 PM PDT 24
Peak memory 198964 kb
Host smart-9ebf4517-2959-4c82-965b-b704ae1251ca
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3573626152 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_wakeup.3573626152
Directory /workspace/34.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/34.pwrmgr_wakeup_reset.1467663014
Short name T218
Test name
Test status
Simulation time 366489476 ps
CPU time 0.95 seconds
Started Mar 28 01:25:31 PM PDT 24
Finished Mar 28 01:25:32 PM PDT 24
Peak memory 199332 kb
Host smart-8199d587-22af-4320-a25b-e9f12eec9790
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1467663014 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_wakeup_reset.1467663014
Directory /workspace/34.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/35.pwrmgr_aborted_low_power.3098559588
Short name T395
Test name
Test status
Simulation time 125339892 ps
CPU time 0.86 seconds
Started Mar 28 01:25:33 PM PDT 24
Finished Mar 28 01:25:35 PM PDT 24
Peak memory 199408 kb
Host smart-6ec097d0-a918-4af4-b738-806e14bb2092
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3098559588 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_aborted_low_power.3098559588
Directory /workspace/35.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/35.pwrmgr_disable_rom_integrity_check.798690458
Short name T313
Test name
Test status
Simulation time 60160991 ps
CPU time 0.82 seconds
Started Mar 28 01:25:35 PM PDT 24
Finished Mar 28 01:25:36 PM PDT 24
Peak memory 198372 kb
Host smart-e75cfab6-d28c-4a8d-987c-ef8f8fd4f05e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=798690458 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_in
tegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_disa
ble_rom_integrity_check.798690458
Directory /workspace/35.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/35.pwrmgr_esc_clk_rst_malfunc.690176353
Short name T403
Test name
Test status
Simulation time 58400861 ps
CPU time 0.58 seconds
Started Mar 28 01:25:32 PM PDT 24
Finished Mar 28 01:25:33 PM PDT 24
Peak memory 197368 kb
Host smart-d45f3d8c-ef0d-49b3-98f1-72617710d88a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=690176353 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_ma
lfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_esc_clk_rst_
malfunc.690176353
Directory /workspace/35.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/35.pwrmgr_escalation_timeout.3177428908
Short name T841
Test name
Test status
Simulation time 214565712 ps
CPU time 1.01 seconds
Started Mar 28 01:25:35 PM PDT 24
Finished Mar 28 01:25:36 PM PDT 24
Peak memory 197292 kb
Host smart-597ca468-c7d2-4407-96d8-17ecf13e7053
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3177428908 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_escalation_timeout.3177428908
Directory /workspace/35.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/35.pwrmgr_glitch.1654191022
Short name T426
Test name
Test status
Simulation time 88600587 ps
CPU time 0.61 seconds
Started Mar 28 01:25:32 PM PDT 24
Finished Mar 28 01:25:33 PM PDT 24
Peak memory 197392 kb
Host smart-1b358f04-f7a9-4681-a830-d7df0449151c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1654191022 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_glitch.1654191022
Directory /workspace/35.pwrmgr_glitch/latest

Test location /workspace/coverage/default/35.pwrmgr_global_esc.3853401143
Short name T949
Test name
Test status
Simulation time 89888718 ps
CPU time 0.63 seconds
Started Mar 28 01:25:30 PM PDT 24
Finished Mar 28 01:25:30 PM PDT 24
Peak memory 197476 kb
Host smart-9869c8c5-a804-4802-8177-6a5bb0eff1c3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3853401143 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_global_esc.3853401143
Directory /workspace/35.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/35.pwrmgr_lowpower_invalid.4191725080
Short name T486
Test name
Test status
Simulation time 43410650 ps
CPU time 0.74 seconds
Started Mar 28 01:25:55 PM PDT 24
Finished Mar 28 01:25:57 PM PDT 24
Peak memory 200784 kb
Host smart-f7a16050-b0c9-4aba-b887-1917d4c07ab7
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4191725080 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_lowpower_inval
id.4191725080
Directory /workspace/35.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/35.pwrmgr_lowpower_wakeup_race.2355386387
Short name T964
Test name
Test status
Simulation time 188771563 ps
CPU time 1.14 seconds
Started Mar 28 01:25:33 PM PDT 24
Finished Mar 28 01:25:34 PM PDT 24
Peak memory 197888 kb
Host smart-ae3d3203-471d-4bb0-bed4-4992427f685b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2355386387 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_lowpower_w
akeup_race.2355386387
Directory /workspace/35.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/35.pwrmgr_reset.1782884184
Short name T890
Test name
Test status
Simulation time 148263884 ps
CPU time 0.85 seconds
Started Mar 28 01:25:34 PM PDT 24
Finished Mar 28 01:25:35 PM PDT 24
Peak memory 199272 kb
Host smart-cc573b3b-fd15-4c15-a938-d91a785309ac
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1782884184 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_reset.1782884184
Directory /workspace/35.pwrmgr_reset/latest

Test location /workspace/coverage/default/35.pwrmgr_reset_invalid.1269429005
Short name T209
Test name
Test status
Simulation time 113724985 ps
CPU time 1.1 seconds
Started Mar 28 01:25:33 PM PDT 24
Finished Mar 28 01:25:35 PM PDT 24
Peak memory 208808 kb
Host smart-96f8005c-46c0-4a75-9d2c-dcdeff0279e6
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1269429005 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_reset_invalid.1269429005
Directory /workspace/35.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/35.pwrmgr_sec_cm_ctrl_config_regwen.2218090439
Short name T275
Test name
Test status
Simulation time 294501785 ps
CPU time 1.23 seconds
Started Mar 28 01:25:32 PM PDT 24
Finished Mar 28 01:25:34 PM PDT 24
Peak memory 200212 kb
Host smart-087ea0d5-c887-4905-abe1-4544d277998b
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2218090439 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_sec_
cm_ctrl_config_regwen.2218090439
Directory /workspace/35.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/35.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.996315800
Short name T515
Test name
Test status
Simulation time 1341881560 ps
CPU time 2.17 seconds
Started Mar 28 01:25:29 PM PDT 24
Finished Mar 28 01:25:31 PM PDT 24
Peak memory 200420 kb
Host smart-bb253227-86a9-495c-881f-ed3703ed1c0a
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=996315800 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 35.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.996315800
Directory /workspace/35.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/35.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3228062714
Short name T394
Test name
Test status
Simulation time 1216450052 ps
CPU time 2.02 seconds
Started Mar 28 01:25:32 PM PDT 24
Finished Mar 28 01:25:34 PM PDT 24
Peak memory 200576 kb
Host smart-96a6dc96-1f8c-4fbb-8591-660bb30612ad
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3228062714 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 35.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3228062714
Directory /workspace/35.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/35.pwrmgr_sec_cm_rstmgr_intersig_mubi.4259045824
Short name T801
Test name
Test status
Simulation time 526892020 ps
CPU time 0.87 seconds
Started Mar 28 01:25:33 PM PDT 24
Finished Mar 28 01:25:35 PM PDT 24
Peak memory 198428 kb
Host smart-1c391c68-a34e-468f-948d-edc5cc02f618
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4259045824 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_sec_cm_rstmgr_intersig
_mubi.4259045824
Directory /workspace/35.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/35.pwrmgr_smoke.2831559095
Short name T268
Test name
Test status
Simulation time 40095753 ps
CPU time 0.68 seconds
Started Mar 28 01:25:29 PM PDT 24
Finished Mar 28 01:25:30 PM PDT 24
Peak memory 197792 kb
Host smart-0bad08ed-0391-4dae-9fbe-8f02b1c80f96
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2831559095 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_smoke.2831559095
Directory /workspace/35.pwrmgr_smoke/latest

Test location /workspace/coverage/default/35.pwrmgr_stress_all.556353309
Short name T677
Test name
Test status
Simulation time 1182281586 ps
CPU time 4.62 seconds
Started Mar 28 01:25:51 PM PDT 24
Finished Mar 28 01:25:56 PM PDT 24
Peak memory 200548 kb
Host smart-1edb926b-9eb5-4993-a81e-28a837079b24
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=556353309 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_stress_all.556353309
Directory /workspace/35.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/35.pwrmgr_wakeup.890366720
Short name T160
Test name
Test status
Simulation time 176052283 ps
CPU time 1.1 seconds
Started Mar 28 01:25:35 PM PDT 24
Finished Mar 28 01:25:36 PM PDT 24
Peak memory 198792 kb
Host smart-0fae4e9e-7c70-4347-abbd-312d529ec66c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=890366720 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_wakeup.890366720
Directory /workspace/35.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/35.pwrmgr_wakeup_reset.1352222506
Short name T327
Test name
Test status
Simulation time 203401150 ps
CPU time 1.1 seconds
Started Mar 28 01:25:29 PM PDT 24
Finished Mar 28 01:25:30 PM PDT 24
Peak memory 199280 kb
Host smart-0ec67dad-c0a8-49ed-a449-1673f9e472be
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1352222506 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_wakeup_reset.1352222506
Directory /workspace/35.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/36.pwrmgr_aborted_low_power.1960618569
Short name T607
Test name
Test status
Simulation time 38537834 ps
CPU time 0.88 seconds
Started Mar 28 01:25:52 PM PDT 24
Finished Mar 28 01:25:54 PM PDT 24
Peak memory 199524 kb
Host smart-40aba5de-255e-4a75-aa69-1f2fb84c7f98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1960618569 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_aborted_low_power.1960618569
Directory /workspace/36.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/36.pwrmgr_disable_rom_integrity_check.2453179859
Short name T787
Test name
Test status
Simulation time 78072521 ps
CPU time 0.76 seconds
Started Mar 28 01:25:53 PM PDT 24
Finished Mar 28 01:25:54 PM PDT 24
Peak memory 198548 kb
Host smart-6f529e61-84b7-400f-a7ef-ba59b9841456
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2453179859 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_dis
able_rom_integrity_check.2453179859
Directory /workspace/36.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/36.pwrmgr_esc_clk_rst_malfunc.3219304868
Short name T530
Test name
Test status
Simulation time 32160484 ps
CPU time 0.65 seconds
Started Mar 28 01:25:53 PM PDT 24
Finished Mar 28 01:25:55 PM PDT 24
Peak memory 196572 kb
Host smart-fa1f6bda-fe75-4784-87d5-02f44e1e8591
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3219304868 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_esc_clk_rst
_malfunc.3219304868
Directory /workspace/36.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/36.pwrmgr_escalation_timeout.3682814086
Short name T670
Test name
Test status
Simulation time 159740888 ps
CPU time 0.99 seconds
Started Mar 28 01:25:52 PM PDT 24
Finished Mar 28 01:25:54 PM PDT 24
Peak memory 197572 kb
Host smart-f18ef4e4-cfe6-4170-9bbc-f0d273d43a48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3682814086 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_escalation_timeout.3682814086
Directory /workspace/36.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/36.pwrmgr_glitch.3891984757
Short name T371
Test name
Test status
Simulation time 51283490 ps
CPU time 0.71 seconds
Started Mar 28 01:25:55 PM PDT 24
Finished Mar 28 01:25:57 PM PDT 24
Peak memory 197376 kb
Host smart-4966244e-9787-41bd-8fb4-f91d63744f2f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3891984757 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_glitch.3891984757
Directory /workspace/36.pwrmgr_glitch/latest

Test location /workspace/coverage/default/36.pwrmgr_global_esc.2728144933
Short name T257
Test name
Test status
Simulation time 73694431 ps
CPU time 0.59 seconds
Started Mar 28 01:25:52 PM PDT 24
Finished Mar 28 01:25:54 PM PDT 24
Peak memory 197772 kb
Host smart-8eb6390f-7de7-4235-825d-b75fb7be49ee
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2728144933 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_global_esc.2728144933
Directory /workspace/36.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/36.pwrmgr_lowpower_invalid.724396042
Short name T465
Test name
Test status
Simulation time 41132842 ps
CPU time 0.71 seconds
Started Mar 28 01:25:51 PM PDT 24
Finished Mar 28 01:25:52 PM PDT 24
Peak memory 200680 kb
Host smart-785d2f3b-6f62-4e5b-a05e-31e820cbf3eb
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=724396042 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inval
id_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_lowpower_invali
d.724396042
Directory /workspace/36.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/36.pwrmgr_lowpower_wakeup_race.787559112
Short name T535
Test name
Test status
Simulation time 206448995 ps
CPU time 1.17 seconds
Started Mar 28 01:25:55 PM PDT 24
Finished Mar 28 01:25:57 PM PDT 24
Peak memory 199008 kb
Host smart-e5d7b601-3a6b-41da-8a26-a5e3be7c03ee
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=787559112 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeu
p_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_lowpower_wa
keup_race.787559112
Directory /workspace/36.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/36.pwrmgr_reset.1817886606
Short name T825
Test name
Test status
Simulation time 90604458 ps
CPU time 0.78 seconds
Started Mar 28 01:25:53 PM PDT 24
Finished Mar 28 01:25:54 PM PDT 24
Peak memory 198436 kb
Host smart-12c6c5c5-e5fb-408e-9987-c9f94128bb6b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1817886606 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_reset.1817886606
Directory /workspace/36.pwrmgr_reset/latest

Test location /workspace/coverage/default/36.pwrmgr_reset_invalid.1357543791
Short name T631
Test name
Test status
Simulation time 101235318 ps
CPU time 1.06 seconds
Started Mar 28 01:25:56 PM PDT 24
Finished Mar 28 01:25:57 PM PDT 24
Peak memory 208776 kb
Host smart-80f531bc-f667-4948-aeed-52f8b91cffd6
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1357543791 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_reset_invalid.1357543791
Directory /workspace/36.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/36.pwrmgr_sec_cm_ctrl_config_regwen.2860152284
Short name T774
Test name
Test status
Simulation time 210972851 ps
CPU time 0.94 seconds
Started Mar 28 01:25:53 PM PDT 24
Finished Mar 28 01:25:55 PM PDT 24
Peak memory 199256 kb
Host smart-7ade30b5-f8e6-4faf-8353-17c65820820d
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2860152284 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_sec_
cm_ctrl_config_regwen.2860152284
Directory /workspace/36.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/36.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2679586253
Short name T331
Test name
Test status
Simulation time 752896289 ps
CPU time 2.75 seconds
Started Mar 28 01:25:56 PM PDT 24
Finished Mar 28 01:25:59 PM PDT 24
Peak memory 200372 kb
Host smart-1c66c6ef-2d8b-46ca-a69c-2e062c667c0a
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2679586253 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 36.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2679586253
Directory /workspace/36.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/36.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1675482571
Short name T617
Test name
Test status
Simulation time 1447668966 ps
CPU time 1.98 seconds
Started Mar 28 01:25:55 PM PDT 24
Finished Mar 28 01:25:58 PM PDT 24
Peak memory 200516 kb
Host smart-8594df14-e267-4f74-9509-40cea50f863b
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1675482571 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 36.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1675482571
Directory /workspace/36.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/36.pwrmgr_sec_cm_rstmgr_intersig_mubi.855239959
Short name T791
Test name
Test status
Simulation time 85317407 ps
CPU time 0.86 seconds
Started Mar 28 01:25:52 PM PDT 24
Finished Mar 28 01:25:54 PM PDT 24
Peak memory 198644 kb
Host smart-ffa42753-bbea-4366-a38b-4d050daf8b71
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=855239959 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_sec_cm_rstmgr_intersig_
mubi.855239959
Directory /workspace/36.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/36.pwrmgr_smoke.2007843543
Short name T302
Test name
Test status
Simulation time 66027941 ps
CPU time 0.66 seconds
Started Mar 28 01:25:53 PM PDT 24
Finished Mar 28 01:25:55 PM PDT 24
Peak memory 197784 kb
Host smart-9d9c7335-34de-45b5-8f8e-1f2fc97db314
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2007843543 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_smoke.2007843543
Directory /workspace/36.pwrmgr_smoke/latest

Test location /workspace/coverage/default/36.pwrmgr_stress_all.1179216556
Short name T83
Test name
Test status
Simulation time 2338205203 ps
CPU time 5.92 seconds
Started Mar 28 01:25:56 PM PDT 24
Finished Mar 28 01:26:02 PM PDT 24
Peak memory 200692 kb
Host smart-1b562e6e-e554-4871-832c-1d9add57db94
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1179216556 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_stress_all.1179216556
Directory /workspace/36.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/36.pwrmgr_stress_all_with_rand_reset.545262057
Short name T772
Test name
Test status
Simulation time 4765946639 ps
CPU time 10.28 seconds
Started Mar 28 01:25:53 PM PDT 24
Finished Mar 28 01:26:04 PM PDT 24
Peak memory 200912 kb
Host smart-8e7b0674-5445-44a5-a3ed-44f48f66cbf6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=545262057 -assert nopost
proc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 36.pwrmgr_stress_all_with_rand_reset.545262057
Directory /workspace/36.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.pwrmgr_wakeup.2951467141
Short name T402
Test name
Test status
Simulation time 226477935 ps
CPU time 0.87 seconds
Started Mar 28 01:25:51 PM PDT 24
Finished Mar 28 01:25:54 PM PDT 24
Peak memory 197920 kb
Host smart-a315e8d5-f25e-4929-9138-42fd38658dbf
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2951467141 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_wakeup.2951467141
Directory /workspace/36.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/36.pwrmgr_wakeup_reset.688142943
Short name T276
Test name
Test status
Simulation time 367956475 ps
CPU time 1.35 seconds
Started Mar 28 01:25:51 PM PDT 24
Finished Mar 28 01:25:54 PM PDT 24
Peak memory 200512 kb
Host smart-fd31ef7f-2fda-4271-a4d2-8c0f027965a7
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=688142943 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_wakeup_reset.688142943
Directory /workspace/36.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/37.pwrmgr_aborted_low_power.686223768
Short name T107
Test name
Test status
Simulation time 46957049 ps
CPU time 0.96 seconds
Started Mar 28 01:25:54 PM PDT 24
Finished Mar 28 01:25:55 PM PDT 24
Peak memory 199404 kb
Host smart-01489bd8-ebba-4d08-b962-c62858614aab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=686223768 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_aborted_low_power.686223768
Directory /workspace/37.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/37.pwrmgr_disable_rom_integrity_check.2171725726
Short name T971
Test name
Test status
Simulation time 85143817 ps
CPU time 0.74 seconds
Started Mar 28 01:25:51 PM PDT 24
Finished Mar 28 01:25:53 PM PDT 24
Peak memory 197764 kb
Host smart-258a2445-058d-4ee0-bf6f-b96db46d6a67
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2171725726 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_dis
able_rom_integrity_check.2171725726
Directory /workspace/37.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/37.pwrmgr_esc_clk_rst_malfunc.483122633
Short name T347
Test name
Test status
Simulation time 33196190 ps
CPU time 0.65 seconds
Started Mar 28 01:25:52 PM PDT 24
Finished Mar 28 01:25:54 PM PDT 24
Peak memory 197244 kb
Host smart-fda91884-9101-455c-9761-9105ec7a4fdc
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=483122633 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_ma
lfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_esc_clk_rst_
malfunc.483122633
Directory /workspace/37.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/37.pwrmgr_escalation_timeout.1001609782
Short name T400
Test name
Test status
Simulation time 161573739 ps
CPU time 0.98 seconds
Started Mar 28 01:25:50 PM PDT 24
Finished Mar 28 01:25:51 PM PDT 24
Peak memory 197288 kb
Host smart-5a7d4c60-3591-4b3c-a73e-458a00114328
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1001609782 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_escalation_timeout.1001609782
Directory /workspace/37.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/37.pwrmgr_glitch.1771129597
Short name T472
Test name
Test status
Simulation time 69713004 ps
CPU time 0.62 seconds
Started Mar 28 01:25:54 PM PDT 24
Finished Mar 28 01:25:55 PM PDT 24
Peak memory 197372 kb
Host smart-9b98a3c5-e3f1-4d99-90fe-903eaa0a5f6a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1771129597 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_glitch.1771129597
Directory /workspace/37.pwrmgr_glitch/latest

Test location /workspace/coverage/default/37.pwrmgr_global_esc.560451803
Short name T740
Test name
Test status
Simulation time 51689977 ps
CPU time 0.63 seconds
Started Mar 28 01:25:53 PM PDT 24
Finished Mar 28 01:25:55 PM PDT 24
Peak memory 197376 kb
Host smart-1f6deac3-d131-4de0-a931-cf2b367d3803
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=560451803 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_global_esc.560451803
Directory /workspace/37.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/37.pwrmgr_lowpower_invalid.473838387
Short name T658
Test name
Test status
Simulation time 76259782 ps
CPU time 0.74 seconds
Started Mar 28 01:25:52 PM PDT 24
Finished Mar 28 01:25:54 PM PDT 24
Peak memory 200740 kb
Host smart-4ce9929f-6dc1-41da-9764-0ab355650dca
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=473838387 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inval
id_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_lowpower_invali
d.473838387
Directory /workspace/37.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/37.pwrmgr_lowpower_wakeup_race.2057538562
Short name T195
Test name
Test status
Simulation time 220837878 ps
CPU time 0.79 seconds
Started Mar 28 01:25:53 PM PDT 24
Finished Mar 28 01:25:54 PM PDT 24
Peak memory 197668 kb
Host smart-1473a7a1-9a86-42cc-82fe-0bcd01e7d444
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2057538562 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_lowpower_w
akeup_race.2057538562
Directory /workspace/37.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/37.pwrmgr_reset.3493978510
Short name T215
Test name
Test status
Simulation time 186571271 ps
CPU time 0.75 seconds
Started Mar 28 01:25:51 PM PDT 24
Finished Mar 28 01:25:52 PM PDT 24
Peak memory 198020 kb
Host smart-8acc6d26-266f-4a4c-9960-cf97f75b5c7d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3493978510 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_reset.3493978510
Directory /workspace/37.pwrmgr_reset/latest

Test location /workspace/coverage/default/37.pwrmgr_reset_invalid.1537759002
Short name T587
Test name
Test status
Simulation time 100123032 ps
CPU time 1.02 seconds
Started Mar 28 01:25:53 PM PDT 24
Finished Mar 28 01:25:54 PM PDT 24
Peak memory 208900 kb
Host smart-738c461d-d4bb-4cc6-9707-dbcc3a36b548
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1537759002 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_reset_invalid.1537759002
Directory /workspace/37.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/37.pwrmgr_sec_cm_ctrl_config_regwen.1344274638
Short name T433
Test name
Test status
Simulation time 358455045 ps
CPU time 0.99 seconds
Started Mar 28 01:25:56 PM PDT 24
Finished Mar 28 01:25:57 PM PDT 24
Peak memory 199508 kb
Host smart-7c08d45a-b7dd-4b9e-b014-2ad322bc7e1a
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1344274638 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_sec_
cm_ctrl_config_regwen.1344274638
Directory /workspace/37.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/37.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1964517892
Short name T439
Test name
Test status
Simulation time 823182117 ps
CPU time 3.1 seconds
Started Mar 28 01:25:54 PM PDT 24
Finished Mar 28 01:25:57 PM PDT 24
Peak memory 200416 kb
Host smart-4a4e0eac-ba03-41d2-9e80-2f7db6e8c303
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1964517892 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 37.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1964517892
Directory /workspace/37.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/37.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.989980135
Short name T661
Test name
Test status
Simulation time 782883137 ps
CPU time 3.11 seconds
Started Mar 28 01:25:54 PM PDT 24
Finished Mar 28 01:25:57 PM PDT 24
Peak memory 200544 kb
Host smart-d9d9a4e3-c561-414f-ada0-49da6c7c57df
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=989980135 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 37.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.989980135
Directory /workspace/37.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/37.pwrmgr_sec_cm_rstmgr_intersig_mubi.3105792908
Short name T198
Test name
Test status
Simulation time 74762951 ps
CPU time 0.97 seconds
Started Mar 28 01:25:54 PM PDT 24
Finished Mar 28 01:25:55 PM PDT 24
Peak memory 198684 kb
Host smart-f8702476-1929-4092-9950-a7a0ed16b687
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3105792908 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_sec_cm_rstmgr_intersig
_mubi.3105792908
Directory /workspace/37.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/37.pwrmgr_smoke.320719432
Short name T820
Test name
Test status
Simulation time 34010301 ps
CPU time 0.66 seconds
Started Mar 28 01:25:53 PM PDT 24
Finished Mar 28 01:25:55 PM PDT 24
Peak memory 198628 kb
Host smart-b8f3ae9d-5ded-46d4-8f44-8d332d07d454
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=320719432 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_smoke.320719432
Directory /workspace/37.pwrmgr_smoke/latest

Test location /workspace/coverage/default/37.pwrmgr_stress_all.1003273270
Short name T82
Test name
Test status
Simulation time 1667798964 ps
CPU time 6.68 seconds
Started Mar 28 01:25:52 PM PDT 24
Finished Mar 28 01:26:00 PM PDT 24
Peak memory 200524 kb
Host smart-633fbb41-b998-4101-994f-8d0d1e6ca5eb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1003273270 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_stress_all.1003273270
Directory /workspace/37.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/37.pwrmgr_wakeup.626893998
Short name T733
Test name
Test status
Simulation time 216033629 ps
CPU time 0.88 seconds
Started Mar 28 01:25:54 PM PDT 24
Finished Mar 28 01:25:55 PM PDT 24
Peak memory 197892 kb
Host smart-483e63d6-9628-4834-ac66-1fe00591f92a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=626893998 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_wakeup.626893998
Directory /workspace/37.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/37.pwrmgr_wakeup_reset.3236579992
Short name T325
Test name
Test status
Simulation time 517218064 ps
CPU time 1.15 seconds
Started Mar 28 01:25:51 PM PDT 24
Finished Mar 28 01:25:53 PM PDT 24
Peak memory 200436 kb
Host smart-66081ff7-4d53-4858-88e0-6d70b3f8afae
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3236579992 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_wakeup_reset.3236579992
Directory /workspace/37.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/38.pwrmgr_aborted_low_power.1412199220
Short name T85
Test name
Test status
Simulation time 22023945 ps
CPU time 0.68 seconds
Started Mar 28 01:25:53 PM PDT 24
Finished Mar 28 01:25:54 PM PDT 24
Peak memory 198480 kb
Host smart-289851c6-dd5d-4220-b163-04d3a4bc0386
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1412199220 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_aborted_low_power.1412199220
Directory /workspace/38.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/38.pwrmgr_esc_clk_rst_malfunc.2910860267
Short name T214
Test name
Test status
Simulation time 44442320 ps
CPU time 0.61 seconds
Started Mar 28 01:25:55 PM PDT 24
Finished Mar 28 01:25:57 PM PDT 24
Peak memory 197276 kb
Host smart-018ba961-b04f-451c-afdf-a3f86a64f6cd
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2910860267 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_esc_clk_rst
_malfunc.2910860267
Directory /workspace/38.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/38.pwrmgr_escalation_timeout.66943105
Short name T905
Test name
Test status
Simulation time 164713015 ps
CPU time 0.96 seconds
Started Mar 28 01:25:51 PM PDT 24
Finished Mar 28 01:25:53 PM PDT 24
Peak memory 197312 kb
Host smart-12bddbd4-2ed5-4152-8c00-02440959f92a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=66943105 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_escalation_timeout.66943105
Directory /workspace/38.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/38.pwrmgr_glitch.181820925
Short name T260
Test name
Test status
Simulation time 35744381 ps
CPU time 0.6 seconds
Started Mar 28 01:25:51 PM PDT 24
Finished Mar 28 01:25:52 PM PDT 24
Peak memory 196636 kb
Host smart-7f130063-65ae-4ee9-8664-5db22e818636
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=181820925 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_glitch.181820925
Directory /workspace/38.pwrmgr_glitch/latest

Test location /workspace/coverage/default/38.pwrmgr_global_esc.3670429128
Short name T312
Test name
Test status
Simulation time 95988896 ps
CPU time 0.62 seconds
Started Mar 28 01:25:52 PM PDT 24
Finished Mar 28 01:25:54 PM PDT 24
Peak memory 197428 kb
Host smart-696a30e0-ecd7-4971-8daf-fae254bae019
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3670429128 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_global_esc.3670429128
Directory /workspace/38.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/38.pwrmgr_lowpower_invalid.1062695503
Short name T880
Test name
Test status
Simulation time 77160299 ps
CPU time 0.71 seconds
Started Mar 28 01:25:55 PM PDT 24
Finished Mar 28 01:25:57 PM PDT 24
Peak memory 200636 kb
Host smart-a363a44f-a769-41a1-a5fc-2bd4f223a29c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1062695503 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_lowpower_inval
id.1062695503
Directory /workspace/38.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/38.pwrmgr_lowpower_wakeup_race.3068249260
Short name T393
Test name
Test status
Simulation time 149869176 ps
CPU time 0.99 seconds
Started Mar 28 01:25:50 PM PDT 24
Finished Mar 28 01:25:51 PM PDT 24
Peak memory 197740 kb
Host smart-a8826ac1-2f8c-49a9-bb5e-20e3e0008ac3
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3068249260 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_lowpower_w
akeup_race.3068249260
Directory /workspace/38.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/38.pwrmgr_reset.508368632
Short name T688
Test name
Test status
Simulation time 57392283 ps
CPU time 0.95 seconds
Started Mar 28 01:25:54 PM PDT 24
Finished Mar 28 01:25:55 PM PDT 24
Peak memory 198520 kb
Host smart-fc0c893f-53e7-43c0-9981-da93ffc21b90
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=508368632 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_reset.508368632
Directory /workspace/38.pwrmgr_reset/latest

Test location /workspace/coverage/default/38.pwrmgr_reset_invalid.334017065
Short name T167
Test name
Test status
Simulation time 168819924 ps
CPU time 0.88 seconds
Started Mar 28 01:25:54 PM PDT 24
Finished Mar 28 01:25:55 PM PDT 24
Peak memory 208900 kb
Host smart-6feecd4c-d1e2-4655-9d71-ed09138ed39e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=334017065 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_reset_invalid.334017065
Directory /workspace/38.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/38.pwrmgr_sec_cm_ctrl_config_regwen.2588906563
Short name T767
Test name
Test status
Simulation time 266492609 ps
CPU time 1.42 seconds
Started Mar 28 01:25:54 PM PDT 24
Finished Mar 28 01:25:57 PM PDT 24
Peak memory 200304 kb
Host smart-3cfdfd2a-f641-4f90-87d8-2b00b10c3feb
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2588906563 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_sec_
cm_ctrl_config_regwen.2588906563
Directory /workspace/38.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/38.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1170094077
Short name T309
Test name
Test status
Simulation time 1018802823 ps
CPU time 2.01 seconds
Started Mar 28 01:25:52 PM PDT 24
Finished Mar 28 01:25:55 PM PDT 24
Peak memory 200584 kb
Host smart-b9088cdb-f074-469b-82ee-a71e092ab5c2
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1170094077 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 38.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1170094077
Directory /workspace/38.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/38.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.177929546
Short name T684
Test name
Test status
Simulation time 810691078 ps
CPU time 3.56 seconds
Started Mar 28 01:25:51 PM PDT 24
Finished Mar 28 01:25:55 PM PDT 24
Peak memory 200624 kb
Host smart-c084a2e0-9046-40fc-a624-5b325a24ec48
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=177929546 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 38.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.177929546
Directory /workspace/38.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/38.pwrmgr_sec_cm_rstmgr_intersig_mubi.1644994996
Short name T338
Test name
Test status
Simulation time 74488773 ps
CPU time 1.03 seconds
Started Mar 28 01:25:54 PM PDT 24
Finished Mar 28 01:25:55 PM PDT 24
Peak memory 198620 kb
Host smart-c61065e8-0fb0-4033-a932-a41b8370f317
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1644994996 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_sec_cm_rstmgr_intersig
_mubi.1644994996
Directory /workspace/38.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/38.pwrmgr_smoke.3409862524
Short name T192
Test name
Test status
Simulation time 31309919 ps
CPU time 0.76 seconds
Started Mar 28 01:25:55 PM PDT 24
Finished Mar 28 01:25:57 PM PDT 24
Peak memory 198704 kb
Host smart-b7524552-9200-4445-925f-7c7196c6b5ac
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3409862524 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_smoke.3409862524
Directory /workspace/38.pwrmgr_smoke/latest

Test location /workspace/coverage/default/38.pwrmgr_stress_all.571142731
Short name T68
Test name
Test status
Simulation time 707574531 ps
CPU time 1.52 seconds
Started Mar 28 01:25:56 PM PDT 24
Finished Mar 28 01:25:58 PM PDT 24
Peak memory 200348 kb
Host smart-e84d41d6-772f-41a3-be1e-e672a7a0feb5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=571142731 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_stress_all.571142731
Directory /workspace/38.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/38.pwrmgr_stress_all_with_rand_reset.3430931950
Short name T124
Test name
Test status
Simulation time 8485909590 ps
CPU time 26.15 seconds
Started Mar 28 01:25:55 PM PDT 24
Finished Mar 28 01:26:22 PM PDT 24
Peak memory 200792 kb
Host smart-38b379a4-fedc-4f9c-bcf5-fe5d4e7913b7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3430931950 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 38.pwrmgr_stress_all_with_rand_reset.3430931950
Directory /workspace/38.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.pwrmgr_wakeup.2869574141
Short name T847
Test name
Test status
Simulation time 569249610 ps
CPU time 0.97 seconds
Started Mar 28 01:25:55 PM PDT 24
Finished Mar 28 01:25:57 PM PDT 24
Peak memory 198876 kb
Host smart-f3911ae0-a44e-490c-8f18-c3b5a6c99a4b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2869574141 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_wakeup.2869574141
Directory /workspace/38.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/38.pwrmgr_wakeup_reset.1393323351
Short name T831
Test name
Test status
Simulation time 146673143 ps
CPU time 0.8 seconds
Started Mar 28 01:25:55 PM PDT 24
Finished Mar 28 01:25:57 PM PDT 24
Peak memory 198612 kb
Host smart-059a2d9d-cf38-4153-9cc6-79d5dc77ff44
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1393323351 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_wakeup_reset.1393323351
Directory /workspace/38.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/39.pwrmgr_aborted_low_power.1048240533
Short name T467
Test name
Test status
Simulation time 82820019 ps
CPU time 0.91 seconds
Started Mar 28 01:25:57 PM PDT 24
Finished Mar 28 01:25:58 PM PDT 24
Peak memory 199640 kb
Host smart-0941864e-a66a-4472-8438-3c5b39f2abd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1048240533 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_aborted_low_power.1048240533
Directory /workspace/39.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/39.pwrmgr_disable_rom_integrity_check.3924830638
Short name T913
Test name
Test status
Simulation time 92982228 ps
CPU time 0.73 seconds
Started Mar 28 01:26:06 PM PDT 24
Finished Mar 28 01:26:07 PM PDT 24
Peak memory 198396 kb
Host smart-bc342c49-fb6b-4d3d-8b8d-ef4f45a40b78
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3924830638 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_dis
able_rom_integrity_check.3924830638
Directory /workspace/39.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/39.pwrmgr_esc_clk_rst_malfunc.4246269866
Short name T886
Test name
Test status
Simulation time 56708912 ps
CPU time 0.59 seconds
Started Mar 28 01:25:54 PM PDT 24
Finished Mar 28 01:25:55 PM PDT 24
Peak memory 197376 kb
Host smart-a77432aa-5423-41cb-87a8-6dd9578cd760
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4246269866 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_esc_clk_rst
_malfunc.4246269866
Directory /workspace/39.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/39.pwrmgr_escalation_timeout.3176908195
Short name T796
Test name
Test status
Simulation time 808804518 ps
CPU time 0.98 seconds
Started Mar 28 01:26:09 PM PDT 24
Finished Mar 28 01:26:10 PM PDT 24
Peak memory 197428 kb
Host smart-a9c36a4f-128e-40ac-8f47-6b4fa49e9bdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3176908195 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_escalation_timeout.3176908195
Directory /workspace/39.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/39.pwrmgr_glitch.1997454239
Short name T671
Test name
Test status
Simulation time 30399742 ps
CPU time 0.62 seconds
Started Mar 28 01:26:06 PM PDT 24
Finished Mar 28 01:26:07 PM PDT 24
Peak memory 197456 kb
Host smart-888655d9-78dd-41cd-a942-6c33005ec199
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1997454239 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_glitch.1997454239
Directory /workspace/39.pwrmgr_glitch/latest

Test location /workspace/coverage/default/39.pwrmgr_global_esc.4052269252
Short name T379
Test name
Test status
Simulation time 76629374 ps
CPU time 0.62 seconds
Started Mar 28 01:25:57 PM PDT 24
Finished Mar 28 01:25:58 PM PDT 24
Peak memory 197424 kb
Host smart-426946d7-d335-4a09-bc2e-6532a020ae02
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4052269252 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_global_esc.4052269252
Directory /workspace/39.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/39.pwrmgr_lowpower_invalid.2802164428
Short name T943
Test name
Test status
Simulation time 98651992 ps
CPU time 0.65 seconds
Started Mar 28 01:26:04 PM PDT 24
Finished Mar 28 01:26:05 PM PDT 24
Peak memory 200680 kb
Host smart-4c7befdf-b4ec-4b67-aad8-d3bbe1b8f2a8
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2802164428 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_lowpower_inval
id.2802164428
Directory /workspace/39.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/39.pwrmgr_lowpower_wakeup_race.3946756519
Short name T894
Test name
Test status
Simulation time 415712936 ps
CPU time 0.93 seconds
Started Mar 28 01:25:55 PM PDT 24
Finished Mar 28 01:25:57 PM PDT 24
Peak memory 199092 kb
Host smart-0c1f5d5b-c609-4d6f-8a3d-ca0dcc2c5c84
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3946756519 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_lowpower_w
akeup_race.3946756519
Directory /workspace/39.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/39.pwrmgr_reset.3398512960
Short name T704
Test name
Test status
Simulation time 104717507 ps
CPU time 0.84 seconds
Started Mar 28 01:25:56 PM PDT 24
Finished Mar 28 01:25:57 PM PDT 24
Peak memory 199268 kb
Host smart-c8ff09d8-3fef-4a64-b6a6-f655ff8fb1f8
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3398512960 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_reset.3398512960
Directory /workspace/39.pwrmgr_reset/latest

Test location /workspace/coverage/default/39.pwrmgr_reset_invalid.938550929
Short name T399
Test name
Test status
Simulation time 100155509 ps
CPU time 1.05 seconds
Started Mar 28 01:26:07 PM PDT 24
Finished Mar 28 01:26:08 PM PDT 24
Peak memory 208828 kb
Host smart-3becf23c-6529-438a-8422-b5c3e22dca36
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=938550929 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_reset_invalid.938550929
Directory /workspace/39.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/39.pwrmgr_sec_cm_ctrl_config_regwen.3083679711
Short name T828
Test name
Test status
Simulation time 241134037 ps
CPU time 1.47 seconds
Started Mar 28 01:25:57 PM PDT 24
Finished Mar 28 01:25:59 PM PDT 24
Peak memory 200212 kb
Host smart-7aff13c5-7abb-4e3a-86b4-45c442278ce9
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3083679711 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_sec_
cm_ctrl_config_regwen.3083679711
Directory /workspace/39.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/39.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.93098980
Short name T432
Test name
Test status
Simulation time 1490267096 ps
CPU time 2.32 seconds
Started Mar 28 01:25:53 PM PDT 24
Finished Mar 28 01:25:56 PM PDT 24
Peak memory 200532 kb
Host smart-abc27049-9155-4bbf-a0fd-dd7a783ebd4d
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93098980 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +
UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 39.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.93098980
Directory /workspace/39.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/39.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2993891904
Short name T333
Test name
Test status
Simulation time 1025165025 ps
CPU time 2.22 seconds
Started Mar 28 01:25:57 PM PDT 24
Finished Mar 28 01:26:00 PM PDT 24
Peak memory 200560 kb
Host smart-1e8d86de-39b1-4be7-bb81-b33a071e02f0
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2993891904 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 39.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2993891904
Directory /workspace/39.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/39.pwrmgr_sec_cm_rstmgr_intersig_mubi.2511372356
Short name T585
Test name
Test status
Simulation time 187323381 ps
CPU time 0.9 seconds
Started Mar 28 01:25:53 PM PDT 24
Finished Mar 28 01:25:55 PM PDT 24
Peak memory 198668 kb
Host smart-36425402-b32c-465c-b35c-2afc2b2478f9
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2511372356 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_sec_cm_rstmgr_intersig
_mubi.2511372356
Directory /workspace/39.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/39.pwrmgr_smoke.3736037685
Short name T807
Test name
Test status
Simulation time 30825370 ps
CPU time 0.63 seconds
Started Mar 28 01:25:55 PM PDT 24
Finished Mar 28 01:25:57 PM PDT 24
Peak memory 198664 kb
Host smart-45960f9b-7b78-4329-a894-b899e8b1e0b5
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3736037685 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_smoke.3736037685
Directory /workspace/39.pwrmgr_smoke/latest

Test location /workspace/coverage/default/39.pwrmgr_stress_all.3811129651
Short name T833
Test name
Test status
Simulation time 891439084 ps
CPU time 3.16 seconds
Started Mar 28 01:26:04 PM PDT 24
Finished Mar 28 01:26:08 PM PDT 24
Peak memory 200596 kb
Host smart-5f6b27d6-f013-4da3-9cae-c60655b2c2ab
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3811129651 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_stress_all.3811129651
Directory /workspace/39.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/39.pwrmgr_stress_all_with_rand_reset.3342010829
Short name T813
Test name
Test status
Simulation time 13486939669 ps
CPU time 41.42 seconds
Started Mar 28 01:26:09 PM PDT 24
Finished Mar 28 01:26:50 PM PDT 24
Peak memory 200928 kb
Host smart-31b17054-d94e-49d1-9fcd-f674729c0dd1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3342010829 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 39.pwrmgr_stress_all_with_rand_reset.3342010829
Directory /workspace/39.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.pwrmgr_wakeup.4195015106
Short name T251
Test name
Test status
Simulation time 462202738 ps
CPU time 0.84 seconds
Started Mar 28 01:25:54 PM PDT 24
Finished Mar 28 01:25:55 PM PDT 24
Peak memory 198844 kb
Host smart-8636ab13-5198-4f9a-900f-333bb68740da
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4195015106 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_wakeup.4195015106
Directory /workspace/39.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/39.pwrmgr_wakeup_reset.1706312014
Short name T389
Test name
Test status
Simulation time 176367367 ps
CPU time 0.94 seconds
Started Mar 28 01:25:57 PM PDT 24
Finished Mar 28 01:25:58 PM PDT 24
Peak memory 199540 kb
Host smart-2994df0a-578a-45a9-b506-160277dd2cb5
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1706312014 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_wakeup_reset.1706312014
Directory /workspace/39.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/4.pwrmgr_aborted_low_power.3142803378
Short name T480
Test name
Test status
Simulation time 84343705 ps
CPU time 0.71 seconds
Started Mar 28 01:22:16 PM PDT 24
Finished Mar 28 01:22:17 PM PDT 24
Peak memory 198092 kb
Host smart-b766fb48-7c68-45c9-a098-48fefc36303d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3142803378 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_aborted_low_power.3142803378
Directory /workspace/4.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/4.pwrmgr_disable_rom_integrity_check.2331234696
Short name T893
Test name
Test status
Simulation time 103634802 ps
CPU time 0.75 seconds
Started Mar 28 01:22:32 PM PDT 24
Finished Mar 28 01:22:33 PM PDT 24
Peak memory 198364 kb
Host smart-ece0ff45-8615-4d1c-baaf-a5ac7075101a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2331234696 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_disa
ble_rom_integrity_check.2331234696
Directory /workspace/4.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/4.pwrmgr_esc_clk_rst_malfunc.1314945594
Short name T741
Test name
Test status
Simulation time 30396889 ps
CPU time 0.65 seconds
Started Mar 28 01:22:31 PM PDT 24
Finished Mar 28 01:22:31 PM PDT 24
Peak memory 197364 kb
Host smart-5459b2ae-a65e-456f-a40a-8f6f29a22786
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1314945594 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_esc_clk_rst_
malfunc.1314945594
Directory /workspace/4.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/4.pwrmgr_escalation_timeout.2958115448
Short name T836
Test name
Test status
Simulation time 162693676 ps
CPU time 0.93 seconds
Started Mar 28 01:22:33 PM PDT 24
Finished Mar 28 01:22:34 PM PDT 24
Peak memory 197756 kb
Host smart-49867043-b0a7-4a07-9775-7c89e17f5ad6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2958115448 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_escalation_timeout.2958115448
Directory /workspace/4.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/4.pwrmgr_glitch.922523193
Short name T719
Test name
Test status
Simulation time 50251457 ps
CPU time 0.61 seconds
Started Mar 28 01:22:32 PM PDT 24
Finished Mar 28 01:22:33 PM PDT 24
Peak memory 197404 kb
Host smart-555cc7dc-eeca-4fb4-a392-b674ec93695b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=922523193 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_glitch.922523193
Directory /workspace/4.pwrmgr_glitch/latest

Test location /workspace/coverage/default/4.pwrmgr_global_esc.3455867320
Short name T203
Test name
Test status
Simulation time 33330707 ps
CPU time 0.62 seconds
Started Mar 28 01:22:32 PM PDT 24
Finished Mar 28 01:22:33 PM PDT 24
Peak memory 197688 kb
Host smart-e06377c6-1049-45c1-aeff-dcbfaa237aeb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3455867320 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_global_esc.3455867320
Directory /workspace/4.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/4.pwrmgr_lowpower_invalid.1353005849
Short name T233
Test name
Test status
Simulation time 112935496 ps
CPU time 0.64 seconds
Started Mar 28 01:22:33 PM PDT 24
Finished Mar 28 01:22:34 PM PDT 24
Peak memory 200700 kb
Host smart-779be5ef-47a4-41f1-a668-c27e601b7105
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1353005849 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_lowpower_invali
d.1353005849
Directory /workspace/4.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/4.pwrmgr_lowpower_wakeup_race.1790734735
Short name T180
Test name
Test status
Simulation time 137114852 ps
CPU time 0.71 seconds
Started Mar 28 01:22:16 PM PDT 24
Finished Mar 28 01:22:17 PM PDT 24
Peak memory 198316 kb
Host smart-860fc374-c210-486b-821c-76826973fe95
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1790734735 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_lowpower_wa
keup_race.1790734735
Directory /workspace/4.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/4.pwrmgr_reset.1896346278
Short name T635
Test name
Test status
Simulation time 92905236 ps
CPU time 0.73 seconds
Started Mar 28 01:22:19 PM PDT 24
Finished Mar 28 01:22:20 PM PDT 24
Peak memory 198356 kb
Host smart-9d2a406c-eae7-4e38-ac30-26c7a8cc8c21
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1896346278 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_reset.1896346278
Directory /workspace/4.pwrmgr_reset/latest

Test location /workspace/coverage/default/4.pwrmgr_reset_invalid.865286860
Short name T722
Test name
Test status
Simulation time 91752362 ps
CPU time 1 seconds
Started Mar 28 01:22:31 PM PDT 24
Finished Mar 28 01:22:32 PM PDT 24
Peak memory 208816 kb
Host smart-ae029a5b-8581-4f9a-84a3-20ccce276651
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=865286860 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_reset_invalid.865286860
Directory /workspace/4.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/4.pwrmgr_sec_cm.1956798707
Short name T17
Test name
Test status
Simulation time 637030702 ps
CPU time 2.04 seconds
Started Mar 28 01:22:32 PM PDT 24
Finished Mar 28 01:22:35 PM PDT 24
Peak memory 217416 kb
Host smart-8495f32f-b7f1-4168-a376-54998ec83734
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1956798707 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_sec_cm.1956798707
Directory /workspace/4.pwrmgr_sec_cm/latest

Test location /workspace/coverage/default/4.pwrmgr_sec_cm_ctrl_config_regwen.2411711531
Short name T790
Test name
Test status
Simulation time 153099489 ps
CPU time 0.85 seconds
Started Mar 28 01:22:34 PM PDT 24
Finished Mar 28 01:22:36 PM PDT 24
Peak memory 199120 kb
Host smart-1256f85c-d779-451b-a294-819a89198acf
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2411711531 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_sec_c
m_ctrl_config_regwen.2411711531
Directory /workspace/4.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/4.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2998873197
Short name T128
Test name
Test status
Simulation time 1166605523 ps
CPU time 2.34 seconds
Started Mar 28 01:22:17 PM PDT 24
Finished Mar 28 01:22:19 PM PDT 24
Peak memory 200476 kb
Host smart-1226ffb6-6be3-4564-b6bb-1e91f7488d14
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2998873197 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 4.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2998873197
Directory /workspace/4.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/4.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3291176755
Short name T30
Test name
Test status
Simulation time 891962596 ps
CPU time 3.4 seconds
Started Mar 28 01:22:32 PM PDT 24
Finished Mar 28 01:22:36 PM PDT 24
Peak memory 200492 kb
Host smart-511bb105-c42f-45de-ae61-207e2ff8275b
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3291176755 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 4.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3291176755
Directory /workspace/4.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/4.pwrmgr_sec_cm_rstmgr_intersig_mubi.1215713657
Short name T584
Test name
Test status
Simulation time 62265178 ps
CPU time 0.92 seconds
Started Mar 28 01:22:34 PM PDT 24
Finished Mar 28 01:22:36 PM PDT 24
Peak memory 198508 kb
Host smart-f1daff0b-5922-4a6a-afce-493ed807f6e0
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1215713657 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_sec_cm_rstmgr_intersig_
mubi.1215713657
Directory /workspace/4.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/4.pwrmgr_smoke.3866069945
Short name T534
Test name
Test status
Simulation time 37656904 ps
CPU time 0.64 seconds
Started Mar 28 01:22:17 PM PDT 24
Finished Mar 28 01:22:18 PM PDT 24
Peak memory 197808 kb
Host smart-a28d25c6-b7a6-4504-b2f0-67161e736549
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3866069945 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_smoke.3866069945
Directory /workspace/4.pwrmgr_smoke/latest

Test location /workspace/coverage/default/4.pwrmgr_stress_all.1426131766
Short name T254
Test name
Test status
Simulation time 553691492 ps
CPU time 2.41 seconds
Started Mar 28 01:22:31 PM PDT 24
Finished Mar 28 01:22:34 PM PDT 24
Peak memory 200644 kb
Host smart-b8245f5d-5bcf-4120-b189-c16a8c073a3a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1426131766 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_stress_all.1426131766
Directory /workspace/4.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/4.pwrmgr_stress_all_with_rand_reset.1620775675
Short name T721
Test name
Test status
Simulation time 3595938435 ps
CPU time 12.09 seconds
Started Mar 28 01:22:36 PM PDT 24
Finished Mar 28 01:22:49 PM PDT 24
Peak memory 200840 kb
Host smart-6812625b-1f50-4b43-afb4-cb3f7893aef4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1620775675 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 4.pwrmgr_stress_all_with_rand_reset.1620775675
Directory /workspace/4.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.pwrmgr_wakeup.123110663
Short name T428
Test name
Test status
Simulation time 155836070 ps
CPU time 0.92 seconds
Started Mar 28 01:22:25 PM PDT 24
Finished Mar 28 01:22:27 PM PDT 24
Peak memory 198936 kb
Host smart-910ac02b-8644-4763-99b7-01fc4154287d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=123110663 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_wakeup.123110663
Directory /workspace/4.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/4.pwrmgr_wakeup_reset.722729789
Short name T827
Test name
Test status
Simulation time 249276308 ps
CPU time 1.41 seconds
Started Mar 28 01:22:18 PM PDT 24
Finished Mar 28 01:22:20 PM PDT 24
Peak memory 200508 kb
Host smart-21a64805-e1f6-44c3-a7bb-c739d7a2d61c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=722729789 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_wakeup_reset.722729789
Directory /workspace/4.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/40.pwrmgr_aborted_low_power.2160075632
Short name T692
Test name
Test status
Simulation time 31540401 ps
CPU time 0.78 seconds
Started Mar 28 01:26:10 PM PDT 24
Finished Mar 28 01:26:11 PM PDT 24
Peak memory 198232 kb
Host smart-4fd6e1f1-a40a-4853-ac34-01dc8cba39ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2160075632 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_aborted_low_power.2160075632
Directory /workspace/40.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/40.pwrmgr_disable_rom_integrity_check.567449874
Short name T144
Test name
Test status
Simulation time 68396524 ps
CPU time 0.69 seconds
Started Mar 28 01:26:10 PM PDT 24
Finished Mar 28 01:26:11 PM PDT 24
Peak memory 198472 kb
Host smart-30d8624f-0b98-4cad-8848-9cbb57ae263f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=567449874 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_in
tegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_disa
ble_rom_integrity_check.567449874
Directory /workspace/40.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/40.pwrmgr_esc_clk_rst_malfunc.423665759
Short name T771
Test name
Test status
Simulation time 31547883 ps
CPU time 0.69 seconds
Started Mar 28 01:26:09 PM PDT 24
Finished Mar 28 01:26:09 PM PDT 24
Peak memory 196668 kb
Host smart-71170fed-ddb9-4349-b409-11ef52e3e170
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=423665759 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_ma
lfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_esc_clk_rst_
malfunc.423665759
Directory /workspace/40.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/40.pwrmgr_escalation_timeout.3592365132
Short name T172
Test name
Test status
Simulation time 187992079 ps
CPU time 0.99 seconds
Started Mar 28 01:26:09 PM PDT 24
Finished Mar 28 01:26:11 PM PDT 24
Peak memory 197472 kb
Host smart-4e4d56e0-6d89-49ce-bcb4-feb2f4a4355d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3592365132 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_escalation_timeout.3592365132
Directory /workspace/40.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/40.pwrmgr_glitch.636691833
Short name T848
Test name
Test status
Simulation time 65466730 ps
CPU time 0.62 seconds
Started Mar 28 01:26:05 PM PDT 24
Finished Mar 28 01:26:06 PM PDT 24
Peak memory 197412 kb
Host smart-14eaec6a-11e7-4f98-8803-4693f08c5e43
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=636691833 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_glitch.636691833
Directory /workspace/40.pwrmgr_glitch/latest

Test location /workspace/coverage/default/40.pwrmgr_global_esc.2194093563
Short name T923
Test name
Test status
Simulation time 81205241 ps
CPU time 0.61 seconds
Started Mar 28 01:26:09 PM PDT 24
Finished Mar 28 01:26:10 PM PDT 24
Peak memory 197696 kb
Host smart-b1e26bb8-4c95-4585-a0fe-1eb19c06f724
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2194093563 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_global_esc.2194093563
Directory /workspace/40.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/40.pwrmgr_lowpower_invalid.3703043900
Short name T736
Test name
Test status
Simulation time 46372384 ps
CPU time 0.75 seconds
Started Mar 28 01:26:08 PM PDT 24
Finished Mar 28 01:26:09 PM PDT 24
Peak memory 199856 kb
Host smart-e56d1f9b-414f-456d-b922-d4cacd10f6f8
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3703043900 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_lowpower_inval
id.3703043900
Directory /workspace/40.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/40.pwrmgr_lowpower_wakeup_race.3149581721
Short name T728
Test name
Test status
Simulation time 537509644 ps
CPU time 0.88 seconds
Started Mar 28 01:26:13 PM PDT 24
Finished Mar 28 01:26:14 PM PDT 24
Peak memory 198832 kb
Host smart-7ef23297-74c1-40f7-8f38-2174b1f7bc8c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3149581721 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_lowpower_w
akeup_race.3149581721
Directory /workspace/40.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/40.pwrmgr_reset.891150229
Short name T577
Test name
Test status
Simulation time 50682232 ps
CPU time 0.87 seconds
Started Mar 28 01:26:09 PM PDT 24
Finished Mar 28 01:26:10 PM PDT 24
Peak memory 198536 kb
Host smart-02ff57ed-d368-41f9-b73d-d4512af9c6c5
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=891150229 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_reset.891150229
Directory /workspace/40.pwrmgr_reset/latest

Test location /workspace/coverage/default/40.pwrmgr_reset_invalid.1346613234
Short name T738
Test name
Test status
Simulation time 171995460 ps
CPU time 0.77 seconds
Started Mar 28 01:26:15 PM PDT 24
Finished Mar 28 01:26:16 PM PDT 24
Peak memory 208896 kb
Host smart-11e43a5f-cfa8-455c-b7da-bf1805517ed5
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1346613234 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_reset_invalid.1346613234
Directory /workspace/40.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/40.pwrmgr_sec_cm_ctrl_config_regwen.1064586272
Short name T45
Test name
Test status
Simulation time 263799537 ps
CPU time 0.72 seconds
Started Mar 28 01:26:08 PM PDT 24
Finished Mar 28 01:26:09 PM PDT 24
Peak memory 198020 kb
Host smart-9fcb9a32-b14f-4a1f-a747-91009b93ca2d
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1064586272 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_sec_
cm_ctrl_config_regwen.1064586272
Directory /workspace/40.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/40.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2485266629
Short name T626
Test name
Test status
Simulation time 927666511 ps
CPU time 2.48 seconds
Started Mar 28 01:26:05 PM PDT 24
Finished Mar 28 01:26:08 PM PDT 24
Peak memory 200528 kb
Host smart-5fb352f1-3533-4814-afbd-7771dfe06499
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2485266629 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 40.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2485266629
Directory /workspace/40.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/40.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1677477231
Short name T854
Test name
Test status
Simulation time 823690475 ps
CPU time 3.12 seconds
Started Mar 28 01:26:06 PM PDT 24
Finished Mar 28 01:26:09 PM PDT 24
Peak memory 200376 kb
Host smart-3f9931f5-7c36-46ff-996e-eb17e671d044
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1677477231 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 40.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1677477231
Directory /workspace/40.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/40.pwrmgr_sec_cm_rstmgr_intersig_mubi.1024316544
Short name T810
Test name
Test status
Simulation time 52690896 ps
CPU time 0.91 seconds
Started Mar 28 01:26:10 PM PDT 24
Finished Mar 28 01:26:11 PM PDT 24
Peak memory 198668 kb
Host smart-6da16ddc-dd02-4c2a-93c5-e3103c45a247
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1024316544 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_sec_cm_rstmgr_intersig
_mubi.1024316544
Directory /workspace/40.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/40.pwrmgr_smoke.3034346795
Short name T702
Test name
Test status
Simulation time 78659404 ps
CPU time 0.63 seconds
Started Mar 28 01:26:09 PM PDT 24
Finished Mar 28 01:26:10 PM PDT 24
Peak memory 198660 kb
Host smart-0738d783-3d37-4593-8dee-34d28b7c0be1
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3034346795 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_smoke.3034346795
Directory /workspace/40.pwrmgr_smoke/latest

Test location /workspace/coverage/default/40.pwrmgr_stress_all.324726418
Short name T940
Test name
Test status
Simulation time 2792697203 ps
CPU time 3.98 seconds
Started Mar 28 01:26:09 PM PDT 24
Finished Mar 28 01:26:13 PM PDT 24
Peak memory 200704 kb
Host smart-1d31d1b9-a6bb-44da-b40e-34af92dd772c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=324726418 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_stress_all.324726418
Directory /workspace/40.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/40.pwrmgr_stress_all_with_rand_reset.881551252
Short name T916
Test name
Test status
Simulation time 15897008299 ps
CPU time 11.08 seconds
Started Mar 28 01:26:07 PM PDT 24
Finished Mar 28 01:26:19 PM PDT 24
Peak memory 200872 kb
Host smart-f9be2d0d-dbc7-43ec-a626-169aa02c702d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=881551252 -assert nopost
proc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 40.pwrmgr_stress_all_with_rand_reset.881551252
Directory /workspace/40.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.pwrmgr_wakeup.248242104
Short name T373
Test name
Test status
Simulation time 166356594 ps
CPU time 0.8 seconds
Started Mar 28 01:26:10 PM PDT 24
Finished Mar 28 01:26:11 PM PDT 24
Peak memory 197720 kb
Host smart-def03da4-3557-46f5-b2fe-495f1d766f01
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=248242104 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_wakeup.248242104
Directory /workspace/40.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/40.pwrmgr_wakeup_reset.2967163526
Short name T680
Test name
Test status
Simulation time 72207057 ps
CPU time 0.67 seconds
Started Mar 28 01:26:08 PM PDT 24
Finished Mar 28 01:26:08 PM PDT 24
Peak memory 198672 kb
Host smart-d9478a19-5f90-491d-8c6a-0df110beeb54
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2967163526 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_wakeup_reset.2967163526
Directory /workspace/40.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/41.pwrmgr_aborted_low_power.686931253
Short name T664
Test name
Test status
Simulation time 48794850 ps
CPU time 0.67 seconds
Started Mar 28 01:26:07 PM PDT 24
Finished Mar 28 01:26:08 PM PDT 24
Peak memory 198744 kb
Host smart-7c606612-4dd9-422f-a68e-42305abad589
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=686931253 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_aborted_low_power.686931253
Directory /workspace/41.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/41.pwrmgr_disable_rom_integrity_check.123640896
Short name T957
Test name
Test status
Simulation time 69324551 ps
CPU time 0.7 seconds
Started Mar 28 01:26:09 PM PDT 24
Finished Mar 28 01:26:10 PM PDT 24
Peak memory 197848 kb
Host smart-2d5a3240-731a-4b5b-ab6a-404ab7c6c23f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=123640896 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_in
tegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_disa
ble_rom_integrity_check.123640896
Directory /workspace/41.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/41.pwrmgr_esc_clk_rst_malfunc.3443566684
Short name T547
Test name
Test status
Simulation time 32769367 ps
CPU time 0.63 seconds
Started Mar 28 01:26:08 PM PDT 24
Finished Mar 28 01:26:09 PM PDT 24
Peak memory 196692 kb
Host smart-3219b44d-05d1-4a88-9319-246995481f94
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3443566684 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_esc_clk_rst
_malfunc.3443566684
Directory /workspace/41.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/41.pwrmgr_escalation_timeout.653624031
Short name T271
Test name
Test status
Simulation time 1529247347 ps
CPU time 0.96 seconds
Started Mar 28 01:26:09 PM PDT 24
Finished Mar 28 01:26:10 PM PDT 24
Peak memory 197316 kb
Host smart-e8dad008-716e-4e9c-b366-415a1db4d709
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=653624031 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_escalation_timeout.653624031
Directory /workspace/41.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/41.pwrmgr_glitch.1352925172
Short name T775
Test name
Test status
Simulation time 53322283 ps
CPU time 0.71 seconds
Started Mar 28 01:26:11 PM PDT 24
Finished Mar 28 01:26:12 PM PDT 24
Peak memory 197336 kb
Host smart-0c8186b9-4c1f-4c9f-b92f-7020fe0ccfd8
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1352925172 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_glitch.1352925172
Directory /workspace/41.pwrmgr_glitch/latest

Test location /workspace/coverage/default/41.pwrmgr_global_esc.2515271169
Short name T918
Test name
Test status
Simulation time 30099603 ps
CPU time 0.61 seconds
Started Mar 28 01:26:08 PM PDT 24
Finished Mar 28 01:26:08 PM PDT 24
Peak memory 197412 kb
Host smart-6a83b382-451a-4d44-9048-ed434beb5620
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2515271169 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_global_esc.2515271169
Directory /workspace/41.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/41.pwrmgr_lowpower_invalid.2620325090
Short name T177
Test name
Test status
Simulation time 52957652 ps
CPU time 0.65 seconds
Started Mar 28 01:26:08 PM PDT 24
Finished Mar 28 01:26:09 PM PDT 24
Peak memory 200708 kb
Host smart-d175564b-4eae-4d07-bb74-26641260e007
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2620325090 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_lowpower_inval
id.2620325090
Directory /workspace/41.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/41.pwrmgr_lowpower_wakeup_race.2021614186
Short name T462
Test name
Test status
Simulation time 211968851 ps
CPU time 0.77 seconds
Started Mar 28 01:26:05 PM PDT 24
Finished Mar 28 01:26:07 PM PDT 24
Peak memory 197756 kb
Host smart-bbcf35c1-42e5-40ab-b37e-39ba248c7f57
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2021614186 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_lowpower_w
akeup_race.2021614186
Directory /workspace/41.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/41.pwrmgr_reset.2212481270
Short name T783
Test name
Test status
Simulation time 69227682 ps
CPU time 0.66 seconds
Started Mar 28 01:26:09 PM PDT 24
Finished Mar 28 01:26:10 PM PDT 24
Peak memory 197896 kb
Host smart-a2113fcd-d617-40ca-b9d2-e0b68c0b06cb
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2212481270 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_reset.2212481270
Directory /workspace/41.pwrmgr_reset/latest

Test location /workspace/coverage/default/41.pwrmgr_reset_invalid.726587395
Short name T621
Test name
Test status
Simulation time 152593877 ps
CPU time 0.88 seconds
Started Mar 28 01:26:07 PM PDT 24
Finished Mar 28 01:26:07 PM PDT 24
Peak memory 208900 kb
Host smart-fab51a8d-24f9-4012-9a7a-1396b898d592
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=726587395 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_reset_invalid.726587395
Directory /workspace/41.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/41.pwrmgr_sec_cm_ctrl_config_regwen.1216751726
Short name T816
Test name
Test status
Simulation time 818265316 ps
CPU time 1.09 seconds
Started Mar 28 01:26:10 PM PDT 24
Finished Mar 28 01:26:11 PM PDT 24
Peak memory 200128 kb
Host smart-429de51c-22de-43a8-b2f7-2115e616801a
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1216751726 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_sec_
cm_ctrl_config_regwen.1216751726
Directory /workspace/41.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/41.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.467663759
Short name T416
Test name
Test status
Simulation time 1010679701 ps
CPU time 2.26 seconds
Started Mar 28 01:26:11 PM PDT 24
Finished Mar 28 01:26:13 PM PDT 24
Peak memory 200340 kb
Host smart-f0fbc52f-4477-46da-9d10-4cc88d27e5fb
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=467663759 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 41.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.467663759
Directory /workspace/41.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/41.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3248588000
Short name T647
Test name
Test status
Simulation time 1267763947 ps
CPU time 2.04 seconds
Started Mar 28 01:26:14 PM PDT 24
Finished Mar 28 01:26:16 PM PDT 24
Peak memory 200528 kb
Host smart-4aef7430-234f-494a-884a-d34f136c29f0
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3248588000 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 41.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3248588000
Directory /workspace/41.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/41.pwrmgr_sec_cm_rstmgr_intersig_mubi.2087072365
Short name T935
Test name
Test status
Simulation time 139682721 ps
CPU time 0.88 seconds
Started Mar 28 01:26:14 PM PDT 24
Finished Mar 28 01:26:15 PM PDT 24
Peak memory 198512 kb
Host smart-3d8cf6aa-40e7-4509-9ca2-c1c433c07d7f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2087072365 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_sec_cm_rstmgr_intersig
_mubi.2087072365
Directory /workspace/41.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/41.pwrmgr_smoke.2921778436
Short name T442
Test name
Test status
Simulation time 47840995 ps
CPU time 0.64 seconds
Started Mar 28 01:26:08 PM PDT 24
Finished Mar 28 01:26:09 PM PDT 24
Peak memory 198596 kb
Host smart-348858a3-1e8a-474e-9894-c954ee49a083
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2921778436 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_smoke.2921778436
Directory /workspace/41.pwrmgr_smoke/latest

Test location /workspace/coverage/default/41.pwrmgr_stress_all.3289988543
Short name T662
Test name
Test status
Simulation time 2126941949 ps
CPU time 3.38 seconds
Started Mar 28 01:26:14 PM PDT 24
Finished Mar 28 01:26:17 PM PDT 24
Peak memory 200536 kb
Host smart-cbea2cb8-0859-43a5-8cbf-272df7295f5c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3289988543 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_stress_all.3289988543
Directory /workspace/41.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/41.pwrmgr_stress_all_with_rand_reset.2325493639
Short name T747
Test name
Test status
Simulation time 17238323943 ps
CPU time 17.05 seconds
Started Mar 28 01:26:08 PM PDT 24
Finished Mar 28 01:26:25 PM PDT 24
Peak memory 200020 kb
Host smart-21b78bd3-d7df-4514-adc5-4cc2eee5d3a2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2325493639 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 41.pwrmgr_stress_all_with_rand_reset.2325493639
Directory /workspace/41.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.pwrmgr_wakeup.75953090
Short name T859
Test name
Test status
Simulation time 108860091 ps
CPU time 0.85 seconds
Started Mar 28 01:26:08 PM PDT 24
Finished Mar 28 01:26:09 PM PDT 24
Peak memory 197660 kb
Host smart-40e1b87d-2dca-4273-a8be-78358c142977
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75953090 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_wakeup.75953090
Directory /workspace/41.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/41.pwrmgr_wakeup_reset.4198588590
Short name T982
Test name
Test status
Simulation time 740297954 ps
CPU time 1.11 seconds
Started Mar 28 01:26:11 PM PDT 24
Finished Mar 28 01:26:12 PM PDT 24
Peak memory 200384 kb
Host smart-cd167b2c-a00a-47bf-a2ca-fb26b044eae6
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4198588590 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_wakeup_reset.4198588590
Directory /workspace/41.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/42.pwrmgr_aborted_low_power.1854085501
Short name T468
Test name
Test status
Simulation time 32791009 ps
CPU time 1.08 seconds
Started Mar 28 01:26:08 PM PDT 24
Finished Mar 28 01:26:09 PM PDT 24
Peak memory 200068 kb
Host smart-fff63d97-2f37-4dce-93bf-c061044ece4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1854085501 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_aborted_low_power.1854085501
Directory /workspace/42.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/42.pwrmgr_esc_clk_rst_malfunc.4224509260
Short name T832
Test name
Test status
Simulation time 28021741 ps
CPU time 0.66 seconds
Started Mar 28 01:26:08 PM PDT 24
Finished Mar 28 01:26:09 PM PDT 24
Peak memory 197360 kb
Host smart-db464d68-9b9e-4d94-8d87-cd72213d92f7
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4224509260 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_esc_clk_rst
_malfunc.4224509260
Directory /workspace/42.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/42.pwrmgr_escalation_timeout.3261804650
Short name T483
Test name
Test status
Simulation time 687487607 ps
CPU time 0.99 seconds
Started Mar 28 01:26:08 PM PDT 24
Finished Mar 28 01:26:09 PM PDT 24
Peak memory 197732 kb
Host smart-9d4f2d37-5bd0-4e5a-9217-80fdd05dacf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3261804650 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_escalation_timeout.3261804650
Directory /workspace/42.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/42.pwrmgr_glitch.1230648393
Short name T851
Test name
Test status
Simulation time 59680487 ps
CPU time 0.65 seconds
Started Mar 28 01:26:07 PM PDT 24
Finished Mar 28 01:26:08 PM PDT 24
Peak memory 197404 kb
Host smart-6c9c085a-0d89-4474-be0a-48fe5352c76e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1230648393 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_glitch.1230648393
Directory /workspace/42.pwrmgr_glitch/latest

Test location /workspace/coverage/default/42.pwrmgr_global_esc.1814160021
Short name T72
Test name
Test status
Simulation time 46592789 ps
CPU time 0.68 seconds
Started Mar 28 01:26:11 PM PDT 24
Finished Mar 28 01:26:12 PM PDT 24
Peak memory 197332 kb
Host smart-754b9921-e1a9-4ec1-82fd-9c683c0485a9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1814160021 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_global_esc.1814160021
Directory /workspace/42.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/42.pwrmgr_lowpower_invalid.1135815757
Short name T526
Test name
Test status
Simulation time 73053746 ps
CPU time 0.68 seconds
Started Mar 28 01:26:15 PM PDT 24
Finished Mar 28 01:26:16 PM PDT 24
Peak memory 200748 kb
Host smart-86a24166-1d60-49ab-b948-c8e1eae61482
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1135815757 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_lowpower_inval
id.1135815757
Directory /workspace/42.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/42.pwrmgr_lowpower_wakeup_race.1837915628
Short name T968
Test name
Test status
Simulation time 112939384 ps
CPU time 0.69 seconds
Started Mar 28 01:26:08 PM PDT 24
Finished Mar 28 01:26:09 PM PDT 24
Peak memory 197676 kb
Host smart-996c3d26-3ac9-46d1-80dc-034ba7ad2e0b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1837915628 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_lowpower_w
akeup_race.1837915628
Directory /workspace/42.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/42.pwrmgr_reset.3033969507
Short name T429
Test name
Test status
Simulation time 153424446 ps
CPU time 0.88 seconds
Started Mar 28 01:26:08 PM PDT 24
Finished Mar 28 01:26:09 PM PDT 24
Peak memory 199332 kb
Host smart-2f64da40-9390-4801-8c8e-bd65b6aa5341
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3033969507 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_reset.3033969507
Directory /workspace/42.pwrmgr_reset/latest

Test location /workspace/coverage/default/42.pwrmgr_reset_invalid.3873724303
Short name T593
Test name
Test status
Simulation time 297028301 ps
CPU time 0.78 seconds
Started Mar 28 01:26:08 PM PDT 24
Finished Mar 28 01:26:08 PM PDT 24
Peak memory 208820 kb
Host smart-3eb0b34f-6230-40fe-926c-3cece37fc412
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3873724303 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_reset_invalid.3873724303
Directory /workspace/42.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/42.pwrmgr_sec_cm_ctrl_config_regwen.1691045787
Short name T374
Test name
Test status
Simulation time 126203360 ps
CPU time 0.8 seconds
Started Mar 28 01:26:08 PM PDT 24
Finished Mar 28 01:26:08 PM PDT 24
Peak memory 198004 kb
Host smart-66b4720c-7602-4d62-99b9-bf82e3467fc3
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1691045787 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_sec_
cm_ctrl_config_regwen.1691045787
Directory /workspace/42.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/42.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.455572491
Short name T803
Test name
Test status
Simulation time 808921138 ps
CPU time 2.8 seconds
Started Mar 28 01:26:10 PM PDT 24
Finished Mar 28 01:26:13 PM PDT 24
Peak memory 200436 kb
Host smart-b9d63d16-8108-4cb2-aa8d-498d50bba045
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=455572491 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 42.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.455572491
Directory /workspace/42.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/42.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.4005805207
Short name T822
Test name
Test status
Simulation time 1170950600 ps
CPU time 2.4 seconds
Started Mar 28 01:26:11 PM PDT 24
Finished Mar 28 01:26:14 PM PDT 24
Peak memory 200520 kb
Host smart-9b7eef1a-2391-4bc3-89ae-f5236b202e58
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4005805207 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 42.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.4005805207
Directory /workspace/42.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/42.pwrmgr_sec_cm_rstmgr_intersig_mubi.798151832
Short name T651
Test name
Test status
Simulation time 65262243 ps
CPU time 0.91 seconds
Started Mar 28 01:26:09 PM PDT 24
Finished Mar 28 01:26:10 PM PDT 24
Peak memory 198680 kb
Host smart-1efe8996-ae69-4414-a0d2-b6161021d661
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=798151832 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_sec_cm_rstmgr_intersig_
mubi.798151832
Directory /workspace/42.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/42.pwrmgr_smoke.1483786974
Short name T300
Test name
Test status
Simulation time 69775701 ps
CPU time 0.66 seconds
Started Mar 28 01:26:10 PM PDT 24
Finished Mar 28 01:26:10 PM PDT 24
Peak memory 197780 kb
Host smart-d578eee0-2ea7-4505-89d6-bc6b56f818c2
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1483786974 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_smoke.1483786974
Directory /workspace/42.pwrmgr_smoke/latest

Test location /workspace/coverage/default/42.pwrmgr_stress_all.2004551231
Short name T865
Test name
Test status
Simulation time 296830418 ps
CPU time 1.59 seconds
Started Mar 28 01:26:15 PM PDT 24
Finished Mar 28 01:26:17 PM PDT 24
Peak memory 200320 kb
Host smart-244ba787-dc33-4aa1-ac64-36394deebccf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2004551231 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_stress_all.2004551231
Directory /workspace/42.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/42.pwrmgr_stress_all_with_rand_reset.1062453973
Short name T58
Test name
Test status
Simulation time 9542750046 ps
CPU time 30.62 seconds
Started Mar 28 01:26:14 PM PDT 24
Finished Mar 28 01:26:46 PM PDT 24
Peak memory 200664 kb
Host smart-ef226ca5-9e12-43db-9016-8d51d2c6b3aa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1062453973 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 42.pwrmgr_stress_all_with_rand_reset.1062453973
Directory /workspace/42.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.pwrmgr_wakeup.32566878
Short name T904
Test name
Test status
Simulation time 30303214 ps
CPU time 0.71 seconds
Started Mar 28 01:26:14 PM PDT 24
Finished Mar 28 01:26:15 PM PDT 24
Peak memory 197496 kb
Host smart-43589adc-f025-4213-84af-600841d91547
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32566878 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_wakeup.32566878
Directory /workspace/42.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/42.pwrmgr_wakeup_reset.3814943033
Short name T720
Test name
Test status
Simulation time 134163867 ps
CPU time 0.92 seconds
Started Mar 28 01:26:05 PM PDT 24
Finished Mar 28 01:26:06 PM PDT 24
Peak memory 198556 kb
Host smart-1b19d1a4-9604-46ed-870d-6ce4d7f369e3
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3814943033 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_wakeup_reset.3814943033
Directory /workspace/42.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/43.pwrmgr_aborted_low_power.2351293574
Short name T491
Test name
Test status
Simulation time 80153069 ps
CPU time 0.7 seconds
Started Mar 28 01:26:20 PM PDT 24
Finished Mar 28 01:26:21 PM PDT 24
Peak memory 198456 kb
Host smart-23faa971-ddfd-4f52-9ebd-1bb43f87b858
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2351293574 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_aborted_low_power.2351293574
Directory /workspace/43.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/43.pwrmgr_disable_rom_integrity_check.1803748463
Short name T675
Test name
Test status
Simulation time 82675051 ps
CPU time 0.68 seconds
Started Mar 28 01:26:28 PM PDT 24
Finished Mar 28 01:26:28 PM PDT 24
Peak memory 198484 kb
Host smart-949d69f1-ed95-4dea-81b2-b870e708747c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1803748463 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_dis
able_rom_integrity_check.1803748463
Directory /workspace/43.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/43.pwrmgr_esc_clk_rst_malfunc.3367959207
Short name T278
Test name
Test status
Simulation time 41746575 ps
CPU time 0.59 seconds
Started Mar 28 01:26:22 PM PDT 24
Finished Mar 28 01:26:22 PM PDT 24
Peak memory 197352 kb
Host smart-4288fbea-2279-435a-bf33-e77baaf354db
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3367959207 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_esc_clk_rst
_malfunc.3367959207
Directory /workspace/43.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/43.pwrmgr_escalation_timeout.1903805554
Short name T679
Test name
Test status
Simulation time 644818987 ps
CPU time 0.99 seconds
Started Mar 28 01:26:28 PM PDT 24
Finished Mar 28 01:26:29 PM PDT 24
Peak memory 197436 kb
Host smart-960f0c53-5292-4bc8-a753-b9887f41f832
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1903805554 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_escalation_timeout.1903805554
Directory /workspace/43.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/43.pwrmgr_glitch.3888055720
Short name T193
Test name
Test status
Simulation time 62293281 ps
CPU time 0.69 seconds
Started Mar 28 01:26:18 PM PDT 24
Finished Mar 28 01:26:19 PM PDT 24
Peak memory 197392 kb
Host smart-d1616762-fd0f-4335-93e8-07b88a41dfc2
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3888055720 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_glitch.3888055720
Directory /workspace/43.pwrmgr_glitch/latest

Test location /workspace/coverage/default/43.pwrmgr_global_esc.2041988584
Short name T954
Test name
Test status
Simulation time 31445718 ps
CPU time 0.61 seconds
Started Mar 28 01:26:21 PM PDT 24
Finished Mar 28 01:26:22 PM PDT 24
Peak memory 197436 kb
Host smart-779bf0fd-d557-4432-a3ce-31620050405b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2041988584 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_global_esc.2041988584
Directory /workspace/43.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/43.pwrmgr_lowpower_invalid.1284805552
Short name T855
Test name
Test status
Simulation time 52009172 ps
CPU time 0.68 seconds
Started Mar 28 01:26:29 PM PDT 24
Finished Mar 28 01:26:30 PM PDT 24
Peak memory 200740 kb
Host smart-c5c52b88-8179-4872-9fdb-01bc1af659b1
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1284805552 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_lowpower_inval
id.1284805552
Directory /workspace/43.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/43.pwrmgr_reset.1527059863
Short name T927
Test name
Test status
Simulation time 129837738 ps
CPU time 0.85 seconds
Started Mar 28 01:26:14 PM PDT 24
Finished Mar 28 01:26:16 PM PDT 24
Peak memory 199192 kb
Host smart-57754202-78e5-4df6-b7a2-a508ad43a21b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1527059863 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_reset.1527059863
Directory /workspace/43.pwrmgr_reset/latest

Test location /workspace/coverage/default/43.pwrmgr_reset_invalid.3215539934
Short name T837
Test name
Test status
Simulation time 252559432 ps
CPU time 0.8 seconds
Started Mar 28 01:26:25 PM PDT 24
Finished Mar 28 01:26:27 PM PDT 24
Peak memory 208768 kb
Host smart-a563de76-daec-48e2-a676-d0ac6712bab4
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3215539934 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_reset_invalid.3215539934
Directory /workspace/43.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/43.pwrmgr_sec_cm_ctrl_config_regwen.1470296307
Short name T420
Test name
Test status
Simulation time 103059948 ps
CPU time 0.8 seconds
Started Mar 28 01:26:24 PM PDT 24
Finished Mar 28 01:26:24 PM PDT 24
Peak memory 197924 kb
Host smart-ecab379d-c898-4030-b627-6e128a54c348
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1470296307 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_sec_
cm_ctrl_config_regwen.1470296307
Directory /workspace/43.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/43.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.12019341
Short name T931
Test name
Test status
Simulation time 974166652 ps
CPU time 2.5 seconds
Started Mar 28 01:26:26 PM PDT 24
Finished Mar 28 01:26:28 PM PDT 24
Peak memory 200512 kb
Host smart-cd1c98fe-55c9-4acd-9022-0d8ccf879395
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12019341 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +
UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 43.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.12019341
Directory /workspace/43.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/43.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.181624888
Short name T595
Test name
Test status
Simulation time 957073347 ps
CPU time 2.01 seconds
Started Mar 28 01:26:27 PM PDT 24
Finished Mar 28 01:26:29 PM PDT 24
Peak memory 200536 kb
Host smart-6c7f2bff-9e6b-4633-b0cf-e46b6174d930
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=181624888 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 43.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.181624888
Directory /workspace/43.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/43.pwrmgr_sec_cm_rstmgr_intersig_mubi.3636798379
Short name T305
Test name
Test status
Simulation time 300815517 ps
CPU time 0.86 seconds
Started Mar 28 01:26:31 PM PDT 24
Finished Mar 28 01:26:33 PM PDT 24
Peak memory 198356 kb
Host smart-99ade65d-69ab-4dc1-ae43-b58b31e6fb27
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3636798379 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_sec_cm_rstmgr_intersig
_mubi.3636798379
Directory /workspace/43.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/43.pwrmgr_smoke.4249347601
Short name T156
Test name
Test status
Simulation time 35873329 ps
CPU time 0.68 seconds
Started Mar 28 01:26:15 PM PDT 24
Finished Mar 28 01:26:16 PM PDT 24
Peak memory 198680 kb
Host smart-31632264-ebb0-4677-a1a4-603d4baa2ff3
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4249347601 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_smoke.4249347601
Directory /workspace/43.pwrmgr_smoke/latest

Test location /workspace/coverage/default/43.pwrmgr_stress_all.3482643583
Short name T644
Test name
Test status
Simulation time 1236194371 ps
CPU time 5.73 seconds
Started Mar 28 01:26:32 PM PDT 24
Finished Mar 28 01:26:38 PM PDT 24
Peak memory 200476 kb
Host smart-b895534d-36cd-4ac8-8741-c537d3599aba
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3482643583 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_stress_all.3482643583
Directory /workspace/43.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/43.pwrmgr_wakeup.4036253296
Short name T384
Test name
Test status
Simulation time 71982135 ps
CPU time 0.69 seconds
Started Mar 28 01:26:15 PM PDT 24
Finished Mar 28 01:26:16 PM PDT 24
Peak memory 198448 kb
Host smart-f01a71d5-28ee-4db3-8e17-3f902cb8c339
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4036253296 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_wakeup.4036253296
Directory /workspace/43.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/43.pwrmgr_wakeup_reset.2094264177
Short name T812
Test name
Test status
Simulation time 111456793 ps
CPU time 0.86 seconds
Started Mar 28 01:26:08 PM PDT 24
Finished Mar 28 01:26:09 PM PDT 24
Peak memory 198688 kb
Host smart-307194a5-af9a-4c78-9a8f-724aab7d2b78
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2094264177 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_wakeup_reset.2094264177
Directory /workspace/43.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/44.pwrmgr_aborted_low_power.2149942272
Short name T560
Test name
Test status
Simulation time 93751425 ps
CPU time 0.68 seconds
Started Mar 28 01:26:21 PM PDT 24
Finished Mar 28 01:26:22 PM PDT 24
Peak memory 198020 kb
Host smart-b0766692-63e3-44b0-8f44-460e9c26e4e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2149942272 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_aborted_low_power.2149942272
Directory /workspace/44.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/44.pwrmgr_disable_rom_integrity_check.1958957337
Short name T337
Test name
Test status
Simulation time 61205807 ps
CPU time 0.89 seconds
Started Mar 28 01:26:28 PM PDT 24
Finished Mar 28 01:26:29 PM PDT 24
Peak memory 198456 kb
Host smart-2b4116c7-f65e-422a-89ae-d1903220270e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1958957337 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_dis
able_rom_integrity_check.1958957337
Directory /workspace/44.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/44.pwrmgr_esc_clk_rst_malfunc.1369209303
Short name T386
Test name
Test status
Simulation time 29682499 ps
CPU time 0.66 seconds
Started Mar 28 01:26:30 PM PDT 24
Finished Mar 28 01:26:30 PM PDT 24
Peak memory 196672 kb
Host smart-ccd8d22c-6937-4a41-885f-c0d1de777421
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1369209303 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_esc_clk_rst
_malfunc.1369209303
Directory /workspace/44.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/44.pwrmgr_escalation_timeout.3570161035
Short name T648
Test name
Test status
Simulation time 617419737 ps
CPU time 1 seconds
Started Mar 28 01:26:19 PM PDT 24
Finished Mar 28 01:26:21 PM PDT 24
Peak memory 197392 kb
Host smart-01ca9686-83ce-42b0-bdb2-3e9b62cf25ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3570161035 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_escalation_timeout.3570161035
Directory /workspace/44.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/44.pwrmgr_glitch.2394532559
Short name T187
Test name
Test status
Simulation time 62681080 ps
CPU time 0.65 seconds
Started Mar 28 01:26:21 PM PDT 24
Finished Mar 28 01:26:22 PM PDT 24
Peak memory 197392 kb
Host smart-cd285b01-d07c-43c3-9f77-59f61cdcc086
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2394532559 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_glitch.2394532559
Directory /workspace/44.pwrmgr_glitch/latest

Test location /workspace/coverage/default/44.pwrmgr_global_esc.1993645152
Short name T438
Test name
Test status
Simulation time 39621204 ps
CPU time 0.64 seconds
Started Mar 28 01:26:21 PM PDT 24
Finished Mar 28 01:26:22 PM PDT 24
Peak memory 197704 kb
Host smart-6dd9aa3b-3906-40b0-8440-2272b51ee377
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1993645152 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_global_esc.1993645152
Directory /workspace/44.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/44.pwrmgr_lowpower_invalid.1354590052
Short name T258
Test name
Test status
Simulation time 47756056 ps
CPU time 0.7 seconds
Started Mar 28 01:26:25 PM PDT 24
Finished Mar 28 01:26:27 PM PDT 24
Peak memory 200764 kb
Host smart-010297a7-14df-491f-87d2-56669e85f0e3
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1354590052 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_lowpower_inval
id.1354590052
Directory /workspace/44.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/44.pwrmgr_lowpower_wakeup_race.218686693
Short name T296
Test name
Test status
Simulation time 185760569 ps
CPU time 1.02 seconds
Started Mar 28 01:26:27 PM PDT 24
Finished Mar 28 01:26:28 PM PDT 24
Peak memory 197792 kb
Host smart-a62fc8d1-f34c-4e99-a76c-26e7d85e9e4f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=218686693 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeu
p_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_lowpower_wa
keup_race.218686693
Directory /workspace/44.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/44.pwrmgr_reset.752025419
Short name T544
Test name
Test status
Simulation time 61580406 ps
CPU time 0.9 seconds
Started Mar 28 01:26:29 PM PDT 24
Finished Mar 28 01:26:30 PM PDT 24
Peak memory 198480 kb
Host smart-5cc50a55-7c82-4101-9092-edd953c0d495
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=752025419 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_reset.752025419
Directory /workspace/44.pwrmgr_reset/latest

Test location /workspace/coverage/default/44.pwrmgr_reset_invalid.2233398792
Short name T891
Test name
Test status
Simulation time 111643746 ps
CPU time 0.88 seconds
Started Mar 28 01:26:20 PM PDT 24
Finished Mar 28 01:26:22 PM PDT 24
Peak memory 208896 kb
Host smart-9eb789a5-1279-450f-9a02-f99e36c36e69
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2233398792 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_reset_invalid.2233398792
Directory /workspace/44.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/44.pwrmgr_sec_cm_ctrl_config_regwen.2259684717
Short name T727
Test name
Test status
Simulation time 267491896 ps
CPU time 1.11 seconds
Started Mar 28 01:26:21 PM PDT 24
Finished Mar 28 01:26:23 PM PDT 24
Peak memory 200212 kb
Host smart-d630eed0-ecbc-44d6-ab0c-b7d332cc8083
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2259684717 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_sec_
cm_ctrl_config_regwen.2259684717
Directory /workspace/44.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/44.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3316339234
Short name T74
Test name
Test status
Simulation time 813260287 ps
CPU time 2.77 seconds
Started Mar 28 01:26:22 PM PDT 24
Finished Mar 28 01:26:25 PM PDT 24
Peak memory 200352 kb
Host smart-4b46b527-1777-4265-be04-82b1f00f31c1
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3316339234 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 44.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3316339234
Directory /workspace/44.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/44.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2951394167
Short name T339
Test name
Test status
Simulation time 978926702 ps
CPU time 2.27 seconds
Started Mar 28 01:26:27 PM PDT 24
Finished Mar 28 01:26:30 PM PDT 24
Peak memory 200520 kb
Host smart-5679d199-e35d-4908-a10c-4ac73f2229d5
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2951394167 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 44.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2951394167
Directory /workspace/44.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/44.pwrmgr_sec_cm_rstmgr_intersig_mubi.785916316
Short name T285
Test name
Test status
Simulation time 91572206 ps
CPU time 0.79 seconds
Started Mar 28 01:26:22 PM PDT 24
Finished Mar 28 01:26:23 PM PDT 24
Peak memory 198500 kb
Host smart-8dba2a79-2a66-4bd0-82d6-e94e16189332
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=785916316 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_sec_cm_rstmgr_intersig_
mubi.785916316
Directory /workspace/44.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/44.pwrmgr_smoke.4082971278
Short name T946
Test name
Test status
Simulation time 30861785 ps
CPU time 0.71 seconds
Started Mar 28 01:26:22 PM PDT 24
Finished Mar 28 01:26:23 PM PDT 24
Peak memory 198548 kb
Host smart-b6ffb965-dcda-49b2-8d23-125c322195b0
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4082971278 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_smoke.4082971278
Directory /workspace/44.pwrmgr_smoke/latest

Test location /workspace/coverage/default/44.pwrmgr_stress_all.239676986
Short name T81
Test name
Test status
Simulation time 1151643548 ps
CPU time 2.51 seconds
Started Mar 28 01:26:18 PM PDT 24
Finished Mar 28 01:26:21 PM PDT 24
Peak memory 200592 kb
Host smart-2b920b09-123f-47af-82dc-663f4a5f0b30
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=239676986 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_stress_all.239676986
Directory /workspace/44.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/44.pwrmgr_stress_all_with_rand_reset.883591657
Short name T612
Test name
Test status
Simulation time 10390432581 ps
CPU time 10.44 seconds
Started Mar 28 01:26:29 PM PDT 24
Finished Mar 28 01:26:39 PM PDT 24
Peak memory 200852 kb
Host smart-ff1a2612-0072-4b0f-8e26-6dddce263927
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=883591657 -assert nopost
proc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 44.pwrmgr_stress_all_with_rand_reset.883591657
Directory /workspace/44.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.pwrmgr_wakeup.1049215717
Short name T718
Test name
Test status
Simulation time 142489429 ps
CPU time 0.74 seconds
Started Mar 28 01:26:31 PM PDT 24
Finished Mar 28 01:26:33 PM PDT 24
Peak memory 197464 kb
Host smart-a031e158-3510-4301-9ebf-5b7daa2e0cb9
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1049215717 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_wakeup.1049215717
Directory /workspace/44.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/44.pwrmgr_wakeup_reset.1778714973
Short name T669
Test name
Test status
Simulation time 357614822 ps
CPU time 1.28 seconds
Started Mar 28 01:26:25 PM PDT 24
Finished Mar 28 01:26:27 PM PDT 24
Peak memory 200336 kb
Host smart-6e92bd5d-57fa-4425-951e-3b7fcab0c024
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1778714973 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_wakeup_reset.1778714973
Directory /workspace/44.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/45.pwrmgr_aborted_low_power.2175379849
Short name T407
Test name
Test status
Simulation time 45359041 ps
CPU time 0.9 seconds
Started Mar 28 01:26:28 PM PDT 24
Finished Mar 28 01:26:29 PM PDT 24
Peak memory 200224 kb
Host smart-bd9fc97d-bdcd-468f-9dac-cbff49f3a4bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2175379849 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_aborted_low_power.2175379849
Directory /workspace/45.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/45.pwrmgr_disable_rom_integrity_check.2300980358
Short name T21
Test name
Test status
Simulation time 65142961 ps
CPU time 0.7 seconds
Started Mar 28 01:26:21 PM PDT 24
Finished Mar 28 01:26:22 PM PDT 24
Peak memory 197844 kb
Host smart-b0126480-4b9b-4386-a1ef-827d51cf5e45
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2300980358 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_dis
able_rom_integrity_check.2300980358
Directory /workspace/45.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/45.pwrmgr_esc_clk_rst_malfunc.4073674536
Short name T330
Test name
Test status
Simulation time 73787006 ps
CPU time 0.59 seconds
Started Mar 28 01:26:29 PM PDT 24
Finished Mar 28 01:26:29 PM PDT 24
Peak memory 197408 kb
Host smart-ebfa2a60-0ab6-4dc9-b411-c21a07fe7eec
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4073674536 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_esc_clk_rst
_malfunc.4073674536
Directory /workspace/45.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/45.pwrmgr_escalation_timeout.3036898965
Short name T447
Test name
Test status
Simulation time 769823092 ps
CPU time 0.96 seconds
Started Mar 28 01:26:31 PM PDT 24
Finished Mar 28 01:26:32 PM PDT 24
Peak memory 197628 kb
Host smart-ce30ce67-7612-456c-95b4-8be093ece48a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3036898965 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_escalation_timeout.3036898965
Directory /workspace/45.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/45.pwrmgr_glitch.870314063
Short name T527
Test name
Test status
Simulation time 24345741 ps
CPU time 0.62 seconds
Started Mar 28 01:26:30 PM PDT 24
Finished Mar 28 01:26:31 PM PDT 24
Peak memory 196780 kb
Host smart-508354b3-5f59-4693-a486-f02e6b9ba28c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=870314063 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_glitch.870314063
Directory /workspace/45.pwrmgr_glitch/latest

Test location /workspace/coverage/default/45.pwrmgr_global_esc.3725777281
Short name T519
Test name
Test status
Simulation time 55939902 ps
CPU time 0.61 seconds
Started Mar 28 01:26:21 PM PDT 24
Finished Mar 28 01:26:22 PM PDT 24
Peak memory 197400 kb
Host smart-bfa36d5c-b241-41d2-9ac0-97282ebeab50
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3725777281 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_global_esc.3725777281
Directory /workspace/45.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/45.pwrmgr_lowpower_invalid.1374621050
Short name T477
Test name
Test status
Simulation time 44937235 ps
CPU time 0.77 seconds
Started Mar 28 01:26:33 PM PDT 24
Finished Mar 28 01:26:34 PM PDT 24
Peak memory 200748 kb
Host smart-5882cc7a-bf0d-46e8-bb7d-6ccaa5c84e70
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1374621050 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_lowpower_inval
id.1374621050
Directory /workspace/45.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/45.pwrmgr_lowpower_wakeup_race.2265799980
Short name T1
Test name
Test status
Simulation time 31748171 ps
CPU time 0.64 seconds
Started Mar 28 01:26:25 PM PDT 24
Finished Mar 28 01:26:25 PM PDT 24
Peak memory 197592 kb
Host smart-7605f9f6-0a38-44e8-811c-69691e23da71
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2265799980 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_lowpower_w
akeup_race.2265799980
Directory /workspace/45.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/45.pwrmgr_reset.2642926843
Short name T556
Test name
Test status
Simulation time 67356288 ps
CPU time 0.79 seconds
Started Mar 28 01:26:23 PM PDT 24
Finished Mar 28 01:26:24 PM PDT 24
Peak memory 197476 kb
Host smart-8262286c-912b-42f3-ac1b-586df14dfd82
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2642926843 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_reset.2642926843
Directory /workspace/45.pwrmgr_reset/latest

Test location /workspace/coverage/default/45.pwrmgr_reset_invalid.2995262440
Short name T484
Test name
Test status
Simulation time 97520005 ps
CPU time 0.88 seconds
Started Mar 28 01:26:21 PM PDT 24
Finished Mar 28 01:26:22 PM PDT 24
Peak memory 208832 kb
Host smart-818ff8d8-e7f2-434f-8e9c-da1efe2456fc
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2995262440 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_reset_invalid.2995262440
Directory /workspace/45.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/45.pwrmgr_sec_cm_ctrl_config_regwen.1712969737
Short name T853
Test name
Test status
Simulation time 144044201 ps
CPU time 1.01 seconds
Started Mar 28 01:26:18 PM PDT 24
Finished Mar 28 01:26:20 PM PDT 24
Peak memory 199344 kb
Host smart-3b0146ea-011b-43d0-a2ae-5c1bfcfcea4f
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1712969737 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_sec_
cm_ctrl_config_regwen.1712969737
Directory /workspace/45.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/45.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.246420271
Short name T782
Test name
Test status
Simulation time 1138254461 ps
CPU time 2.27 seconds
Started Mar 28 01:26:22 PM PDT 24
Finished Mar 28 01:26:25 PM PDT 24
Peak memory 200432 kb
Host smart-e807cdc8-6ecf-4208-af93-fe32cb60636d
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=246420271 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 45.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.246420271
Directory /workspace/45.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/45.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2215363677
Short name T265
Test name
Test status
Simulation time 908850973 ps
CPU time 3.39 seconds
Started Mar 28 01:26:29 PM PDT 24
Finished Mar 28 01:26:32 PM PDT 24
Peak memory 200480 kb
Host smart-bc758b73-0f48-47d6-8940-8c7c4c1658a0
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2215363677 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 45.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2215363677
Directory /workspace/45.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/45.pwrmgr_sec_cm_rstmgr_intersig_mubi.173985720
Short name T564
Test name
Test status
Simulation time 51904455 ps
CPU time 0.91 seconds
Started Mar 28 01:26:22 PM PDT 24
Finished Mar 28 01:26:23 PM PDT 24
Peak memory 198408 kb
Host smart-7db32e1f-c233-4515-9011-75be24ee31f0
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=173985720 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_sec_cm_rstmgr_intersig_
mubi.173985720
Directory /workspace/45.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/45.pwrmgr_smoke.2084525837
Short name T761
Test name
Test status
Simulation time 77697999 ps
CPU time 0.67 seconds
Started Mar 28 01:26:25 PM PDT 24
Finished Mar 28 01:26:25 PM PDT 24
Peak memory 197852 kb
Host smart-22162b5e-d066-47fc-aa90-11e34d8b3b95
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2084525837 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_smoke.2084525837
Directory /workspace/45.pwrmgr_smoke/latest

Test location /workspace/coverage/default/45.pwrmgr_stress_all.1174873067
Short name T398
Test name
Test status
Simulation time 1161569743 ps
CPU time 5.78 seconds
Started Mar 28 01:26:23 PM PDT 24
Finished Mar 28 01:26:29 PM PDT 24
Peak memory 200304 kb
Host smart-3e6520ca-42b6-4b49-9cae-481bc545dc22
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1174873067 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_stress_all.1174873067
Directory /workspace/45.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/45.pwrmgr_stress_all_with_rand_reset.3575835469
Short name T878
Test name
Test status
Simulation time 8813876281 ps
CPU time 32.94 seconds
Started Mar 28 01:26:23 PM PDT 24
Finished Mar 28 01:26:56 PM PDT 24
Peak memory 200460 kb
Host smart-d22ad62a-5610-4f00-b7ff-42662dfaf7d9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3575835469 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 45.pwrmgr_stress_all_with_rand_reset.3575835469
Directory /workspace/45.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.pwrmgr_wakeup.2699258902
Short name T454
Test name
Test status
Simulation time 274955166 ps
CPU time 0.9 seconds
Started Mar 28 01:26:21 PM PDT 24
Finished Mar 28 01:26:22 PM PDT 24
Peak memory 199052 kb
Host smart-c1d6fd77-5656-46b1-8cdc-e604e4cd6684
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2699258902 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_wakeup.2699258902
Directory /workspace/45.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/45.pwrmgr_wakeup_reset.3100476860
Short name T969
Test name
Test status
Simulation time 336667694 ps
CPU time 1.36 seconds
Started Mar 28 01:26:29 PM PDT 24
Finished Mar 28 01:26:31 PM PDT 24
Peak memory 200440 kb
Host smart-959080ba-e0c2-410c-80ae-cec6c4f1becf
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3100476860 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_wakeup_reset.3100476860
Directory /workspace/45.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/46.pwrmgr_aborted_low_power.3863185319
Short name T346
Test name
Test status
Simulation time 143760018 ps
CPU time 0.93 seconds
Started Mar 28 01:26:24 PM PDT 24
Finished Mar 28 01:26:25 PM PDT 24
Peak memory 200212 kb
Host smart-b67c73b2-9566-4e60-a0e3-587d7a21e892
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3863185319 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_aborted_low_power.3863185319
Directory /workspace/46.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/46.pwrmgr_disable_rom_integrity_check.1754376040
Short name T600
Test name
Test status
Simulation time 67727432 ps
CPU time 0.77 seconds
Started Mar 28 01:26:24 PM PDT 24
Finished Mar 28 01:26:25 PM PDT 24
Peak memory 198456 kb
Host smart-4fafac15-2ffa-48bb-a033-bc0eaa741ac0
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1754376040 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_dis
able_rom_integrity_check.1754376040
Directory /workspace/46.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/46.pwrmgr_esc_clk_rst_malfunc.105522792
Short name T785
Test name
Test status
Simulation time 31777069 ps
CPU time 0.64 seconds
Started Mar 28 01:26:30 PM PDT 24
Finished Mar 28 01:26:31 PM PDT 24
Peak memory 197356 kb
Host smart-886ac638-92c9-4a9f-af8d-15d06bade652
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105522792 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_ma
lfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_esc_clk_rst_
malfunc.105522792
Directory /workspace/46.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/46.pwrmgr_escalation_timeout.4049980330
Short name T378
Test name
Test status
Simulation time 161632476 ps
CPU time 1.03 seconds
Started Mar 28 01:26:25 PM PDT 24
Finished Mar 28 01:26:26 PM PDT 24
Peak memory 197772 kb
Host smart-32ac3f89-6183-42bf-9087-fb32562b55c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4049980330 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_escalation_timeout.4049980330
Directory /workspace/46.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/46.pwrmgr_glitch.296151183
Short name T14
Test name
Test status
Simulation time 55921065 ps
CPU time 0.7 seconds
Started Mar 28 01:26:25 PM PDT 24
Finished Mar 28 01:26:27 PM PDT 24
Peak memory 197396 kb
Host smart-53aa48d7-ff2d-4ad2-8b77-b4644fb482d5
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=296151183 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_glitch.296151183
Directory /workspace/46.pwrmgr_glitch/latest

Test location /workspace/coverage/default/46.pwrmgr_global_esc.1125163890
Short name T958
Test name
Test status
Simulation time 45184495 ps
CPU time 0.65 seconds
Started Mar 28 01:26:28 PM PDT 24
Finished Mar 28 01:26:29 PM PDT 24
Peak memory 197744 kb
Host smart-d3e54f74-8436-4b8c-bd7c-3f8054cb42f5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1125163890 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_global_esc.1125163890
Directory /workspace/46.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/46.pwrmgr_lowpower_invalid.1567208275
Short name T505
Test name
Test status
Simulation time 43156758 ps
CPU time 0.72 seconds
Started Mar 28 01:26:30 PM PDT 24
Finished Mar 28 01:26:31 PM PDT 24
Peak memory 200728 kb
Host smart-edabb3f2-d7dd-45a8-831e-3ff55662975c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1567208275 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_lowpower_inval
id.1567208275
Directory /workspace/46.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/46.pwrmgr_lowpower_wakeup_race.2209958682
Short name T703
Test name
Test status
Simulation time 252798620 ps
CPU time 1.19 seconds
Started Mar 28 01:26:31 PM PDT 24
Finished Mar 28 01:26:32 PM PDT 24
Peak memory 198836 kb
Host smart-f00acc61-0030-4ca4-a98e-1b5572ba0404
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2209958682 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_lowpower_w
akeup_race.2209958682
Directory /workspace/46.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/46.pwrmgr_reset.1981371514
Short name T208
Test name
Test status
Simulation time 44864854 ps
CPU time 0.63 seconds
Started Mar 28 01:26:30 PM PDT 24
Finished Mar 28 01:26:30 PM PDT 24
Peak memory 198476 kb
Host smart-69019e06-b4e8-45d2-a609-d8891db93459
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1981371514 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_reset.1981371514
Directory /workspace/46.pwrmgr_reset/latest

Test location /workspace/coverage/default/46.pwrmgr_reset_invalid.1402778536
Short name T475
Test name
Test status
Simulation time 109597968 ps
CPU time 1 seconds
Started Mar 28 01:26:30 PM PDT 24
Finished Mar 28 01:26:32 PM PDT 24
Peak memory 208828 kb
Host smart-114737ac-0f36-47b4-a67d-7d517576f7ea
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1402778536 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_reset_invalid.1402778536
Directory /workspace/46.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/46.pwrmgr_sec_cm_ctrl_config_regwen.1339677648
Short name T4
Test name
Test status
Simulation time 223545942 ps
CPU time 0.87 seconds
Started Mar 28 01:26:30 PM PDT 24
Finished Mar 28 01:26:31 PM PDT 24
Peak memory 198988 kb
Host smart-bf8df0db-5471-4bbc-beb3-466a379eb415
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1339677648 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_sec_
cm_ctrl_config_regwen.1339677648
Directory /workspace/46.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/46.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.751271931
Short name T489
Test name
Test status
Simulation time 900646569 ps
CPU time 2.69 seconds
Started Mar 28 01:26:26 PM PDT 24
Finished Mar 28 01:26:29 PM PDT 24
Peak memory 200416 kb
Host smart-a5f07d7c-0e46-4b3a-84f5-a34a5d6de826
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=751271931 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 46.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.751271931
Directory /workspace/46.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/46.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3770559075
Short name T29
Test name
Test status
Simulation time 1211319850 ps
CPU time 2.18 seconds
Started Mar 28 01:26:26 PM PDT 24
Finished Mar 28 01:26:29 PM PDT 24
Peak memory 200552 kb
Host smart-e634e8df-b357-4c96-99c8-fbd43a86ca99
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3770559075 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 46.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3770559075
Directory /workspace/46.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/46.pwrmgr_sec_cm_rstmgr_intersig_mubi.1593751262
Short name T714
Test name
Test status
Simulation time 77033505 ps
CPU time 0.97 seconds
Started Mar 28 01:26:26 PM PDT 24
Finished Mar 28 01:26:28 PM PDT 24
Peak memory 199036 kb
Host smart-6ee4c63a-44ec-42cc-b1f3-f337540a3849
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1593751262 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_sec_cm_rstmgr_intersig
_mubi.1593751262
Directory /workspace/46.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/46.pwrmgr_smoke.1813769980
Short name T862
Test name
Test status
Simulation time 30690218 ps
CPU time 0.65 seconds
Started Mar 28 01:26:23 PM PDT 24
Finished Mar 28 01:26:24 PM PDT 24
Peak memory 198568 kb
Host smart-bffc4287-6b5d-43e7-b1eb-445f976cb3bf
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1813769980 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_smoke.1813769980
Directory /workspace/46.pwrmgr_smoke/latest

Test location /workspace/coverage/default/46.pwrmgr_stress_all.1915861719
Short name T694
Test name
Test status
Simulation time 1503934432 ps
CPU time 2.67 seconds
Started Mar 28 01:26:30 PM PDT 24
Finished Mar 28 01:26:34 PM PDT 24
Peak memory 200512 kb
Host smart-bcdf3ad0-9d20-4948-a22f-df463008590f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1915861719 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_stress_all.1915861719
Directory /workspace/46.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/46.pwrmgr_wakeup.4161234923
Short name T900
Test name
Test status
Simulation time 314518357 ps
CPU time 0.97 seconds
Started Mar 28 01:26:25 PM PDT 24
Finished Mar 28 01:26:27 PM PDT 24
Peak memory 199072 kb
Host smart-0be26c1d-02a0-407c-8866-4e6ba9c2e788
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4161234923 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_wakeup.4161234923
Directory /workspace/46.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/46.pwrmgr_wakeup_reset.3085489497
Short name T906
Test name
Test status
Simulation time 302671129 ps
CPU time 0.92 seconds
Started Mar 28 01:26:19 PM PDT 24
Finished Mar 28 01:26:20 PM PDT 24
Peak memory 199372 kb
Host smart-9ca9a13c-3e43-4d75-8659-68ccb1abaeb7
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3085489497 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_wakeup_reset.3085489497
Directory /workspace/46.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/47.pwrmgr_aborted_low_power.2700948368
Short name T385
Test name
Test status
Simulation time 154539836 ps
CPU time 0.79 seconds
Started Mar 28 01:26:30 PM PDT 24
Finished Mar 28 01:26:31 PM PDT 24
Peak memory 199112 kb
Host smart-cf5c938f-187e-4fb3-ac64-381c648a486f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2700948368 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_aborted_low_power.2700948368
Directory /workspace/47.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/47.pwrmgr_disable_rom_integrity_check.2235758032
Short name T956
Test name
Test status
Simulation time 70000008 ps
CPU time 0.67 seconds
Started Mar 28 01:26:28 PM PDT 24
Finished Mar 28 01:26:29 PM PDT 24
Peak memory 198556 kb
Host smart-16f85f6b-0d6d-4af4-8ad9-d4e906fd5b0a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2235758032 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_dis
able_rom_integrity_check.2235758032
Directory /workspace/47.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/47.pwrmgr_esc_clk_rst_malfunc.4031760919
Short name T673
Test name
Test status
Simulation time 29469028 ps
CPU time 0.62 seconds
Started Mar 28 01:26:26 PM PDT 24
Finished Mar 28 01:26:27 PM PDT 24
Peak memory 196608 kb
Host smart-897216e8-71d8-4465-9cbd-e8b6804abc9e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4031760919 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_esc_clk_rst
_malfunc.4031760919
Directory /workspace/47.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/47.pwrmgr_escalation_timeout.2994407936
Short name T928
Test name
Test status
Simulation time 605338099 ps
CPU time 0.92 seconds
Started Mar 28 01:26:32 PM PDT 24
Finished Mar 28 01:26:34 PM PDT 24
Peak memory 197468 kb
Host smart-753292c4-d8d4-4ec5-bf8e-8d78b58622cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2994407936 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_escalation_timeout.2994407936
Directory /workspace/47.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/47.pwrmgr_glitch.2917158503
Short name T131
Test name
Test status
Simulation time 89734390 ps
CPU time 0.6 seconds
Started Mar 28 01:26:30 PM PDT 24
Finished Mar 28 01:26:31 PM PDT 24
Peak memory 197508 kb
Host smart-4d27c1fb-648d-499c-b914-4975688f21ce
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2917158503 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_glitch.2917158503
Directory /workspace/47.pwrmgr_glitch/latest

Test location /workspace/coverage/default/47.pwrmgr_global_esc.2615891168
Short name T436
Test name
Test status
Simulation time 34666246 ps
CPU time 0.63 seconds
Started Mar 28 01:26:33 PM PDT 24
Finished Mar 28 01:26:34 PM PDT 24
Peak memory 197436 kb
Host smart-61f0cfb4-31f9-452d-832c-67a737750d92
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2615891168 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_global_esc.2615891168
Directory /workspace/47.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/47.pwrmgr_lowpower_invalid.4160745757
Short name T660
Test name
Test status
Simulation time 72197751 ps
CPU time 0.7 seconds
Started Mar 28 01:26:34 PM PDT 24
Finished Mar 28 01:26:35 PM PDT 24
Peak memory 200740 kb
Host smart-f0824f8a-0d44-4ad7-9dd9-801008032bd2
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4160745757 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_lowpower_inval
id.4160745757
Directory /workspace/47.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/47.pwrmgr_lowpower_wakeup_race.1150715875
Short name T874
Test name
Test status
Simulation time 180752740 ps
CPU time 1.08 seconds
Started Mar 28 01:26:30 PM PDT 24
Finished Mar 28 01:26:31 PM PDT 24
Peak memory 198840 kb
Host smart-c8e7183d-0e51-4712-90d5-8c6d0d036eaf
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1150715875 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_lowpower_w
akeup_race.1150715875
Directory /workspace/47.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/47.pwrmgr_reset.4166788939
Short name T188
Test name
Test status
Simulation time 39837005 ps
CPU time 0.77 seconds
Started Mar 28 01:26:25 PM PDT 24
Finished Mar 28 01:26:27 PM PDT 24
Peak memory 198060 kb
Host smart-7efa5a27-0f18-456d-ba67-e0a8f97b759c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4166788939 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_reset.4166788939
Directory /workspace/47.pwrmgr_reset/latest

Test location /workspace/coverage/default/47.pwrmgr_reset_invalid.1225496254
Short name T460
Test name
Test status
Simulation time 102311317 ps
CPU time 1.08 seconds
Started Mar 28 01:26:33 PM PDT 24
Finished Mar 28 01:26:34 PM PDT 24
Peak memory 208808 kb
Host smart-bad9ca9e-2a2b-4c30-893c-9b80071a7847
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1225496254 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_reset_invalid.1225496254
Directory /workspace/47.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/47.pwrmgr_sec_cm_ctrl_config_regwen.1991700380
Short name T938
Test name
Test status
Simulation time 96148793 ps
CPU time 0.79 seconds
Started Mar 28 01:26:33 PM PDT 24
Finished Mar 28 01:26:34 PM PDT 24
Peak memory 198432 kb
Host smart-028001b0-fbb3-4c6b-9044-5613928f34b0
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1991700380 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_sec_
cm_ctrl_config_regwen.1991700380
Directory /workspace/47.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/47.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2052636610
Short name T643
Test name
Test status
Simulation time 1051459523 ps
CPU time 2.43 seconds
Started Mar 28 01:26:29 PM PDT 24
Finished Mar 28 01:26:32 PM PDT 24
Peak memory 200576 kb
Host smart-2b696017-81dc-4bd1-8ade-5a5d4905a1a3
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2052636610 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 47.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2052636610
Directory /workspace/47.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/47.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.4081224634
Short name T845
Test name
Test status
Simulation time 2513926344 ps
CPU time 2.15 seconds
Started Mar 28 01:26:33 PM PDT 24
Finished Mar 28 01:26:35 PM PDT 24
Peak memory 200716 kb
Host smart-14c93537-bc9b-4db2-b688-f769866d5b59
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4081224634 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 47.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.4081224634
Directory /workspace/47.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/47.pwrmgr_sec_cm_rstmgr_intersig_mubi.1976655412
Short name T6
Test name
Test status
Simulation time 89888283 ps
CPU time 0.79 seconds
Started Mar 28 01:26:29 PM PDT 24
Finished Mar 28 01:26:30 PM PDT 24
Peak memory 198440 kb
Host smart-45c7360c-efbf-49ed-a5d4-5d59e91fc246
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1976655412 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_sec_cm_rstmgr_intersig
_mubi.1976655412
Directory /workspace/47.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/47.pwrmgr_smoke.665575638
Short name T431
Test name
Test status
Simulation time 73123404 ps
CPU time 0.66 seconds
Started Mar 28 01:26:26 PM PDT 24
Finished Mar 28 01:26:27 PM PDT 24
Peak memory 197848 kb
Host smart-3c486aa5-672c-49b4-9999-049d73891dd2
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=665575638 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_smoke.665575638
Directory /workspace/47.pwrmgr_smoke/latest

Test location /workspace/coverage/default/47.pwrmgr_stress_all.3794636778
Short name T240
Test name
Test status
Simulation time 1934593327 ps
CPU time 4.81 seconds
Started Mar 28 01:26:34 PM PDT 24
Finished Mar 28 01:26:39 PM PDT 24
Peak memory 200640 kb
Host smart-ca31a8aa-b159-44f6-b608-97c91a6dc1c8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3794636778 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_stress_all.3794636778
Directory /workspace/47.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/47.pwrmgr_stress_all_with_rand_reset.1599409452
Short name T13
Test name
Test status
Simulation time 8514291285 ps
CPU time 16.33 seconds
Started Mar 28 01:26:34 PM PDT 24
Finished Mar 28 01:26:50 PM PDT 24
Peak memory 200904 kb
Host smart-524e4659-ccac-41aa-870a-9041a4fc6b07
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1599409452 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 47.pwrmgr_stress_all_with_rand_reset.1599409452
Directory /workspace/47.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.pwrmgr_wakeup.3303489044
Short name T159
Test name
Test status
Simulation time 124637666 ps
CPU time 0.89 seconds
Started Mar 28 01:26:31 PM PDT 24
Finished Mar 28 01:26:33 PM PDT 24
Peak memory 197788 kb
Host smart-c6736182-df4f-4ca3-bb36-a825e6c43164
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3303489044 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_wakeup.3303489044
Directory /workspace/47.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/47.pwrmgr_wakeup_reset.644172234
Short name T452
Test name
Test status
Simulation time 462497227 ps
CPU time 1.21 seconds
Started Mar 28 01:26:22 PM PDT 24
Finished Mar 28 01:26:23 PM PDT 24
Peak memory 200452 kb
Host smart-e40ae30a-a899-4cb4-a1b9-49ee24e15c40
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=644172234 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_wakeup_reset.644172234
Directory /workspace/47.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/48.pwrmgr_aborted_low_power.2692611661
Short name T625
Test name
Test status
Simulation time 17274144 ps
CPU time 0.62 seconds
Started Mar 28 01:26:26 PM PDT 24
Finished Mar 28 01:26:27 PM PDT 24
Peak memory 198448 kb
Host smart-adfa1bb7-662e-47bb-8613-9a25e4afd5f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2692611661 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_aborted_low_power.2692611661
Directory /workspace/48.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/48.pwrmgr_disable_rom_integrity_check.4070752388
Short name T596
Test name
Test status
Simulation time 63584176 ps
CPU time 0.7 seconds
Started Mar 28 01:26:44 PM PDT 24
Finished Mar 28 01:26:45 PM PDT 24
Peak memory 198360 kb
Host smart-5666b4f5-51e7-44ae-8882-0fcf6ca44c05
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4070752388 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_dis
able_rom_integrity_check.4070752388
Directory /workspace/48.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/48.pwrmgr_esc_clk_rst_malfunc.2168182964
Short name T821
Test name
Test status
Simulation time 30075831 ps
CPU time 0.61 seconds
Started Mar 28 01:26:27 PM PDT 24
Finished Mar 28 01:26:28 PM PDT 24
Peak memory 197384 kb
Host smart-1d7fa241-fa34-4f16-a14b-74d83d262fb7
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2168182964 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_esc_clk_rst
_malfunc.2168182964
Directory /workspace/48.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/48.pwrmgr_escalation_timeout.1920898781
Short name T770
Test name
Test status
Simulation time 2153831952 ps
CPU time 0.94 seconds
Started Mar 28 01:26:43 PM PDT 24
Finished Mar 28 01:26:45 PM PDT 24
Peak memory 197352 kb
Host smart-7779bb3f-b61c-4471-abb3-ddf5dc2c654c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1920898781 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_escalation_timeout.1920898781
Directory /workspace/48.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/48.pwrmgr_glitch.3624763892
Short name T10
Test name
Test status
Simulation time 53393103 ps
CPU time 0.68 seconds
Started Mar 28 01:26:42 PM PDT 24
Finished Mar 28 01:26:43 PM PDT 24
Peak memory 197444 kb
Host smart-6cd4d998-6819-407e-bdb8-d921aadd103f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3624763892 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_glitch.3624763892
Directory /workspace/48.pwrmgr_glitch/latest

Test location /workspace/coverage/default/48.pwrmgr_global_esc.2889771499
Short name T358
Test name
Test status
Simulation time 115908301 ps
CPU time 0.64 seconds
Started Mar 28 01:26:43 PM PDT 24
Finished Mar 28 01:26:44 PM PDT 24
Peak memory 197416 kb
Host smart-c4890d9d-8228-462b-8af3-10512707877f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2889771499 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_global_esc.2889771499
Directory /workspace/48.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/48.pwrmgr_lowpower_invalid.955006125
Short name T797
Test name
Test status
Simulation time 121588462 ps
CPU time 0.7 seconds
Started Mar 28 01:26:40 PM PDT 24
Finished Mar 28 01:26:41 PM PDT 24
Peak memory 200616 kb
Host smart-805defa3-054c-4e77-826d-a03b128fdb6d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=955006125 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inval
id_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_lowpower_invali
d.955006125
Directory /workspace/48.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/48.pwrmgr_lowpower_wakeup_race.1662465550
Short name T649
Test name
Test status
Simulation time 114666337 ps
CPU time 0.93 seconds
Started Mar 28 01:26:30 PM PDT 24
Finished Mar 28 01:26:31 PM PDT 24
Peak memory 197684 kb
Host smart-bf6e84d2-9219-41aa-85f4-95381d278429
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1662465550 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_lowpower_w
akeup_race.1662465550
Directory /workspace/48.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/48.pwrmgr_reset.3453175628
Short name T287
Test name
Test status
Simulation time 169937210 ps
CPU time 1 seconds
Started Mar 28 01:26:35 PM PDT 24
Finished Mar 28 01:26:36 PM PDT 24
Peak memory 199216 kb
Host smart-e9480a9d-d977-46d0-b2b6-a43680823c78
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3453175628 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_reset.3453175628
Directory /workspace/48.pwrmgr_reset/latest

Test location /workspace/coverage/default/48.pwrmgr_reset_invalid.2244331739
Short name T934
Test name
Test status
Simulation time 216263014 ps
CPU time 0.83 seconds
Started Mar 28 01:26:43 PM PDT 24
Finished Mar 28 01:26:45 PM PDT 24
Peak memory 208900 kb
Host smart-2510668d-21a1-49aa-9a74-0c96ecff85a0
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2244331739 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_reset_invalid.2244331739
Directory /workspace/48.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/48.pwrmgr_sec_cm_ctrl_config_regwen.2137733695
Short name T592
Test name
Test status
Simulation time 160356443 ps
CPU time 0.91 seconds
Started Mar 28 01:26:42 PM PDT 24
Finished Mar 28 01:26:45 PM PDT 24
Peak memory 199264 kb
Host smart-09056db9-caad-48f7-9b86-ee36e9aa3295
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2137733695 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_sec_
cm_ctrl_config_regwen.2137733695
Directory /workspace/48.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/48.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2787873547
Short name T739
Test name
Test status
Simulation time 953407656 ps
CPU time 2.33 seconds
Started Mar 28 01:26:30 PM PDT 24
Finished Mar 28 01:26:32 PM PDT 24
Peak memory 200592 kb
Host smart-273aee49-48d0-48df-a5fd-332459407aa2
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2787873547 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 48.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2787873547
Directory /workspace/48.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/48.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3606346278
Short name T332
Test name
Test status
Simulation time 994364522 ps
CPU time 2.51 seconds
Started Mar 28 01:26:27 PM PDT 24
Finished Mar 28 01:26:30 PM PDT 24
Peak memory 200440 kb
Host smart-a19d20c9-9b7b-48be-9207-dbb1525ee2ca
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3606346278 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 48.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3606346278
Directory /workspace/48.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/48.pwrmgr_sec_cm_rstmgr_intersig_mubi.321822539
Short name T194
Test name
Test status
Simulation time 62867433 ps
CPU time 0.84 seconds
Started Mar 28 01:26:28 PM PDT 24
Finished Mar 28 01:26:29 PM PDT 24
Peak memory 198544 kb
Host smart-de0e9b1e-965c-4bbd-a4ac-8c0c74605847
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=321822539 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_sec_cm_rstmgr_intersig_
mubi.321822539
Directory /workspace/48.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/48.pwrmgr_smoke.3767660925
Short name T236
Test name
Test status
Simulation time 30893546 ps
CPU time 0.68 seconds
Started Mar 28 01:26:28 PM PDT 24
Finished Mar 28 01:26:29 PM PDT 24
Peak memory 198632 kb
Host smart-9650fb33-f9ef-4843-8b7f-b55b4ebeb897
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3767660925 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_smoke.3767660925
Directory /workspace/48.pwrmgr_smoke/latest

Test location /workspace/coverage/default/48.pwrmgr_stress_all.3370343295
Short name T557
Test name
Test status
Simulation time 1741263799 ps
CPU time 6.98 seconds
Started Mar 28 01:26:42 PM PDT 24
Finished Mar 28 01:26:49 PM PDT 24
Peak memory 200628 kb
Host smart-537fc86b-661c-432d-8aa0-9d787dcaac8c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3370343295 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_stress_all.3370343295
Directory /workspace/48.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/48.pwrmgr_stress_all_with_rand_reset.3020295917
Short name T496
Test name
Test status
Simulation time 11385784264 ps
CPU time 10.45 seconds
Started Mar 28 01:26:44 PM PDT 24
Finished Mar 28 01:26:54 PM PDT 24
Peak memory 200796 kb
Host smart-b6e7ee55-4abb-4e8d-a1ac-ebade48c39f7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3020295917 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 48.pwrmgr_stress_all_with_rand_reset.3020295917
Directory /workspace/48.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.pwrmgr_wakeup.2161468359
Short name T69
Test name
Test status
Simulation time 478081219 ps
CPU time 1 seconds
Started Mar 28 01:26:34 PM PDT 24
Finished Mar 28 01:26:36 PM PDT 24
Peak memory 198900 kb
Host smart-330804c2-0768-401d-a2d1-85c0a91c677c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2161468359 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_wakeup.2161468359
Directory /workspace/48.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/48.pwrmgr_wakeup_reset.774361812
Short name T716
Test name
Test status
Simulation time 52642131 ps
CPU time 0.7 seconds
Started Mar 28 01:26:28 PM PDT 24
Finished Mar 28 01:26:29 PM PDT 24
Peak memory 198548 kb
Host smart-c3fa286c-f288-483e-a529-b223ff0fd0a4
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=774361812 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_wakeup_reset.774361812
Directory /workspace/48.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/49.pwrmgr_aborted_low_power.3335769710
Short name T509
Test name
Test status
Simulation time 121088344 ps
CPU time 0.69 seconds
Started Mar 28 01:26:40 PM PDT 24
Finished Mar 28 01:26:41 PM PDT 24
Peak memory 197904 kb
Host smart-669b3aa1-f2d9-4580-8ed5-4b47c7469871
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3335769710 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_aborted_low_power.3335769710
Directory /workspace/49.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/49.pwrmgr_disable_rom_integrity_check.4010045670
Short name T150
Test name
Test status
Simulation time 73792388 ps
CPU time 0.68 seconds
Started Mar 28 01:26:42 PM PDT 24
Finished Mar 28 01:26:43 PM PDT 24
Peak memory 197924 kb
Host smart-d3c1e150-ba57-4cb3-bef7-f02266a94014
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4010045670 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_dis
able_rom_integrity_check.4010045670
Directory /workspace/49.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/49.pwrmgr_esc_clk_rst_malfunc.1312877385
Short name T306
Test name
Test status
Simulation time 47277406 ps
CPU time 0.6 seconds
Started Mar 28 01:26:41 PM PDT 24
Finished Mar 28 01:26:41 PM PDT 24
Peak memory 197376 kb
Host smart-91bf7f0b-998a-4e77-869a-f74887d35848
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1312877385 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_esc_clk_rst
_malfunc.1312877385
Directory /workspace/49.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/49.pwrmgr_escalation_timeout.1150264735
Short name T406
Test name
Test status
Simulation time 695873462 ps
CPU time 0.93 seconds
Started Mar 28 01:26:44 PM PDT 24
Finished Mar 28 01:26:45 PM PDT 24
Peak memory 197396 kb
Host smart-cb3bfb13-a818-476c-a5a4-374b407d08da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1150264735 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_escalation_timeout.1150264735
Directory /workspace/49.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/49.pwrmgr_glitch.896867558
Short name T464
Test name
Test status
Simulation time 47382732 ps
CPU time 0.64 seconds
Started Mar 28 01:26:44 PM PDT 24
Finished Mar 28 01:26:44 PM PDT 24
Peak memory 196744 kb
Host smart-236b8b55-fb94-472a-870e-d5a8beb13985
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=896867558 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_glitch.896867558
Directory /workspace/49.pwrmgr_glitch/latest

Test location /workspace/coverage/default/49.pwrmgr_global_esc.3590021437
Short name T637
Test name
Test status
Simulation time 30688350 ps
CPU time 0.63 seconds
Started Mar 28 01:26:43 PM PDT 24
Finished Mar 28 01:26:44 PM PDT 24
Peak memory 197268 kb
Host smart-63c5b8b1-c754-476c-918f-21f6622b2a88
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3590021437 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_global_esc.3590021437
Directory /workspace/49.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/49.pwrmgr_lowpower_invalid.4010815309
Short name T445
Test name
Test status
Simulation time 43255255 ps
CPU time 0.71 seconds
Started Mar 28 01:26:43 PM PDT 24
Finished Mar 28 01:26:44 PM PDT 24
Peak memory 200748 kb
Host smart-9046a205-46ff-4bd8-bd4e-d74cced575be
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4010815309 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_lowpower_inval
id.4010815309
Directory /workspace/49.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/49.pwrmgr_lowpower_wakeup_race.100558970
Short name T228
Test name
Test status
Simulation time 90277057 ps
CPU time 0.78 seconds
Started Mar 28 01:26:42 PM PDT 24
Finished Mar 28 01:26:44 PM PDT 24
Peak memory 197580 kb
Host smart-628c162f-cd25-4f56-95f8-da7e61c04a16
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100558970 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeu
p_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_lowpower_wa
keup_race.100558970
Directory /workspace/49.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/49.pwrmgr_reset.3743070145
Short name T492
Test name
Test status
Simulation time 58397403 ps
CPU time 0.85 seconds
Started Mar 28 01:26:40 PM PDT 24
Finished Mar 28 01:26:41 PM PDT 24
Peak memory 197900 kb
Host smart-11bed769-bfaa-4294-a5de-98c62107f55c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3743070145 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_reset.3743070145
Directory /workspace/49.pwrmgr_reset/latest

Test location /workspace/coverage/default/49.pwrmgr_reset_invalid.1390050165
Short name T937
Test name
Test status
Simulation time 208315715 ps
CPU time 0.81 seconds
Started Mar 28 01:26:40 PM PDT 24
Finished Mar 28 01:26:41 PM PDT 24
Peak memory 208852 kb
Host smart-7a0f2db9-d49b-4f3e-9e26-db4fbe18d76f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1390050165 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_reset_invalid.1390050165
Directory /workspace/49.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/49.pwrmgr_sec_cm_ctrl_config_regwen.2490218818
Short name T939
Test name
Test status
Simulation time 122594874 ps
CPU time 0.92 seconds
Started Mar 28 01:26:44 PM PDT 24
Finished Mar 28 01:26:45 PM PDT 24
Peak memory 198068 kb
Host smart-76aec4fc-5bd6-4b68-94fc-6f79266b00a3
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2490218818 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_sec_
cm_ctrl_config_regwen.2490218818
Directory /workspace/49.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/49.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1896466044
Short name T241
Test name
Test status
Simulation time 1060445118 ps
CPU time 2.35 seconds
Started Mar 28 01:26:43 PM PDT 24
Finished Mar 28 01:26:46 PM PDT 24
Peak memory 200244 kb
Host smart-83c75b6e-57fb-4bd4-92ff-cdabda8c6af6
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1896466044 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 49.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1896466044
Directory /workspace/49.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/49.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3868048969
Short name T972
Test name
Test status
Simulation time 1306222398 ps
CPU time 2.38 seconds
Started Mar 28 01:26:42 PM PDT 24
Finished Mar 28 01:26:44 PM PDT 24
Peak memory 200556 kb
Host smart-5e6a0ff8-5835-4e37-8887-f4adf531cfeb
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3868048969 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 49.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3868048969
Directory /workspace/49.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/49.pwrmgr_sec_cm_rstmgr_intersig_mubi.1783779218
Short name T978
Test name
Test status
Simulation time 140688011 ps
CPU time 0.88 seconds
Started Mar 28 01:26:42 PM PDT 24
Finished Mar 28 01:26:43 PM PDT 24
Peak memory 198676 kb
Host smart-9e0a70c7-4163-4ca2-b2e4-f1cf5367d09d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1783779218 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_sec_cm_rstmgr_intersig
_mubi.1783779218
Directory /workspace/49.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/49.pwrmgr_smoke.1220991509
Short name T606
Test name
Test status
Simulation time 57052316 ps
CPU time 0.63 seconds
Started Mar 28 01:26:40 PM PDT 24
Finished Mar 28 01:26:41 PM PDT 24
Peak memory 197796 kb
Host smart-b67bc112-7f0a-4984-9978-90e630c25027
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1220991509 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_smoke.1220991509
Directory /workspace/49.pwrmgr_smoke/latest

Test location /workspace/coverage/default/49.pwrmgr_stress_all.3601828574
Short name T463
Test name
Test status
Simulation time 1255221905 ps
CPU time 2.79 seconds
Started Mar 28 01:26:43 PM PDT 24
Finished Mar 28 01:26:46 PM PDT 24
Peak memory 200692 kb
Host smart-0089d7cd-2c85-48db-a25c-32d6142d4a1e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3601828574 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_stress_all.3601828574
Directory /workspace/49.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/49.pwrmgr_stress_all_with_rand_reset.838312784
Short name T111
Test name
Test status
Simulation time 23869382092 ps
CPU time 21.76 seconds
Started Mar 28 01:26:45 PM PDT 24
Finished Mar 28 01:27:07 PM PDT 24
Peak memory 200876 kb
Host smart-2865afca-93ec-4c3d-bcee-4555bff8344b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=838312784 -assert nopost
proc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 49.pwrmgr_stress_all_with_rand_reset.838312784
Directory /workspace/49.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.pwrmgr_wakeup.78246714
Short name T857
Test name
Test status
Simulation time 114145097 ps
CPU time 0.68 seconds
Started Mar 28 01:26:40 PM PDT 24
Finished Mar 28 01:26:40 PM PDT 24
Peak memory 197496 kb
Host smart-6a2afc4f-821f-4d5d-aebc-108e4e027632
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78246714 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_wakeup.78246714
Directory /workspace/49.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/49.pwrmgr_wakeup_reset.3440644490
Short name T501
Test name
Test status
Simulation time 104983891 ps
CPU time 0.67 seconds
Started Mar 28 01:26:42 PM PDT 24
Finished Mar 28 01:26:43 PM PDT 24
Peak memory 198472 kb
Host smart-ef0741c3-1c65-4d06-9216-78de4c35e7fa
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3440644490 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_wakeup_reset.3440644490
Directory /workspace/49.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/5.pwrmgr_aborted_low_power.2136998421
Short name T237
Test name
Test status
Simulation time 18219446 ps
CPU time 0.66 seconds
Started Mar 28 01:22:32 PM PDT 24
Finished Mar 28 01:22:33 PM PDT 24
Peak memory 197840 kb
Host smart-d5f0fff2-164c-4060-a62b-93071049d099
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2136998421 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_aborted_low_power.2136998421
Directory /workspace/5.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/5.pwrmgr_disable_rom_integrity_check.1557639996
Short name T143
Test name
Test status
Simulation time 79070649 ps
CPU time 0.72 seconds
Started Mar 28 01:22:32 PM PDT 24
Finished Mar 28 01:22:33 PM PDT 24
Peak memory 198068 kb
Host smart-d48ec678-85b8-4d8b-8ae5-c3dd59672c85
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1557639996 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_disa
ble_rom_integrity_check.1557639996
Directory /workspace/5.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/5.pwrmgr_esc_clk_rst_malfunc.58890167
Short name T311
Test name
Test status
Simulation time 30687988 ps
CPU time 0.62 seconds
Started Mar 28 01:22:34 PM PDT 24
Finished Mar 28 01:22:34 PM PDT 24
Peak memory 197344 kb
Host smart-2019abde-6d3c-4df2-88ec-e4402dc7cdb1
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58890167 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_mal
func_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_esc_clk_rst_ma
lfunc.58890167
Directory /workspace/5.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/5.pwrmgr_escalation_timeout.204172588
Short name T213
Test name
Test status
Simulation time 636406289 ps
CPU time 0.95 seconds
Started Mar 28 01:22:33 PM PDT 24
Finished Mar 28 01:22:34 PM PDT 24
Peak memory 197428 kb
Host smart-911a0767-d56d-4b66-8609-d1c43a8045f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=204172588 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_escalation_timeout.204172588
Directory /workspace/5.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/5.pwrmgr_glitch.2125741370
Short name T885
Test name
Test status
Simulation time 50490519 ps
CPU time 0.64 seconds
Started Mar 28 01:22:33 PM PDT 24
Finished Mar 28 01:22:34 PM PDT 24
Peak memory 196656 kb
Host smart-5594ac7a-59c0-4ee4-b7d9-b56eb17e1381
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2125741370 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_glitch.2125741370
Directory /workspace/5.pwrmgr_glitch/latest

Test location /workspace/coverage/default/5.pwrmgr_global_esc.3648934063
Short name T586
Test name
Test status
Simulation time 42156241 ps
CPU time 0.59 seconds
Started Mar 28 01:22:31 PM PDT 24
Finished Mar 28 01:22:32 PM PDT 24
Peak memory 197632 kb
Host smart-b20a759c-ac3f-4faf-af42-65c7fdc739c3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3648934063 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_global_esc.3648934063
Directory /workspace/5.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/5.pwrmgr_lowpower_invalid.3491226458
Short name T362
Test name
Test status
Simulation time 59209968 ps
CPU time 0.68 seconds
Started Mar 28 01:22:34 PM PDT 24
Finished Mar 28 01:22:35 PM PDT 24
Peak memory 200732 kb
Host smart-529bfc84-32e7-418a-81b3-5214154a8481
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3491226458 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_lowpower_invali
d.3491226458
Directory /workspace/5.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/5.pwrmgr_lowpower_wakeup_race.497081928
Short name T737
Test name
Test status
Simulation time 393882263 ps
CPU time 1.03 seconds
Started Mar 28 01:22:33 PM PDT 24
Finished Mar 28 01:22:35 PM PDT 24
Peak memory 199068 kb
Host smart-73f985ab-4b4a-4176-a805-e6495e5ed7fe
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=497081928 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeu
p_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_lowpower_wak
eup_race.497081928
Directory /workspace/5.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/5.pwrmgr_reset.2318720180
Short name T205
Test name
Test status
Simulation time 204630445 ps
CPU time 0.9 seconds
Started Mar 28 01:22:33 PM PDT 24
Finished Mar 28 01:22:34 PM PDT 24
Peak memory 198972 kb
Host smart-c2dd84e9-5f8e-457a-8959-6760fd03b458
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2318720180 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_reset.2318720180
Directory /workspace/5.pwrmgr_reset/latest

Test location /workspace/coverage/default/5.pwrmgr_reset_invalid.2990946274
Short name T915
Test name
Test status
Simulation time 154224123 ps
CPU time 0.83 seconds
Started Mar 28 01:22:32 PM PDT 24
Finished Mar 28 01:22:32 PM PDT 24
Peak memory 208860 kb
Host smart-8f8ad079-5d44-4ade-aeb0-fba788650d11
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2990946274 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_reset_invalid.2990946274
Directory /workspace/5.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/5.pwrmgr_sec_cm_ctrl_config_regwen.1626788874
Short name T698
Test name
Test status
Simulation time 223526239 ps
CPU time 0.89 seconds
Started Mar 28 01:22:33 PM PDT 24
Finished Mar 28 01:22:34 PM PDT 24
Peak memory 199116 kb
Host smart-e0795f5f-6662-408a-827a-da754c3a685a
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1626788874 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_sec_c
m_ctrl_config_regwen.1626788874
Directory /workspace/5.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/5.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2811821979
Short name T243
Test name
Test status
Simulation time 868116396 ps
CPU time 3.27 seconds
Started Mar 28 01:22:33 PM PDT 24
Finished Mar 28 01:22:36 PM PDT 24
Peak memory 200532 kb
Host smart-224b0dd5-07b0-4631-a345-2b7df8ceee9e
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2811821979 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 5.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2811821979
Directory /workspace/5.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/5.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.273443485
Short name T734
Test name
Test status
Simulation time 1177951463 ps
CPU time 2.2 seconds
Started Mar 28 01:22:33 PM PDT 24
Finished Mar 28 01:22:36 PM PDT 24
Peak memory 200440 kb
Host smart-72d6db48-d8e9-4f16-92f0-ad7d329c8318
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=273443485 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 5.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.273443485
Directory /workspace/5.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/5.pwrmgr_sec_cm_rstmgr_intersig_mubi.1829508424
Short name T811
Test name
Test status
Simulation time 53385153 ps
CPU time 0.88 seconds
Started Mar 28 01:22:31 PM PDT 24
Finished Mar 28 01:22:32 PM PDT 24
Peak memory 198564 kb
Host smart-1a7b81d4-cf2e-4502-861d-56daa426fa95
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1829508424 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_sec_cm_rstmgr_intersig_
mubi.1829508424
Directory /workspace/5.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/5.pwrmgr_smoke.234762687
Short name T974
Test name
Test status
Simulation time 53162277 ps
CPU time 0.68 seconds
Started Mar 28 01:22:33 PM PDT 24
Finished Mar 28 01:22:34 PM PDT 24
Peak memory 198652 kb
Host smart-a999cb0e-24e9-413e-8e64-775d9198593b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=234762687 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_smoke.234762687
Directory /workspace/5.pwrmgr_smoke/latest

Test location /workspace/coverage/default/5.pwrmgr_stress_all.3043952675
Short name T299
Test name
Test status
Simulation time 4091901905 ps
CPU time 2.38 seconds
Started Mar 28 01:22:33 PM PDT 24
Finished Mar 28 01:22:36 PM PDT 24
Peak memory 200684 kb
Host smart-d222d4b2-70c0-49ff-afba-9b2fc0fb5d5b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3043952675 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_stress_all.3043952675
Directory /workspace/5.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/5.pwrmgr_stress_all_with_rand_reset.2772814288
Short name T608
Test name
Test status
Simulation time 13240180270 ps
CPU time 15.65 seconds
Started Mar 28 01:22:32 PM PDT 24
Finished Mar 28 01:22:48 PM PDT 24
Peak memory 200788 kb
Host smart-38211030-dba3-4d7b-9878-dc22c09a9dca
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2772814288 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 5.pwrmgr_stress_all_with_rand_reset.2772814288
Directory /workspace/5.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.pwrmgr_wakeup.1991446361
Short name T850
Test name
Test status
Simulation time 192023590 ps
CPU time 1.17 seconds
Started Mar 28 01:22:31 PM PDT 24
Finished Mar 28 01:22:32 PM PDT 24
Peak memory 198832 kb
Host smart-4cf81674-ca09-42b0-a6eb-f4072a41bb6b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1991446361 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_wakeup.1991446361
Directory /workspace/5.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/5.pwrmgr_wakeup_reset.3502352846
Short name T408
Test name
Test status
Simulation time 329240611 ps
CPU time 1.11 seconds
Started Mar 28 01:22:33 PM PDT 24
Finished Mar 28 01:22:34 PM PDT 24
Peak memory 199572 kb
Host smart-7fef6b55-106c-4ace-bb9b-5d59714dffee
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3502352846 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_wakeup_reset.3502352846
Directory /workspace/5.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/6.pwrmgr_aborted_low_power.83006202
Short name T250
Test name
Test status
Simulation time 134666465 ps
CPU time 0.63 seconds
Started Mar 28 01:22:44 PM PDT 24
Finished Mar 28 01:22:45 PM PDT 24
Peak memory 197804 kb
Host smart-88ea47de-14fd-4051-b0a7-88cca4c7a452
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=83006202 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_aborted_low_power.83006202
Directory /workspace/6.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/6.pwrmgr_disable_rom_integrity_check.618159135
Short name T487
Test name
Test status
Simulation time 74075008 ps
CPU time 0.71 seconds
Started Mar 28 01:22:45 PM PDT 24
Finished Mar 28 01:22:46 PM PDT 24
Peak memory 198468 kb
Host smart-5bf25aa7-101e-49de-95b3-12a5824dd1d9
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=618159135 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_in
tegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_disab
le_rom_integrity_check.618159135
Directory /workspace/6.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/6.pwrmgr_esc_clk_rst_malfunc.251673139
Short name T292
Test name
Test status
Simulation time 41775196 ps
CPU time 0.62 seconds
Started Mar 28 01:22:46 PM PDT 24
Finished Mar 28 01:22:47 PM PDT 24
Peak memory 196652 kb
Host smart-780adef3-f524-4c4b-b087-33fc4a6a6f6b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=251673139 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_ma
lfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_esc_clk_rst_m
alfunc.251673139
Directory /workspace/6.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/6.pwrmgr_escalation_timeout.3128907431
Short name T352
Test name
Test status
Simulation time 168901579 ps
CPU time 0.97 seconds
Started Mar 28 01:22:44 PM PDT 24
Finished Mar 28 01:22:46 PM PDT 24
Peak memory 197408 kb
Host smart-f1fbbf2b-db7a-49ec-8095-42dba8299f13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3128907431 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_escalation_timeout.3128907431
Directory /workspace/6.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/6.pwrmgr_glitch.2084091484
Short name T881
Test name
Test status
Simulation time 55437450 ps
CPU time 0.66 seconds
Started Mar 28 01:22:47 PM PDT 24
Finished Mar 28 01:22:48 PM PDT 24
Peak memory 197368 kb
Host smart-6bf9234c-f797-41ac-a370-09db5e9275b9
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2084091484 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_glitch.2084091484
Directory /workspace/6.pwrmgr_glitch/latest

Test location /workspace/coverage/default/6.pwrmgr_global_esc.1163809011
Short name T229
Test name
Test status
Simulation time 124504911 ps
CPU time 0.61 seconds
Started Mar 28 01:22:44 PM PDT 24
Finished Mar 28 01:22:45 PM PDT 24
Peak memory 197368 kb
Host smart-e85c5bef-0d0e-44be-bdee-a7ba1e871c9f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1163809011 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_global_esc.1163809011
Directory /workspace/6.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/6.pwrmgr_lowpower_invalid.1161607481
Short name T355
Test name
Test status
Simulation time 57121182 ps
CPU time 0.7 seconds
Started Mar 28 01:22:46 PM PDT 24
Finished Mar 28 01:22:46 PM PDT 24
Peak memory 200728 kb
Host smart-0e13ec01-3331-46bc-a123-984a62de3404
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1161607481 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_lowpower_invali
d.1161607481
Directory /workspace/6.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/6.pwrmgr_lowpower_wakeup_race.2198266059
Short name T856
Test name
Test status
Simulation time 150036744 ps
CPU time 0.86 seconds
Started Mar 28 01:22:31 PM PDT 24
Finished Mar 28 01:22:32 PM PDT 24
Peak memory 197768 kb
Host smart-67b2faf0-6353-47cb-9b09-1b513733b8bb
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2198266059 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_lowpower_wa
keup_race.2198266059
Directory /workspace/6.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/6.pwrmgr_reset.1331344310
Short name T369
Test name
Test status
Simulation time 90107640 ps
CPU time 0.72 seconds
Started Mar 28 01:22:31 PM PDT 24
Finished Mar 28 01:22:32 PM PDT 24
Peak memory 197692 kb
Host smart-e4b5d972-67de-4986-b0a9-c886f9a0deb1
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1331344310 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_reset.1331344310
Directory /workspace/6.pwrmgr_reset/latest

Test location /workspace/coverage/default/6.pwrmgr_reset_invalid.1992296126
Short name T165
Test name
Test status
Simulation time 111378652 ps
CPU time 0.93 seconds
Started Mar 28 01:22:47 PM PDT 24
Finished Mar 28 01:22:48 PM PDT 24
Peak memory 208800 kb
Host smart-8d761d28-4d44-422e-bc61-8958922411db
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1992296126 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_reset_invalid.1992296126
Directory /workspace/6.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/6.pwrmgr_sec_cm_ctrl_config_regwen.2380364134
Short name T451
Test name
Test status
Simulation time 41931335 ps
CPU time 0.76 seconds
Started Mar 28 01:22:44 PM PDT 24
Finished Mar 28 01:22:44 PM PDT 24
Peak memory 198044 kb
Host smart-4b2929f2-830a-4b70-a10c-cb737731000a
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2380364134 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_sec_c
m_ctrl_config_regwen.2380364134
Directory /workspace/6.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/6.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2947084022
Short name T663
Test name
Test status
Simulation time 1158356067 ps
CPU time 2.16 seconds
Started Mar 28 01:22:48 PM PDT 24
Finished Mar 28 01:22:51 PM PDT 24
Peak memory 200476 kb
Host smart-d0a4f6c4-a3a4-46df-bc2a-fbd44e07c39f
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2947084022 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 6.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2947084022
Directory /workspace/6.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/6.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.898140873
Short name T220
Test name
Test status
Simulation time 1023857277 ps
CPU time 2.09 seconds
Started Mar 28 01:22:44 PM PDT 24
Finished Mar 28 01:22:47 PM PDT 24
Peak memory 200512 kb
Host smart-b3610232-b1fc-4004-bac9-3891913b887a
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=898140873 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 6.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.898140873
Directory /workspace/6.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/6.pwrmgr_sec_cm_rstmgr_intersig_mubi.478876735
Short name T157
Test name
Test status
Simulation time 53619419 ps
CPU time 0.95 seconds
Started Mar 28 01:22:44 PM PDT 24
Finished Mar 28 01:22:46 PM PDT 24
Peak memory 198604 kb
Host smart-debb1eca-b487-480a-9f87-7c3b5508c2e4
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=478876735 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_sec_cm_rstmgr_intersig_m
ubi.478876735
Directory /workspace/6.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/6.pwrmgr_smoke.715602576
Short name T550
Test name
Test status
Simulation time 83128022 ps
CPU time 0.62 seconds
Started Mar 28 01:22:34 PM PDT 24
Finished Mar 28 01:22:34 PM PDT 24
Peak memory 197788 kb
Host smart-0b7d71d9-4dbd-482b-8087-bce94ebbd56d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=715602576 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_smoke.715602576
Directory /workspace/6.pwrmgr_smoke/latest

Test location /workspace/coverage/default/6.pwrmgr_stress_all.1184166205
Short name T555
Test name
Test status
Simulation time 1687952574 ps
CPU time 2.1 seconds
Started Mar 28 01:22:45 PM PDT 24
Finished Mar 28 01:22:48 PM PDT 24
Peak memory 200560 kb
Host smart-3bfaad84-0911-49db-876e-022ffa5dcdca
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1184166205 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_stress_all.1184166205
Directory /workspace/6.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/6.pwrmgr_wakeup.1293373672
Short name T619
Test name
Test status
Simulation time 211360906 ps
CPU time 0.95 seconds
Started Mar 28 01:22:33 PM PDT 24
Finished Mar 28 01:22:34 PM PDT 24
Peak memory 197760 kb
Host smart-e91d30af-5a4b-4fe0-8588-c72907e1020c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1293373672 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_wakeup.1293373672
Directory /workspace/6.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/6.pwrmgr_wakeup_reset.1257829307
Short name T191
Test name
Test status
Simulation time 257547800 ps
CPU time 0.96 seconds
Started Mar 28 01:22:31 PM PDT 24
Finished Mar 28 01:22:32 PM PDT 24
Peak memory 199516 kb
Host smart-9796631b-17ed-4997-a73b-922d1833f9d9
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1257829307 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_wakeup_reset.1257829307
Directory /workspace/6.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/7.pwrmgr_aborted_low_power.2757379613
Short name T871
Test name
Test status
Simulation time 67407831 ps
CPU time 0.86 seconds
Started Mar 28 01:22:46 PM PDT 24
Finished Mar 28 01:22:48 PM PDT 24
Peak memory 199576 kb
Host smart-d26e4352-55ee-42c2-9c9f-a2ffeda39d60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2757379613 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_aborted_low_power.2757379613
Directory /workspace/7.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/7.pwrmgr_disable_rom_integrity_check.4134727040
Short name T830
Test name
Test status
Simulation time 63795295 ps
CPU time 0.86 seconds
Started Mar 28 01:22:43 PM PDT 24
Finished Mar 28 01:22:44 PM PDT 24
Peak memory 198480 kb
Host smart-9c8ab42f-2dbb-4fe5-bffd-7fda3721cd56
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4134727040 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_disa
ble_rom_integrity_check.4134727040
Directory /workspace/7.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/7.pwrmgr_esc_clk_rst_malfunc.2715278005
Short name T829
Test name
Test status
Simulation time 31898641 ps
CPU time 0.6 seconds
Started Mar 28 01:22:47 PM PDT 24
Finished Mar 28 01:22:48 PM PDT 24
Peak memory 196628 kb
Host smart-ad524fce-47bf-46b0-9eed-e1f8f1834134
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2715278005 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_esc_clk_rst_
malfunc.2715278005
Directory /workspace/7.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/7.pwrmgr_escalation_timeout.1397433996
Short name T277
Test name
Test status
Simulation time 323283730 ps
CPU time 0.96 seconds
Started Mar 28 01:22:46 PM PDT 24
Finished Mar 28 01:22:48 PM PDT 24
Peak memory 197728 kb
Host smart-5fde466c-60fd-4468-a6ba-7ca0b09dc661
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1397433996 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_escalation_timeout.1397433996
Directory /workspace/7.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/7.pwrmgr_glitch.1408696759
Short name T173
Test name
Test status
Simulation time 66003948 ps
CPU time 0.6 seconds
Started Mar 28 01:22:46 PM PDT 24
Finished Mar 28 01:22:47 PM PDT 24
Peak memory 196748 kb
Host smart-0d1c78cc-059e-4ad2-a16e-4a24eca7b58d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1408696759 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_glitch.1408696759
Directory /workspace/7.pwrmgr_glitch/latest

Test location /workspace/coverage/default/7.pwrmgr_global_esc.2739148212
Short name T401
Test name
Test status
Simulation time 60554686 ps
CPU time 0.6 seconds
Started Mar 28 01:22:44 PM PDT 24
Finished Mar 28 01:22:45 PM PDT 24
Peak memory 197456 kb
Host smart-7c16746c-b05b-42e3-996c-3fda8963bdd4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2739148212 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_global_esc.2739148212
Directory /workspace/7.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/7.pwrmgr_lowpower_invalid.1241193572
Short name T532
Test name
Test status
Simulation time 43361227 ps
CPU time 0.69 seconds
Started Mar 28 01:22:59 PM PDT 24
Finished Mar 28 01:22:59 PM PDT 24
Peak memory 200680 kb
Host smart-4667f4b6-edad-48df-be27-b5e627017bd1
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1241193572 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_lowpower_invali
d.1241193572
Directory /workspace/7.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/7.pwrmgr_lowpower_wakeup_race.192014569
Short name T506
Test name
Test status
Simulation time 196194071 ps
CPU time 0.94 seconds
Started Mar 28 01:22:45 PM PDT 24
Finished Mar 28 01:22:47 PM PDT 24
Peak memory 198884 kb
Host smart-246f8b08-059b-456d-934e-dda9c4a50d29
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=192014569 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeu
p_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_lowpower_wak
eup_race.192014569
Directory /workspace/7.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/7.pwrmgr_reset.975150805
Short name T26
Test name
Test status
Simulation time 106920979 ps
CPU time 0.82 seconds
Started Mar 28 01:22:43 PM PDT 24
Finished Mar 28 01:22:44 PM PDT 24
Peak memory 198352 kb
Host smart-9de3595a-c5fc-46c1-beed-2da5c0b39d77
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=975150805 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_reset.975150805
Directory /workspace/7.pwrmgr_reset/latest

Test location /workspace/coverage/default/7.pwrmgr_reset_invalid.3171715480
Short name T808
Test name
Test status
Simulation time 128817186 ps
CPU time 0.86 seconds
Started Mar 28 01:22:45 PM PDT 24
Finished Mar 28 01:22:47 PM PDT 24
Peak memory 208832 kb
Host smart-40c82e65-3bf8-4fba-88c7-831c41d64c7e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3171715480 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_reset_invalid.3171715480
Directory /workspace/7.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/7.pwrmgr_sec_cm_ctrl_config_regwen.1920637191
Short name T461
Test name
Test status
Simulation time 165862935 ps
CPU time 0.78 seconds
Started Mar 28 01:22:44 PM PDT 24
Finished Mar 28 01:22:45 PM PDT 24
Peak memory 198456 kb
Host smart-26e3c1d4-a264-4cf0-9a5e-e6d74fd3f511
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1920637191 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_sec_c
m_ctrl_config_regwen.1920637191
Directory /workspace/7.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/7.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.808354861
Short name T450
Test name
Test status
Simulation time 819633192 ps
CPU time 3.21 seconds
Started Mar 28 01:22:45 PM PDT 24
Finished Mar 28 01:22:49 PM PDT 24
Peak memory 200536 kb
Host smart-bb7f6f41-8a75-46cc-8a78-0bcdfcfa1b82
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=808354861 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 7.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.808354861
Directory /workspace/7.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/7.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3425595753
Short name T227
Test name
Test status
Simulation time 941894624 ps
CPU time 2.63 seconds
Started Mar 28 01:22:46 PM PDT 24
Finished Mar 28 01:22:49 PM PDT 24
Peak memory 200572 kb
Host smart-eabaa751-fb72-4604-b0f7-61c479127597
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3425595753 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 7.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3425595753
Directory /workspace/7.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/7.pwrmgr_sec_cm_rstmgr_intersig_mubi.163721275
Short name T249
Test name
Test status
Simulation time 484233355 ps
CPU time 0.85 seconds
Started Mar 28 01:22:44 PM PDT 24
Finished Mar 28 01:22:45 PM PDT 24
Peak memory 198676 kb
Host smart-dbf63b97-6f53-4024-9593-e8a5f2120031
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=163721275 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_sec_cm_rstmgr_intersig_m
ubi.163721275
Directory /workspace/7.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/7.pwrmgr_smoke.787848526
Short name T310
Test name
Test status
Simulation time 146953641 ps
CPU time 0.62 seconds
Started Mar 28 01:22:46 PM PDT 24
Finished Mar 28 01:22:47 PM PDT 24
Peak memory 197832 kb
Host smart-15bf6927-ce68-4313-af99-08ca08438579
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=787848526 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_smoke.787848526
Directory /workspace/7.pwrmgr_smoke/latest

Test location /workspace/coverage/default/7.pwrmgr_stress_all.633376993
Short name T28
Test name
Test status
Simulation time 2300969586 ps
CPU time 3.17 seconds
Started Mar 28 01:23:00 PM PDT 24
Finished Mar 28 01:23:03 PM PDT 24
Peak memory 200624 kb
Host smart-ea846643-6051-45f5-80f6-d6a6f1ac8474
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=633376993 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_stress_all.633376993
Directory /workspace/7.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/7.pwrmgr_wakeup.70697639
Short name T697
Test name
Test status
Simulation time 207369421 ps
CPU time 1.01 seconds
Started Mar 28 01:22:43 PM PDT 24
Finished Mar 28 01:22:45 PM PDT 24
Peak memory 199160 kb
Host smart-1d4ede69-39cd-4c0c-a91a-5c0d3dd7398c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70697639 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_wakeup.70697639
Directory /workspace/7.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/7.pwrmgr_wakeup_reset.558883272
Short name T752
Test name
Test status
Simulation time 191023949 ps
CPU time 1.16 seconds
Started Mar 28 01:22:45 PM PDT 24
Finished Mar 28 01:22:47 PM PDT 24
Peak memory 199384 kb
Host smart-cb5a19a7-3a36-4599-9c94-815464423953
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=558883272 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_wakeup_reset.558883272
Directory /workspace/7.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/8.pwrmgr_aborted_low_power.3186081093
Short name T344
Test name
Test status
Simulation time 18828625 ps
CPU time 0.63 seconds
Started Mar 28 01:23:01 PM PDT 24
Finished Mar 28 01:23:01 PM PDT 24
Peak memory 197824 kb
Host smart-e69fb513-7862-44fa-8878-64383ade1d73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3186081093 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_aborted_low_power.3186081093
Directory /workspace/8.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/8.pwrmgr_disable_rom_integrity_check.3044365774
Short name T988
Test name
Test status
Simulation time 54399039 ps
CPU time 0.88 seconds
Started Mar 28 01:22:59 PM PDT 24
Finished Mar 28 01:23:00 PM PDT 24
Peak memory 198524 kb
Host smart-d8ed4824-b68f-4906-81fd-3706e8723b00
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3044365774 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_disa
ble_rom_integrity_check.3044365774
Directory /workspace/8.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/8.pwrmgr_esc_clk_rst_malfunc.3058667756
Short name T207
Test name
Test status
Simulation time 30847673 ps
CPU time 0.64 seconds
Started Mar 28 01:22:59 PM PDT 24
Finished Mar 28 01:23:00 PM PDT 24
Peak memory 197372 kb
Host smart-7f0bbbbc-3a0a-401f-8643-e835a2d88307
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3058667756 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_esc_clk_rst_
malfunc.3058667756
Directory /workspace/8.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/8.pwrmgr_escalation_timeout.225723623
Short name T984
Test name
Test status
Simulation time 607426363 ps
CPU time 0.95 seconds
Started Mar 28 01:22:58 PM PDT 24
Finished Mar 28 01:23:00 PM PDT 24
Peak memory 197432 kb
Host smart-78cbcd9c-38bc-4735-9e86-f6f34e0b2f06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=225723623 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_escalation_timeout.225723623
Directory /workspace/8.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/8.pwrmgr_glitch.3589636846
Short name T866
Test name
Test status
Simulation time 174614363 ps
CPU time 0.61 seconds
Started Mar 28 01:23:01 PM PDT 24
Finished Mar 28 01:23:02 PM PDT 24
Peak memory 196608 kb
Host smart-b9e0c9f0-4f33-40b7-b636-6354633e4604
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3589636846 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_glitch.3589636846
Directory /workspace/8.pwrmgr_glitch/latest

Test location /workspace/coverage/default/8.pwrmgr_global_esc.1944338946
Short name T284
Test name
Test status
Simulation time 28127397 ps
CPU time 0.62 seconds
Started Mar 28 01:23:00 PM PDT 24
Finished Mar 28 01:23:01 PM PDT 24
Peak memory 197664 kb
Host smart-6f3f6ea7-a898-4418-b101-d603208c122e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1944338946 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_global_esc.1944338946
Directory /workspace/8.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/8.pwrmgr_lowpower_invalid.4223614444
Short name T963
Test name
Test status
Simulation time 78347823 ps
CPU time 0.66 seconds
Started Mar 28 01:23:01 PM PDT 24
Finished Mar 28 01:23:02 PM PDT 24
Peak memory 200720 kb
Host smart-8dba9e51-019d-4d0f-bf09-24263fc0f01f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4223614444 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_lowpower_invali
d.4223614444
Directory /workspace/8.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/8.pwrmgr_lowpower_wakeup_race.3257932412
Short name T799
Test name
Test status
Simulation time 109606131 ps
CPU time 0.67 seconds
Started Mar 28 01:22:59 PM PDT 24
Finished Mar 28 01:23:00 PM PDT 24
Peak memory 197424 kb
Host smart-963bdd8b-5d3b-42b3-9657-76726540befd
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3257932412 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_lowpower_wa
keup_race.3257932412
Directory /workspace/8.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/8.pwrmgr_reset.1890102692
Short name T512
Test name
Test status
Simulation time 72207052 ps
CPU time 0.74 seconds
Started Mar 28 01:23:01 PM PDT 24
Finished Mar 28 01:23:02 PM PDT 24
Peak memory 197716 kb
Host smart-c43b19ba-01c6-462d-be67-61f9e87151f7
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1890102692 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_reset.1890102692
Directory /workspace/8.pwrmgr_reset/latest

Test location /workspace/coverage/default/8.pwrmgr_reset_invalid.1693339172
Short name T166
Test name
Test status
Simulation time 96457358 ps
CPU time 0.95 seconds
Started Mar 28 01:23:00 PM PDT 24
Finished Mar 28 01:23:01 PM PDT 24
Peak memory 208716 kb
Host smart-cb990fcc-6a74-41f8-9b04-5268bd372815
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1693339172 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_reset_invalid.1693339172
Directory /workspace/8.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/8.pwrmgr_sec_cm_ctrl_config_regwen.3303971684
Short name T887
Test name
Test status
Simulation time 135919164 ps
CPU time 0.74 seconds
Started Mar 28 01:23:00 PM PDT 24
Finished Mar 28 01:23:01 PM PDT 24
Peak memory 198436 kb
Host smart-a72c752e-42f9-4118-81b8-c3d84f1877d1
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3303971684 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_sec_c
m_ctrl_config_regwen.3303971684
Directory /workspace/8.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/8.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3801566737
Short name T75
Test name
Test status
Simulation time 788457118 ps
CPU time 3.21 seconds
Started Mar 28 01:23:00 PM PDT 24
Finished Mar 28 01:23:03 PM PDT 24
Peak memory 200540 kb
Host smart-f1b85bf6-4b9d-48a7-929b-e763a21c33ae
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3801566737 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 8.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3801566737
Directory /workspace/8.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/8.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.4104974120
Short name T979
Test name
Test status
Simulation time 871923636 ps
CPU time 3.27 seconds
Started Mar 28 01:23:00 PM PDT 24
Finished Mar 28 01:23:04 PM PDT 24
Peak memory 200528 kb
Host smart-1e904d74-5cfc-47d7-827d-85deaa1acc88
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4104974120 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 8.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.4104974120
Directory /workspace/8.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/8.pwrmgr_sec_cm_rstmgr_intersig_mubi.1459779692
Short name T730
Test name
Test status
Simulation time 86994832 ps
CPU time 0.92 seconds
Started Mar 28 01:23:00 PM PDT 24
Finished Mar 28 01:23:01 PM PDT 24
Peak memory 198772 kb
Host smart-04b9a530-7ae5-4051-bd1e-1b62313dbde5
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1459779692 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_sec_cm_rstmgr_intersig_
mubi.1459779692
Directory /workspace/8.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/8.pwrmgr_smoke.2582021377
Short name T478
Test name
Test status
Simulation time 27015937 ps
CPU time 0.66 seconds
Started Mar 28 01:22:59 PM PDT 24
Finished Mar 28 01:23:00 PM PDT 24
Peak memory 198644 kb
Host smart-f120e8b3-af89-4b44-8e3c-fce7c84a5184
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2582021377 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_smoke.2582021377
Directory /workspace/8.pwrmgr_smoke/latest

Test location /workspace/coverage/default/8.pwrmgr_stress_all.1948336596
Short name T413
Test name
Test status
Simulation time 1093399839 ps
CPU time 3.95 seconds
Started Mar 28 01:23:02 PM PDT 24
Finished Mar 28 01:23:06 PM PDT 24
Peak memory 200584 kb
Host smart-9b1502c4-b7f0-46d0-afdb-6e2295f5f2fe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1948336596 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_stress_all.1948336596
Directory /workspace/8.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/8.pwrmgr_stress_all_with_rand_reset.931054044
Short name T123
Test name
Test status
Simulation time 4674936988 ps
CPU time 15.21 seconds
Started Mar 28 01:23:00 PM PDT 24
Finished Mar 28 01:23:15 PM PDT 24
Peak memory 200920 kb
Host smart-d938f0cc-0360-4f2b-af11-ea6093cb574b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=931054044 -assert nopost
proc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 8.pwrmgr_stress_all_with_rand_reset.931054044
Directory /workspace/8.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.pwrmgr_wakeup.4117610680
Short name T226
Test name
Test status
Simulation time 176975776 ps
CPU time 0.84 seconds
Started Mar 28 01:23:02 PM PDT 24
Finished Mar 28 01:23:03 PM PDT 24
Peak memory 197820 kb
Host smart-e2215407-07af-488d-8b8f-b704aa7083d0
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4117610680 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_wakeup.4117610680
Directory /workspace/8.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/8.pwrmgr_wakeup_reset.1901729582
Short name T802
Test name
Test status
Simulation time 280922053 ps
CPU time 0.92 seconds
Started Mar 28 01:23:01 PM PDT 24
Finished Mar 28 01:23:02 PM PDT 24
Peak memory 199532 kb
Host smart-fe66eb3c-4a69-43ba-9f4f-6e096584b421
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1901729582 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_wakeup_reset.1901729582
Directory /workspace/8.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/9.pwrmgr_aborted_low_power.1347918334
Short name T899
Test name
Test status
Simulation time 63670819 ps
CPU time 0.71 seconds
Started Mar 28 01:23:19 PM PDT 24
Finished Mar 28 01:23:19 PM PDT 24
Peak memory 197832 kb
Host smart-12365668-9f3e-4175-b444-d149fd6427ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1347918334 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_aborted_low_power.1347918334
Directory /workspace/9.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/9.pwrmgr_disable_rom_integrity_check.2872795734
Short name T748
Test name
Test status
Simulation time 91845786 ps
CPU time 0.69 seconds
Started Mar 28 01:23:18 PM PDT 24
Finished Mar 28 01:23:19 PM PDT 24
Peak memory 198544 kb
Host smart-11c5ab14-1e94-450d-a139-145f73743848
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2872795734 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_disa
ble_rom_integrity_check.2872795734
Directory /workspace/9.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/9.pwrmgr_esc_clk_rst_malfunc.51108331
Short name T976
Test name
Test status
Simulation time 39964380 ps
CPU time 0.61 seconds
Started Mar 28 01:23:21 PM PDT 24
Finished Mar 28 01:23:22 PM PDT 24
Peak memory 196664 kb
Host smart-fb2d645f-e23a-46e4-9fc1-56ef7cdb609e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51108331 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_mal
func_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_esc_clk_rst_ma
lfunc.51108331
Directory /workspace/9.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/9.pwrmgr_escalation_timeout.121378949
Short name T763
Test name
Test status
Simulation time 316587770 ps
CPU time 0.98 seconds
Started Mar 28 01:23:24 PM PDT 24
Finished Mar 28 01:23:25 PM PDT 24
Peak memory 197668 kb
Host smart-322b0b2e-246b-4cbe-b024-183669b2181c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=121378949 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_escalation_timeout.121378949
Directory /workspace/9.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/9.pwrmgr_glitch.15014927
Short name T425
Test name
Test status
Simulation time 79163798 ps
CPU time 0.62 seconds
Started Mar 28 01:23:20 PM PDT 24
Finished Mar 28 01:23:21 PM PDT 24
Peak memory 196804 kb
Host smart-1750b0c0-5607-40c0-bb11-972686e6f2b8
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15014927 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_glitch.15014927
Directory /workspace/9.pwrmgr_glitch/latest

Test location /workspace/coverage/default/9.pwrmgr_global_esc.3890404706
Short name T700
Test name
Test status
Simulation time 111269294 ps
CPU time 0.58 seconds
Started Mar 28 01:23:24 PM PDT 24
Finished Mar 28 01:23:24 PM PDT 24
Peak memory 197632 kb
Host smart-1b1d7b1c-dc29-46fd-b9de-a287af3e6e1c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3890404706 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_global_esc.3890404706
Directory /workspace/9.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/9.pwrmgr_lowpower_invalid.3024479501
Short name T382
Test name
Test status
Simulation time 46416503 ps
CPU time 0.75 seconds
Started Mar 28 01:23:18 PM PDT 24
Finished Mar 28 01:23:19 PM PDT 24
Peak memory 200696 kb
Host smart-732aaca3-8f8f-40cb-9130-51da936aae82
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3024479501 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_lowpower_invali
d.3024479501
Directory /workspace/9.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/9.pwrmgr_lowpower_wakeup_race.2758940459
Short name T924
Test name
Test status
Simulation time 297846131 ps
CPU time 1.23 seconds
Started Mar 28 01:22:58 PM PDT 24
Finished Mar 28 01:22:59 PM PDT 24
Peak memory 198916 kb
Host smart-02472ba7-cadc-4f6f-aca9-aa5c9de09e53
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2758940459 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_lowpower_wa
keup_race.2758940459
Directory /workspace/9.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/9.pwrmgr_reset.4241859048
Short name T421
Test name
Test status
Simulation time 56306473 ps
CPU time 0.92 seconds
Started Mar 28 01:22:58 PM PDT 24
Finished Mar 28 01:23:00 PM PDT 24
Peak memory 199160 kb
Host smart-1fd50751-f9f8-463e-934b-c97facba0444
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4241859048 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_reset.4241859048
Directory /workspace/9.pwrmgr_reset/latest

Test location /workspace/coverage/default/9.pwrmgr_reset_invalid.3765651641
Short name T840
Test name
Test status
Simulation time 167061944 ps
CPU time 0.79 seconds
Started Mar 28 01:23:17 PM PDT 24
Finished Mar 28 01:23:18 PM PDT 24
Peak memory 208904 kb
Host smart-8281519c-4ea5-44ed-9e64-cc5ab25586f7
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3765651641 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_reset_invalid.3765651641
Directory /workspace/9.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/9.pwrmgr_sec_cm_ctrl_config_regwen.4060002607
Short name T183
Test name
Test status
Simulation time 55187820 ps
CPU time 0.65 seconds
Started Mar 28 01:23:19 PM PDT 24
Finished Mar 28 01:23:20 PM PDT 24
Peak memory 198444 kb
Host smart-d9c507e8-83fd-4b59-a659-7166f4940572
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4060002607 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_sec_c
m_ctrl_config_regwen.4060002607
Directory /workspace/9.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/9.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.656803488
Short name T210
Test name
Test status
Simulation time 771908102 ps
CPU time 2.96 seconds
Started Mar 28 01:23:20 PM PDT 24
Finished Mar 28 01:23:23 PM PDT 24
Peak memory 200580 kb
Host smart-4e01d0aa-aa08-48dd-a759-cd9879c30e28
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=656803488 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 9.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.656803488
Directory /workspace/9.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/9.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3498384128
Short name T819
Test name
Test status
Simulation time 1926791951 ps
CPU time 2.29 seconds
Started Mar 28 01:23:23 PM PDT 24
Finished Mar 28 01:23:26 PM PDT 24
Peak memory 200560 kb
Host smart-52d28875-ea5d-4b86-b8d3-08326bc93a16
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3498384128 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 9.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3498384128
Directory /workspace/9.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/9.pwrmgr_sec_cm_rstmgr_intersig_mubi.1252889249
Short name T551
Test name
Test status
Simulation time 64972357 ps
CPU time 0.97 seconds
Started Mar 28 01:23:20 PM PDT 24
Finished Mar 28 01:23:21 PM PDT 24
Peak memory 198396 kb
Host smart-0518696a-4bd7-472e-a88b-ae0b16295ad4
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1252889249 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_sec_cm_rstmgr_intersig_
mubi.1252889249
Directory /workspace/9.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/9.pwrmgr_smoke.2166546033
Short name T409
Test name
Test status
Simulation time 174678615 ps
CPU time 0.61 seconds
Started Mar 28 01:22:58 PM PDT 24
Finished Mar 28 01:22:59 PM PDT 24
Peak memory 197820 kb
Host smart-d8f5c0e9-e566-483d-a45c-dc688db4f2af
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2166546033 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_smoke.2166546033
Directory /workspace/9.pwrmgr_smoke/latest

Test location /workspace/coverage/default/9.pwrmgr_stress_all.4128452730
Short name T232
Test name
Test status
Simulation time 1180986580 ps
CPU time 4.64 seconds
Started Mar 28 01:23:17 PM PDT 24
Finished Mar 28 01:23:21 PM PDT 24
Peak memory 200644 kb
Host smart-60b0f4b2-cba9-4089-9f30-f73dcdbaacce
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4128452730 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_stress_all.4128452730
Directory /workspace/9.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/9.pwrmgr_stress_all_with_rand_reset.32973902
Short name T121
Test name
Test status
Simulation time 5319641230 ps
CPU time 6.82 seconds
Started Mar 28 01:23:21 PM PDT 24
Finished Mar 28 01:23:28 PM PDT 24
Peak memory 200748 kb
Host smart-741b5a27-1f0e-4fa0-b4c1-542c727f6ac4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32973902 -assert nopostp
roc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 9.pwrmgr_stress_all_with_rand_reset.32973902
Directory /workspace/9.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.pwrmgr_wakeup.1275699571
Short name T583
Test name
Test status
Simulation time 398641804 ps
CPU time 1.02 seconds
Started Mar 28 01:23:01 PM PDT 24
Finished Mar 28 01:23:02 PM PDT 24
Peak memory 199196 kb
Host smart-8999c507-f11e-4505-9b5c-80ac785f6f6e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1275699571 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_wakeup.1275699571
Directory /workspace/9.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/9.pwrmgr_wakeup_reset.3348833548
Short name T786
Test name
Test status
Simulation time 108863714 ps
CPU time 1.03 seconds
Started Mar 28 01:23:01 PM PDT 24
Finished Mar 28 01:23:03 PM PDT 24
Peak memory 199232 kb
Host smart-983d128f-2125-47e4-94a8-6e89f7796441
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3348833548 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_wakeup_reset.3348833548
Directory /workspace/9.pwrmgr_wakeup_reset/latest
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