Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	475120	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

182049

1

T1

1

T3

51

T4

35

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	345381	1			T1	1		T2	1		T3	84
values[0x0]	155678	1			T3	14		T4	18		T5	8
values[0x1]	156110	1			T3	19		T4	15		T5	14

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	376095	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

281074

1

T1

1

T3

60

T4

42

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	2631	1			T6	1		T39	2		T25	2
valid_sources[0x01]	2181	1			T6	1		T7	1		T25	3
valid_sources[0x02]	2456	1			T3	1		T6	2		T8	1
valid_sources[0x03]	2147	1			T6	1		T8	1		T9	1
valid_sources[0x04]	3169	1			T5	1		T6	3		T7	1
valid_sources[0x05]	3071	1			T4	2		T6	2		T25	1
valid_sources[0x06]	2144	1			T4	1		T5	2		T6	2
valid_sources[0x07]	2066	1			T6	3		T8	1		T39	3
valid_sources[0x08]	2116	1			T6	1		T25	8		T178	1
valid_sources[0x09]	2131	1			T4	1		T6	8		T7	2
valid_sources[0x0a]	3367	1			T3	1		T6	7		T26	1
valid_sources[0x0b]	2123	1			T6	1		T39	1		T25	4
valid_sources[0x0c]	2255	1			T4	2		T6	1		T39	1
valid_sources[0x0d]	2402	1			T4	2		T6	1		T60	2
valid_sources[0x0e]	2261	1			T5	1		T8	1		T13	2
valid_sources[0x0f]	2208	1			T5	1		T6	2		T25	3
valid_sources[0x10]	2273	1			T5	1		T6	3		T39	2
valid_sources[0x11]	2228	1			T6	12		T39	1		T25	3
valid_sources[0x12]	3194	1			T6	3		T8	1		T39	2
valid_sources[0x13]	2068	1			T4	1		T6	4		T7	3
valid_sources[0x14]	2170	1			T5	1		T8	1		T25	3
valid_sources[0x15]	2151	1			T6	11		T39	2		T138	3
valid_sources[0x16]	2129	1			T6	6		T26	2		T39	2
valid_sources[0x17]	2147	1			T3	1		T6	8		T25	4
valid_sources[0x18]	2349	1			T6	4		T39	3		T25	2
valid_sources[0x19]	2122	1			T4	6		T6	5		T8	1
valid_sources[0x1a]	2120	1			T6	7		T39	2		T25	2
valid_sources[0x1b]	2061	1			T6	2		T60	4		T39	1
valid_sources[0x1c]	2053	1			T4	2		T6	3		T8	2
valid_sources[0x1d]	2361	1			T6	6		T26	1		T39	1
valid_sources[0x1e]	1956	1			T3	2		T6	3		T39	3
valid_sources[0x1f]	2134	1			T6	2		T7	1		T39	1
valid_sources[0x20]	2461	1			T3	1		T5	1		T6	3
valid_sources[0x21]	5362	1			T4	2		T6	4		T39	2
valid_sources[0x22]	2194	1			T4	1		T6	1		T26	2
valid_sources[0x23]	2178	1			T4	2		T6	1		T8	1
valid_sources[0x24]	2638	1			T26	1		T39	1		T25	5
valid_sources[0x25]	2719	1			T6	2		T25	6		T138	1
valid_sources[0x26]	3870	1			T3	1		T6	1		T39	2
valid_sources[0x27]	4463	1			T3	1		T6	4		T39	2
valid_sources[0x28]	2273	1			T3	1		T5	1		T6	2
valid_sources[0x29]	2217	1			T4	1		T5	1		T6	4
valid_sources[0x2a]	1964	1			T5	2		T6	1		T7	2
valid_sources[0x2b]	2471	1			T6	2		T7	1		T25	2
valid_sources[0x2c]	4353	1			T3	1		T6	4		T26	1
valid_sources[0x2d]	2309	1			T3	2		T6	2		T25	3
valid_sources[0x2e]	2669	1			T6	6		T39	1		T25	2
valid_sources[0x2f]	2136	1			T6	1		T9	2		T39	1
valid_sources[0x30]	2258	1			T6	3		T8	4		T39	1
valid_sources[0x31]	3287	1			T3	3		T5	2		T6	5
valid_sources[0x32]	2740	1			T6	1		T26	2		T25	3
valid_sources[0x33]	2470	1			T6	5		T8	2		T39	1
valid_sources[0x34]	2106	1			T6	4		T7	4		T26	1
valid_sources[0x35]	2248	1			T4	1		T6	2		T7	1
valid_sources[0x36]	2469	1			T4	1		T6	5		T39	2
valid_sources[0x37]	2466	1			T6	6		T7	4		T60	4
valid_sources[0x38]	2123	1			T3	1		T4	2		T5	1
valid_sources[0x39]	1838	1			T3	3		T5	3		T6	1
valid_sources[0x3a]	2681	1			T3	1		T6	7		T7	2
valid_sources[0x3b]	2231	1			T6	3		T60	10		T25	4
valid_sources[0x3c]	2487	1			T6	1		T8	1		T26	1
valid_sources[0x3d]	2045	1			T3	2		T6	2		T39	1
valid_sources[0x3e]	2328	1			T6	2		T26	1		T25	4
valid_sources[0x3f]	2107	1			T6	4		T8	1		T26	1
valid_sources[0x40]	2178	1			T4	1		T6	3		T25	3
valid_sources[0x41]	2325	1			T6	8		T8	1		T25	1
valid_sources[0x42]	2184	1			T3	4		T4	2		T6	5
valid_sources[0x43]	1955	1			T6	2		T39	1		T25	4
valid_sources[0x44]	2205	1			T3	1		T6	7		T39	1
valid_sources[0x45]	2154	1			T5	1		T6	1		T8	1
valid_sources[0x46]	2002	1			T6	3		T26	1		T25	2
valid_sources[0x47]	2300	1			T6	2		T7	2		T25	3
valid_sources[0x48]	2868	1			T3	2		T6	3		T7	1
valid_sources[0x49]	2133	1			T3	2		T6	4		T39	1
valid_sources[0x4a]	2168	1			T5	1		T6	2		T39	2
valid_sources[0x4b]	2054	1			T6	1		T60	4		T39	1
valid_sources[0x4c]	2444	1			T4	1		T6	3		T8	2
valid_sources[0x4d]	6664	1			T5	1		T6	1		T25	4
valid_sources[0x4e]	2200	1			T6	3		T9	4		T39	3
valid_sources[0x4f]	2132	1			T6	4		T8	1		T39	1
valid_sources[0x50]	2412	1			T5	1		T6	4		T60	2
valid_sources[0x51]	2213	1			T6	3		T8	1		T25	4
valid_sources[0x52]	2163	1			T6	1		T60	26		T39	1
valid_sources[0x53]	2129	1			T3	3		T4	1		T5	2
valid_sources[0x54]	1928	1			T4	1		T26	1		T39	1
valid_sources[0x55]	2083	1			T6	9		T60	18		T39	1
valid_sources[0x56]	2903	1			T5	2		T6	8		T7	8
valid_sources[0x57]	2245	1			T3	5		T4	2		T6	5
valid_sources[0x58]	2071	1			T3	2		T5	1		T6	5
valid_sources[0x59]	2072	1			T6	6		T7	1		T39	2
valid_sources[0x5a]	2067	1			T6	4		T39	2		T25	3
valid_sources[0x5b]	3118	1			T6	4		T8	1		T25	4
valid_sources[0x5c]	2033	1			T6	7		T7	1		T8	2
valid_sources[0x5d]	2076	1			T1	1		T3	1		T4	1
valid_sources[0x5e]	2089	1			T6	1		T60	9		T40	1
valid_sources[0x5f]	2253	1			T3	1		T5	2		T6	3
valid_sources[0x60]	2508	1			T3	3		T6	3		T9	3
valid_sources[0x61]	2013	1			T4	2		T6	5		T25	7
valid_sources[0x62]	4837	1			T6	7		T39	2		T25	1
valid_sources[0x63]	2317	1			T3	1		T8	1		T13	8
valid_sources[0x64]	3449	1			T5	1		T6	6		T7	1
valid_sources[0x65]	2133	1			T3	1		T4	1		T6	2
valid_sources[0x66]	2171	1			T6	4		T39	2		T25	1
valid_sources[0x67]	2771	1			T6	4		T39	1		T25	1
valid_sources[0x68]	2148	1			T3	2		T4	1		T6	2
valid_sources[0x69]	2311	1			T6	3		T39	2		T25	1
valid_sources[0x6a]	2088	1			T5	1		T6	2		T25	5
valid_sources[0x6b]	2082	1			T3	3		T6	2		T39	1
valid_sources[0x6c]	1948	1			T5	1		T6	7		T7	4
valid_sources[0x6d]	2250	1			T3	4		T5	1		T6	5
valid_sources[0x6e]	2004	1			T6	3		T7	2		T39	1
valid_sources[0x6f]	6091	1			T3	1		T5	2		T6	2
valid_sources[0x70]	2097	1			T5	1		T6	4		T8	1
valid_sources[0x71]	2017	1			T3	2		T5	2		T6	2
valid_sources[0x72]	3130	1			T6	2		T39	1		T25	2
valid_sources[0x73]	2669	1			T6	2		T25	1		T40	8
valid_sources[0x74]	2345	1			T3	1		T4	1		T6	6
valid_sources[0x75]	3373	1			T4	3		T6	2		T8	1
valid_sources[0x76]	4888	1			T6	7		T39	1		T25	11
valid_sources[0x77]	2005	1			T3	1		T6	3		T7	3
valid_sources[0x78]	1866	1			T3	1		T6	3		T26	1
valid_sources[0x79]	2053	1			T6	7		T39	1		T25	2
valid_sources[0x7a]	3155	1			T4	1		T5	1		T7	3
valid_sources[0x7b]	3785	1			T3	1		T6	3		T39	2
valid_sources[0x7c]	2144	1			T5	1		T6	2		T8	1
valid_sources[0x7d]	2016	1			T4	1		T6	2		T39	1
valid_sources[0x7e]	1893	1			T6	3		T7	2		T39	2
valid_sources[0x7f]	2036	1			T3	1		T6	4		T9	9
valid_sources[0x80]	1989	1			T4	2		T6	5		T79	3

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

92463

1

T1

1

T3

41

T4

30

values[0x0]

all_enables

biggest_size

58201

1

T3

6

T4

3

T5

3

values[0x1]

all_enables

biggest_size

31385

1

T3

4

T4

2

T5

1