SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING |
100.00 | 100.00 | 1 | 100 | 1 | 1 | 64 | 64 |
NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_rom_ctrl_done_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_rom_ctrl_good_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_sw_rst_req_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 35163 | 1 | T6 | 398 | T27 | 1 | T25 | 389 | ||||
others[1] | 34853 | 1 | T5 | 2 | T6 | 387 | T25 | 383 | ||||
others[2] | 35095 | 1 | T6 | 388 | T25 | 416 | T79 | 375 | ||||
others[3] | 58304 | 1 | T6 | 697 | T26 | 1 | T25 | 688 | ||||
false | 17284 | 1 | T5 | 3 | T6 | 50 | T9 | 2 | ||||
true | 26775 | 1 | T1 | 3 | T2 | 2 | T3 | 13 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 34903 | 1 | T6 | 385 | T25 | 404 | T79 | 382 | ||||
others[1] | 35079 | 1 | T5 | 1 | T6 | 431 | T26 | 1 | ||||
others[2] | 35359 | 1 | T6 | 380 | T25 | 393 | T79 | 404 | ||||
others[3] | 58185 | 1 | T6 | 676 | T25 | 658 | T79 | 652 | ||||
false | 11230 | 1 | T5 | 4 | T6 | 50 | T9 | 3 | ||||
true | 20795 | 1 | T1 | 3 | T2 | 2 | T3 | 13 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 683 | 1 | T8 | 1 | T60 | 2 | T27 | 2 | ||||
others[1] | 693 | 1 | T3 | 1 | T5 | 1 | T9 | 1 | ||||
others[2] | 655 | 1 | T4 | 1 | T9 | 3 | T26 | 1 | ||||
others[3] | 1072 | 1 | T3 | 2 | T4 | 1 | T8 | 1 | ||||
false | 12786 | 1 | T1 | 3 | T2 | 2 | T3 | 21 | ||||
true | 3786 | 1 | T3 | 5 | T4 | 7 | T5 | 2 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |