Unified Coverage Report :: Module :: pwrmgr_csr_assert_fpv

Module : pwrmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_pwrmgr_csr_assert_0/pwrmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.pwrmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : pwrmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	23385474	14902	0	0
intr_enable_rd_A	23385474	39653	0	0
reset_en_rd_A	23385474	1153	0	0
reset_en_regwen_rd_A	23385474	1157	0	0
wake_info_capture_dis_rd_A	23385474	1042	0	0
wakeup_en_rd_A	23385474	1942	0	0
wakeup_en_regwen_rd_A	23385474	1050	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23385474	14902	0	0
T16	159837	2	0	0
T23	0	10	0	0
T24	0	31	0	0
T30	0	10	0	0
T34	0	12	0	0
T47	0	37	0	0
T48	0	95	0	0
T54	3919	0	0	0
T72	0	18	0	0
T80	943	0	0	0
T82	55663	0	0	0
T130	0	31	0	0
T131	0	1	0	0
T132	5361	0	0	0
T133	1309	0	0	0
T134	5685	0	0	0
T135	1071	0	0	0
T136	859	0	0	0
T137	2350	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23385474	39653	0	0
T7	2218	49	0	0
T8	4672	0	0	0
T9	4643	0	0	0
T10	2539	0	0	0
T11	15928	0	0	0
T13	1243	0	0	0
T14	7627	0	0	0
T16	0	1648	0	0
T26	1303	0	0	0
T27	0	2	0	0
T41	1168	8	0	0
T60	5259	0	0	0
T78	0	30	0	0
T80	0	8	0	0
T81	0	33	0	0
T82	0	195	0	0
T135	0	6	0	0
T138	0	88	0	0

reset_en_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23385474	1153	0	0
T34	0	10	0	0
T44	2003	0	0	0
T45	0	5	0	0
T55	16098	0	0	0
T72	114563	4	0	0
T139	0	13	0	0
T140	0	10	0	0
T141	0	1	0	0
T142	0	5	0	0
T143	0	23	0	0
T144	0	10	0	0
T145	0	1	0	0
T146	2045	0	0	0
T147	6103	0	0	0
T148	1669	0	0	0
T149	5446	0	0	0
T150	15579	0	0	0
T151	2754	0	0	0
T152	2264	0	0	0

reset_en_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23385474	1157	0	0
T34	0	6	0	0
T44	2003	0	0	0
T45	0	13	0	0
T55	16098	0	0	0
T59	0	3	0	0
T72	114563	5	0	0
T140	0	20	0	0
T142	0	3	0	0
T143	0	22	0	0
T144	0	7	0	0
T145	0	7	0	0
T146	2045	0	0	0
T147	6103	0	0	0
T148	1669	0	0	0
T149	5446	0	0	0
T150	15579	0	0	0
T151	2754	0	0	0
T152	2264	0	0	0
T153	0	8	0	0

wake_info_capture_dis_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23385474	1042	0	0
T34	231493	8	0	0
T35	2401	0	0	0
T36	1310	0	0	0
T37	9413	0	0	0
T38	27488	0	0	0
T45	0	9	0	0
T58	0	13	0	0
T100	11216	0	0	0
T139	0	4	0	0
T140	0	21	0	0
T142	0	1	0	0
T143	0	12	0	0
T144	0	15	0	0
T145	0	1	0	0
T153	0	1	0	0
T154	2868	0	0	0
T155	54902	0	0	0
T156	7254	0	0	0
T157	16817	0	0	0

wakeup_en_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23385474	1942	0	0
T34	0	1	0	0
T44	2003	0	0	0
T45	0	1	0	0
T55	16098	0	0	0
T72	114563	2	0	0
T139	0	17	0	0
T140	0	20	0	0
T141	0	1	0	0
T142	0	1	0	0
T144	0	7	0	0
T145	0	6	0	0
T146	2045	0	0	0
T147	6103	0	0	0
T148	1669	0	0	0
T149	5446	0	0	0
T150	15579	0	0	0
T151	2754	0	0	0
T152	2264	0	0	0
T153	0	2	0	0

wakeup_en_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23385474	1050	0	0
T34	231493	9	0	0
T35	2401	0	0	0
T36	1310	0	0	0
T37	9413	0	0	0
T38	27488	0	0	0
T45	0	6	0	0
T58	0	17	0	0
T59	0	10	0	0
T100	11216	0	0	0
T139	0	4	0	0
T140	0	19	0	0
T141	0	7	0	0
T142	0	4	0	0
T143	0	8	0	0
T153	0	1	0	0
T154	2868	0	0	0
T155	54902	0	0	0
T156	7254	0	0	0
T157	16817	0	0	0