Unified Coverage Report :: Module :: pwrmgr_sec_cm_checker_assert

Module : pwrmgr_sec_cm_checker_assert

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_sec_cm_checker_assert	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.pwrmgr_sec_cm_checker_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : pwrmgr_sec_cm_checker_assert

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	39	1	1	100.00
ALWAYS	40	1	1	100.00
ALWAYS	41	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv' or '../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
39	1	1
40	1	1
41	1	1

---

Cond Coverage for Module : pwrmgr_sec_cm_checker_assert

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       39
 EXPRESSION (((!rst_ni)) || disable_sva)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       40
 EXPRESSION (((!rst_esc_ni)) || disable_sva)
             -------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       41
 EXPRESSION (((!rst_slow_ni)) || disable_sva)
             --------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

---

Assert Coverage for Module : pwrmgr_sec_cm_checker_assert

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	10	10	100.00	10	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	10	10	100.00	10	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
RomAllowActiveState_A	22751409	55032	0	0
RomAllowCheckGoodState_A	22751409	55081	0	0
RomBlockActiveState_A	22751409	31820	0	0
RomBlockCheckGoodState_A	22751409	431126	0	0
RomIntgChkDisFalse_A	22751409	22116169	0	0
RomIntgChkDisTrue_A	22751409	151603	0	0
RstreqChkEsctimeout_A	22751409	4061	0	0
RstreqChkFsmterm_A	22751409	120	0	0
RstreqChkGlbesc_A	22751409	4064	0	0
RstreqChkMainpd_A	22751409	986429	0	0

RomAllowActiveState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22751409	55032	0	0
T1	1913	3	0	0
T2	1115	2	0	0
T3	2836	13	0	0
T4	6494	12	0	0
T5	1631	7	0	0
T6	38066	87	0	0
T7	2218	13	0	0
T8	4672	12	0	0
T9	4643	10	0	0
T10	2539	3	0	0

RomAllowCheckGoodState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22751409	55081	0	0
T1	1913	3	0	0
T2	1115	2	0	0
T3	2836	14	0	0
T4	6494	13	0	0
T5	1631	7	0	0
T6	38066	87	0	0
T7	2218	13	0	0
T8	4672	13	0	0
T9	4643	10	0	0
T10	2539	3	0	0

RomBlockActiveState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22751409	31820	0	0
T5	1631	360	0	0
T6	38066	0	0	0
T7	2218	0	0	0
T8	4672	0	0	0
T9	4643	848	0	0
T10	2539	0	0	0
T11	15928	0	0	0
T13	1243	0	0	0
T26	1303	102	0	0
T27	0	393	0	0
T41	1168	0	0	0
T91	0	296	0	0
T158	0	898	0	0
T159	0	1422	0	0
T160	0	241	0	0
T161	0	21	0	0
T162	0	238	0	0

RomBlockCheckGoodState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22751409	431126	0	0
T5	1631	121	0	0
T6	38066	2958	0	0
T7	2218	0	0	0
T8	4672	0	0	0
T9	4643	682	0	0
T10	2539	0	0	0
T11	15928	0	0	0
T13	1243	0	0	0
T15	0	1446	0	0
T25	0	1338	0	0
T26	1303	2	0	0
T27	0	235	0	0
T40	0	253	0	0
T41	1168	0	0	0
T78	0	390	0	0
T79	0	1310	0	0

RomIntgChkDisFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22751409	22116169	0	0
T1	1913	1654	0	0
T2	1115	947	0	0
T3	2836	1900	0	0
T4	6494	5624	0	0
T5	1631	1002	0	0
T6	38066	37924	0	0
T7	2218	2157	0	0
T8	4672	3786	0	0
T9	4643	3067	0	0
T10	2539	2365	0	0

RomIntgChkDisTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22751409	151603	0	0
T5	1631	485	0	0
T6	38066	0	0	0
T7	2218	0	0	0
T8	4672	0	0	0
T9	4643	1488	0	0
T10	2539	0	0	0
T11	15928	0	0	0
T13	1243	0	0	0
T26	1303	129	0	0
T27	0	188	0	0
T41	1168	0	0	0
T82	0	1782	0	0
T91	0	90	0	0
T158	0	2086	0	0
T159	0	309	0	0
T160	0	182	0	0
T163	0	726	0	0

RstreqChkEsctimeout_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22751409	4061	0	0
T1	1913	2	0	0
T2	1115	1	0	0
T3	2836	4	0	0
T4	6494	5	0	0
T5	1631	4	0	0
T6	38066	0	0	0
T7	2218	0	0	0
T8	4672	7	0	0
T9	4643	3	0	0
T10	2539	1	0	0
T11	0	1	0	0
T26	0	2	0	0

RstreqChkFsmterm_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22751409	120	0	0
T20	8318	20	0	0
T21	0	20	0	0
T22	0	20	0	0
T28	0	20	0	0
T29	0	40	0	0
T30	166498	0	0	0
T31	1193	0	0	0
T32	770	0	0	0
T33	515	0	0	0
T34	231493	0	0	0
T35	2401	0	0	0
T36	1310	0	0	0
T37	9413	0	0	0
T38	27488	0	0	0

RstreqChkGlbesc_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22751409	4064	0	0
T1	1913	2	0	0
T2	1115	1	0	0
T3	2836	4	0	0
T4	6494	5	0	0
T5	1631	4	0	0
T6	38066	0	0	0
T7	2218	0	0	0
T8	4672	7	0	0
T9	4643	3	0	0
T10	2539	1	0	0
T11	0	1	0	0
T26	0	2	0	0

RstreqChkMainpd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22751409	986429	0	0
T3	2836	87	0	0
T4	6494	213	0	0
T5	1631	24	0	0
T6	38066	3378	0	0
T7	2218	0	0	0
T8	4672	170	0	0
T9	4643	1428	0	0
T10	2539	0	0	0
T13	1243	0	0	0
T26	1303	36	0	0
T27	0	686	0	0
T39	0	164	0	0
T41	0	20	0	0