Group : pwrmgr_env_pkg::pwrmgr_env_cov::control_cg
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Group : pwrmgr_env_pkg::pwrmgr_env_cov::control_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_env_0.1/pwrmgr_env_cov.sv


Summary for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 12 0 12 100.00
Crosses 64 0 64 100.00


Variables for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
core_cp 2 0 2 100.00 100 1 1 2
io_cp 2 0 2 100.00 100 1 1 2
main_pd_n_cp 2 0 2 100.00 100 1 1 2
sleep_cp 2 0 2 100.00 100 1 1 2
usb_active_cp 2 0 2 100.00 100 1 1 2
usb_lp_cp 2 0 2 100.00 100 1 1 2


Crosses for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
control_cross 64 0 64 100.00 100 1 1 0


Summary for Variable core_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for core_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 29751 1 T2 22 T5 2 T7 664
auto[1] 28409 1 T2 18 T7 557 T9 9


Summary for Variable io_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for io_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 29656 1 T2 18 T5 2 T7 613
auto[1] 28504 1 T2 22 T7 608 T9 7


Summary for Variable main_pd_n_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for main_pd_n_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 28729 1 T2 24 T7 605 T9 6
auto[1] 29431 1 T2 16 T5 2 T7 616


Summary for Variable sleep_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for sleep_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 33101 1 T2 20 T5 1 T7 734
auto[1] 25059 1 T2 20 T5 1 T7 487


Summary for Variable usb_active_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for usb_active_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 28294 1 T2 20 T7 619 T9 11
auto[1] 29866 1 T2 20 T5 2 T7 602


Summary for Variable usb_lp_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for usb_lp_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 30081 1 T2 18 T5 2 T7 627
auto[1] 28079 1 T2 22 T7 594 T9 7


Summary for Cross control_cross

Samples crossed: core_cp io_cp usb_lp_cp usb_active_cp main_pd_n_cp sleep_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 64 0 64 100.00


Automatically Generated Cross Bins for control_cross

Bins
core_cpio_cpusb_lp_cpusb_active_cpmain_pd_n_cpsleep_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] auto[0] auto[0] auto[0] auto[0] 997 1 T2 1 T7 23 T14 22
auto[0] auto[0] auto[0] auto[0] auto[0] auto[1] 745 1 T2 1 T7 18 T14 20
auto[0] auto[0] auto[0] auto[0] auto[1] auto[0] 993 1 T7 26 T9 2 T14 17
auto[0] auto[0] auto[0] auto[0] auto[1] auto[1] 767 1 T7 19 T14 11 T27 1
auto[0] auto[0] auto[0] auto[1] auto[0] auto[0] 1051 1 T2 1 T7 15 T14 20
auto[0] auto[0] auto[0] auto[1] auto[0] auto[1] 812 1 T2 1 T7 9 T14 13
auto[0] auto[0] auto[0] auto[1] auto[1] auto[0] 1596 1 T5 1 T7 39 T14 30
auto[0] auto[0] auto[0] auto[1] auto[1] auto[1] 1340 1 T5 1 T7 28 T14 27
auto[0] auto[0] auto[1] auto[0] auto[0] auto[0] 1007 1 T7 30 T14 17 T78 1
auto[0] auto[0] auto[1] auto[0] auto[0] auto[1] 714 1 T7 18 T14 12 T26 3
auto[0] auto[0] auto[1] auto[0] auto[1] auto[0] 1041 1 T7 31 T9 1 T14 22
auto[0] auto[0] auto[1] auto[0] auto[1] auto[1] 781 1 T7 20 T14 20 T26 2
auto[0] auto[0] auto[1] auto[1] auto[0] auto[0] 991 1 T2 2 T7 19 T14 17
auto[0] auto[0] auto[1] auto[1] auto[0] auto[1] 738 1 T2 2 T7 17 T14 14
auto[0] auto[0] auto[1] auto[1] auto[1] auto[0] 965 1 T7 15 T9 1 T14 22
auto[0] auto[0] auto[1] auto[1] auto[1] auto[1] 741 1 T7 12 T14 19 T27 1
auto[0] auto[1] auto[0] auto[0] auto[0] auto[0] 1048 1 T2 2 T7 27 T14 23
auto[0] auto[1] auto[0] auto[0] auto[0] auto[1] 778 1 T2 2 T7 19 T14 20
auto[0] auto[1] auto[0] auto[0] auto[1] auto[0] 1025 1 T7 31 T9 2 T14 9
auto[0] auto[1] auto[0] auto[0] auto[1] auto[1] 771 1 T7 22 T14 6 T26 5
auto[0] auto[1] auto[0] auto[1] auto[0] auto[0] 1078 1 T7 21 T14 27 T78 1
auto[0] auto[1] auto[0] auto[1] auto[0] auto[1] 838 1 T7 15 T14 25 T26 1
auto[0] auto[1] auto[0] auto[1] auto[1] auto[0] 1015 1 T7 22 T14 14 T30 3
auto[0] auto[1] auto[0] auto[1] auto[1] auto[1] 793 1 T7 11 T14 12 T30 2
auto[0] auto[1] auto[1] auto[0] auto[0] auto[0] 1061 1 T2 1 T7 25 T9 1
auto[0] auto[1] auto[1] auto[0] auto[0] auto[1] 799 1 T2 1 T7 16 T14 16
auto[0] auto[1] auto[1] auto[0] auto[1] auto[0] 1011 1 T2 3 T7 20 T14 18
auto[0] auto[1] auto[1] auto[0] auto[1] auto[1] 758 1 T2 3 T7 12 T14 14
auto[0] auto[1] auto[1] auto[1] auto[0] auto[0] 1034 1 T7 23 T14 9 T26 1
auto[0] auto[1] auto[1] auto[1] auto[0] auto[1] 775 1 T7 17 T14 7 T26 1
auto[0] auto[1] auto[1] auto[1] auto[1] auto[0] 960 1 T2 1 T7 27 T14 23
auto[0] auto[1] auto[1] auto[1] auto[1] auto[1] 728 1 T2 1 T7 17 T14 19
auto[1] auto[0] auto[0] auto[0] auto[0] auto[0] 1006 1 T7 12 T9 2 T14 18
auto[1] auto[0] auto[0] auto[0] auto[0] auto[1] 746 1 T7 10 T14 15 T26 2
auto[1] auto[0] auto[0] auto[0] auto[1] auto[0] 1045 1 T7 26 T14 19 T27 1
auto[1] auto[0] auto[0] auto[0] auto[1] auto[1] 803 1 T7 12 T14 14 T27 1
auto[1] auto[0] auto[0] auto[1] auto[0] auto[0] 1065 1 T2 2 T7 30 T9 1
auto[1] auto[0] auto[0] auto[1] auto[0] auto[1] 819 1 T2 2 T7 21 T14 21
auto[1] auto[0] auto[0] auto[1] auto[1] auto[0] 1004 1 T7 23 T14 18 T78 1
auto[1] auto[0] auto[0] auto[1] auto[1] auto[1] 763 1 T7 14 T14 14 T26 2
auto[1] auto[0] auto[1] auto[0] auto[0] auto[0] 1029 1 T2 1 T7 25 T14 19
auto[1] auto[0] auto[1] auto[0] auto[0] auto[1] 753 1 T2 1 T7 15 T14 19
auto[1] auto[0] auto[1] auto[0] auto[1] auto[0] 1029 1 T2 1 T7 17 T9 1
auto[1] auto[0] auto[1] auto[0] auto[1] auto[1] 759 1 T2 1 T7 10 T14 14
auto[1] auto[0] auto[1] auto[1] auto[0] auto[0] 1023 1 T7 19 T9 1 T14 18
auto[1] auto[0] auto[1] auto[1] auto[0] auto[1] 770 1 T7 11 T14 15 T30 1
auto[1] auto[0] auto[1] auto[1] auto[1] auto[0] 1006 1 T2 1 T7 17 T14 17
auto[1] auto[0] auto[1] auto[1] auto[1] auto[1] 757 1 T2 1 T7 12 T14 12
auto[1] auto[1] auto[0] auto[0] auto[0] auto[0] 1049 1 T2 1 T7 23 T14 25
auto[1] auto[1] auto[0] auto[0] auto[0] auto[1] 806 1 T2 1 T7 12 T14 17
auto[1] auto[1] auto[0] auto[0] auto[1] auto[0] 963 1 T7 18 T9 1 T14 15
auto[1] auto[1] auto[0] auto[0] auto[1] auto[1] 724 1 T7 12 T14 11 T26 3
auto[1] auto[1] auto[0] auto[1] auto[0] auto[0] 1025 1 T2 1 T7 18 T9 1
auto[1] auto[1] auto[0] auto[1] auto[0] auto[1] 752 1 T2 1 T7 12 T14 19
auto[1] auto[1] auto[0] auto[1] auto[1] auto[0] 1060 1 T2 1 T7 23 T14 17
auto[1] auto[1] auto[0] auto[1] auto[1] auto[1] 804 1 T2 1 T7 16 T14 17
auto[1] auto[1] auto[1] auto[0] auto[0] auto[0] 937 1 T7 29 T14 19 T78 1
auto[1] auto[1] auto[1] auto[0] auto[0] auto[1] 695 1 T7 19 T14 15 T26 1
auto[1] auto[1] auto[1] auto[0] auto[1] auto[0] 956 1 T7 14 T9 1 T14 19
auto[1] auto[1] auto[1] auto[0] auto[1] auto[1] 698 1 T7 8 T14 12 T26 1
auto[1] auto[1] auto[1] auto[1] auto[0] auto[0] 1019 1 T7 22 T14 18 T26 2
auto[1] auto[1] auto[1] auto[1] auto[0] auto[1] 769 1 T7 15 T14 14 T26 2
auto[1] auto[1] auto[1] auto[1] auto[1] auto[0] 1012 1 T2 1 T7 24 T9 1
auto[1] auto[1] auto[1] auto[1] auto[1] auto[1] 763 1 T2 1 T7 18 T14 13

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