Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	478623	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

186320

1

T1

35

T2

7

T3

117

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	352292	1			T1	128		T2	12		T3	169
values[0x0]	156538	1			T1	32		T2	8		T3	81
values[0x1]	156113	1			T1	50		T2	6		T3	93

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	379090	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

285853

1

T1

77

T2

13

T3

172

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	5689	1			T1	12		T2	1		T8	6
valid_sources[0x01]	2239	1			T7	3		T8	9		T13	40
valid_sources[0x02]	2072	1			T13	33		T80	1		T24	1
valid_sources[0x03]	3134	1			T3	5		T8	1		T13	51
valid_sources[0x04]	2108	1			T1	2		T3	4		T8	9
valid_sources[0x05]	2130	1			T3	4		T7	1		T8	6
valid_sources[0x06]	2449	1			T3	1		T7	11		T8	3
valid_sources[0x07]	2233	1			T2	1		T8	4		T13	36
valid_sources[0x08]	3326	1			T3	1		T8	10		T13	33
valid_sources[0x09]	2247	1			T3	7		T7	9		T8	3
valid_sources[0x0a]	3478	1			T3	1		T7	2		T8	6
valid_sources[0x0b]	2099	1			T1	5		T3	1		T8	1
valid_sources[0x0c]	2175	1			T2	1		T8	2		T10	18
valid_sources[0x0d]	2275	1			T3	1		T8	11		T13	46
valid_sources[0x0e]	2087	1			T8	4		T13	45		T14	1
valid_sources[0x0f]	2256	1			T3	4		T8	2		T13	30
valid_sources[0x10]	2481	1			T1	1		T8	2		T13	43
valid_sources[0x11]	2342	1			T8	2		T13	23		T21	19
valid_sources[0x12]	2858	1			T3	4		T7	1		T8	1
valid_sources[0x13]	3013	1			T3	4		T8	3		T13	30
valid_sources[0x14]	2220	1			T3	2		T7	2		T8	5
valid_sources[0x15]	2259	1			T8	4		T13	41		T80	2
valid_sources[0x16]	3022	1			T3	1		T8	3		T13	32
valid_sources[0x17]	1910	1			T13	33		T21	20		T37	11
valid_sources[0x18]	3144	1			T1	1		T3	4		T13	39
valid_sources[0x19]	2666	1			T3	1		T8	2		T13	30
valid_sources[0x1a]	2387	1			T8	4		T13	35		T80	1
valid_sources[0x1b]	2149	1			T1	6		T8	3		T13	38
valid_sources[0x1c]	2111	1			T8	3		T13	30		T14	1
valid_sources[0x1d]	2279	1			T3	1		T8	3		T10	18
valid_sources[0x1e]	2500	1			T8	4		T10	18		T13	39
valid_sources[0x1f]	2938	1			T7	4		T8	2		T13	35
valid_sources[0x20]	2238	1			T3	4		T7	5		T8	3
valid_sources[0x21]	2160	1			T3	1		T8	2		T13	40
valid_sources[0x22]	2387	1			T3	2		T8	2		T13	45
valid_sources[0x23]	2011	1			T8	2		T13	45		T80	1
valid_sources[0x24]	2653	1			T3	4		T8	3		T13	27
valid_sources[0x25]	2234	1			T7	2		T8	2		T13	32
valid_sources[0x26]	2139	1			T3	1		T8	4		T13	31
valid_sources[0x27]	3104	1			T7	4		T10	18		T13	35
valid_sources[0x28]	2472	1			T13	37		T80	2		T14	1
valid_sources[0x29]	2586	1			T3	2		T7	2		T8	2
valid_sources[0x2a]	2181	1			T1	4		T3	3		T8	1
valid_sources[0x2b]	2640	1			T3	2		T7	3		T8	2
valid_sources[0x2c]	2148	1			T7	5		T8	5		T13	30
valid_sources[0x2d]	3751	1			T2	1		T8	1		T10	17
valid_sources[0x2e]	2998	1			T10	18		T13	41		T24	1
valid_sources[0x2f]	2373	1			T8	6		T13	35		T21	16
valid_sources[0x30]	2000	1			T2	1		T3	1		T8	4
valid_sources[0x31]	2264	1			T1	1		T3	1		T8	4
valid_sources[0x32]	2144	1			T1	1		T7	2		T8	5
valid_sources[0x33]	2412	1			T1	4		T3	2		T4	61
valid_sources[0x34]	2180	1			T3	1		T8	7		T13	30
valid_sources[0x35]	3260	1			T1	1		T7	3		T13	26
valid_sources[0x36]	2269	1			T1	3		T8	1		T13	37
valid_sources[0x37]	2186	1			T1	1		T3	2		T8	3
valid_sources[0x38]	2548	1			T3	1		T7	2		T8	1
valid_sources[0x39]	5040	1			T3	4		T8	2		T13	25
valid_sources[0x3a]	2158	1			T8	2		T13	42		T80	1
valid_sources[0x3b]	2779	1			T3	1		T8	2		T13	35
valid_sources[0x3c]	2139	1			T3	2		T7	1		T8	1
valid_sources[0x3d]	2269	1			T3	4		T13	37		T80	1
valid_sources[0x3e]	2849	1			T3	3		T8	10		T13	38
valid_sources[0x3f]	2211	1			T3	2		T8	6		T13	27
valid_sources[0x40]	2006	1			T3	1		T8	3		T13	44
valid_sources[0x41]	2400	1			T2	1		T3	1		T8	4
valid_sources[0x42]	2399	1			T7	1		T8	4		T13	41
valid_sources[0x43]	2030	1			T7	4		T8	2		T13	33
valid_sources[0x44]	2208	1			T3	2		T8	1		T13	29
valid_sources[0x45]	2885	1			T7	2		T8	1		T13	28
valid_sources[0x46]	3749	1			T8	5		T10	52		T13	39
valid_sources[0x47]	2328	1			T8	1		T13	47		T80	1
valid_sources[0x48]	2043	1			T8	3		T13	39		T21	24
valid_sources[0x49]	2469	1			T3	4		T7	2		T8	2
valid_sources[0x4a]	2236	1			T8	4		T13	25		T14	2
valid_sources[0x4b]	2590	1			T1	3		T3	1		T8	3
valid_sources[0x4c]	2211	1			T1	4		T2	1		T3	3
valid_sources[0x4d]	2433	1			T3	3		T7	8		T8	3
valid_sources[0x4e]	2125	1			T1	4		T3	1		T8	2
valid_sources[0x4f]	3194	1			T8	6		T13	42		T21	16
valid_sources[0x50]	2364	1			T3	4		T8	3		T13	35
valid_sources[0x51]	2317	1			T2	1		T3	1		T8	5
valid_sources[0x52]	2163	1			T8	2		T13	39		T14	2
valid_sources[0x53]	2233	1			T1	7		T3	2		T8	2
valid_sources[0x54]	4105	1			T1	5		T2	2		T3	2
valid_sources[0x55]	3240	1			T3	5		T13	39		T80	2
valid_sources[0x56]	2255	1			T3	1		T8	3		T13	36
valid_sources[0x57]	3988	1			T7	1		T8	2		T13	34
valid_sources[0x58]	1875	1			T1	1		T3	2		T8	8
valid_sources[0x59]	2517	1			T3	4		T8	5		T10	18
valid_sources[0x5a]	2132	1			T8	8		T13	27		T14	1
valid_sources[0x5b]	2561	1			T1	1		T3	1		T8	6
valid_sources[0x5c]	2318	1			T8	2		T13	39		T14	2
valid_sources[0x5d]	2400	1			T3	2		T8	2		T10	18
valid_sources[0x5e]	3039	1			T3	1		T8	2		T13	45
valid_sources[0x5f]	2321	1			T1	2		T2	1		T3	3
valid_sources[0x60]	2607	1			T8	4		T13	28		T80	3
valid_sources[0x61]	2308	1			T3	1		T8	2		T13	25
valid_sources[0x62]	2398	1			T8	2		T13	44		T14	1
valid_sources[0x63]	2336	1			T7	7		T8	4		T13	36
valid_sources[0x64]	2098	1			T8	4		T13	31		T24	1
valid_sources[0x65]	2059	1			T3	3		T13	26		T80	3
valid_sources[0x66]	2703	1			T8	5		T13	56		T24	2
valid_sources[0x67]	2506	1			T3	7		T8	1		T13	34
valid_sources[0x68]	2253	1			T3	1		T8	2		T13	25
valid_sources[0x69]	3772	1			T8	2		T13	29		T80	1
valid_sources[0x6a]	2250	1			T3	4		T8	9		T13	46
valid_sources[0x6b]	2266	1			T3	1		T7	2		T8	2
valid_sources[0x6c]	2147	1			T8	5		T13	39		T14	1
valid_sources[0x6d]	2401	1			T3	5		T8	7		T10	17
valid_sources[0x6e]	3088	1			T3	4		T13	42		T14	3
valid_sources[0x6f]	2594	1			T1	1		T3	8		T7	6
valid_sources[0x70]	2801	1			T3	1		T8	7		T13	30
valid_sources[0x71]	2531	1			T3	2		T7	9		T13	34
valid_sources[0x72]	2144	1			T1	2		T8	4		T13	34
valid_sources[0x73]	1957	1			T8	5		T13	48		T14	1
valid_sources[0x74]	2221	1			T3	13		T8	2		T13	30
valid_sources[0x75]	2772	1			T1	3		T3	1		T7	7
valid_sources[0x76]	2092	1			T3	4		T8	6		T13	35
valid_sources[0x77]	2142	1			T3	3		T7	1		T8	1
valid_sources[0x78]	2649	1			T3	2		T8	3		T13	40
valid_sources[0x79]	2121	1			T3	2		T7	5		T8	1
valid_sources[0x7a]	4914	1			T1	4		T3	1		T8	15
valid_sources[0x7b]	2250	1			T8	8		T13	38		T81	19
valid_sources[0x7c]	3383	1			T3	2		T8	4		T10	17
valid_sources[0x7d]	3167	1			T1	4		T3	2		T7	5
valid_sources[0x7e]	2231	1			T8	1		T13	38		T21	21
valid_sources[0x7f]	2455	1			T1	1		T2	1		T3	6
valid_sources[0x80]	2397	1			T1	4		T3	1		T7	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

96005

1

T1

12

T2

3

T3

58

values[0x0]

all_enables

biggest_size

58434

1

T1

14

T2

3

T3

35

values[0x1]

all_enables

biggest_size

31881

1

T1

9

T2

1

T3

24