SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING |
100.00 | 100.00 | 1 | 100 | 1 | 1 | 64 | 64 |
NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_rom_ctrl_done_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_rom_ctrl_good_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_sw_rst_req_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 35001 | 1 | T8 | 312 | T23 | 310 | T76 | 393 | ||||
others[1] | 35114 | 1 | T8 | 338 | T23 | 293 | T76 | 414 | ||||
others[2] | 34952 | 1 | T8 | 289 | T23 | 294 | T24 | 1 | ||||
others[3] | 58399 | 1 | T8 | 465 | T23 | 504 | T76 | 646 | ||||
false | 17925 | 1 | T6 | 30 | T8 | 50 | T10 | 20 | ||||
true | 27523 | 1 | T1 | 2 | T2 | 1 | T3 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 34945 | 1 | T8 | 294 | T23 | 308 | T76 | 406 | ||||
others[1] | 35011 | 1 | T8 | 302 | T23 | 308 | T76 | 379 | ||||
others[2] | 35350 | 1 | T8 | 292 | T23 | 271 | T76 | 423 | ||||
others[3] | 58160 | 1 | T8 | 509 | T23 | 502 | T76 | 666 | ||||
false | 11549 | 1 | T6 | 15 | T8 | 50 | T10 | 10 | ||||
true | 21204 | 1 | T1 | 2 | T2 | 1 | T3 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 673 | 1 | T1 | 3 | T4 | 1 | T7 | 4 | ||||
others[1] | 637 | 1 | T7 | 4 | T10 | 4 | T13 | 6 | ||||
others[2] | 684 | 1 | T1 | 1 | T7 | 6 | T13 | 11 | ||||
others[3] | 1137 | 1 | T1 | 2 | T7 | 10 | T10 | 3 | ||||
false | 12853 | 1 | T1 | 17 | T2 | 1 | T3 | 1 | ||||
true | 3761 | 1 | T1 | 9 | T4 | 2 | T7 | 1 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |