Unified Coverage Report :: Module :: pwrmgr_rstmgr_sva_if

Module : pwrmgr_rstmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_rstmgr_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.pwrmgr_rstmgr_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : pwrmgr_rstmgr_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	33	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv' or '../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
33	1	1

---

Cond Coverage for Module : pwrmgr_rstmgr_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       33
 EXPRESSION (((!rst_slow_ni)) || disable_sva)
             --------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T6
0	1	Covered	T1,T2,T3
1	0	Covered	T8,T13,T21

---

Assert Coverage for Module : pwrmgr_rstmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_assertions_per_power_domains[0].LcHandshakeOff_A	24100041	5830	0	0
gen_assertions_per_power_domains[0].LcHandshakeOn_A	24100041	260720	0	0
gen_assertions_per_power_domains[0].SysHandshakeOff_A	24100041	9845015	0	0
gen_assertions_per_power_domains[0].SysHandshakeOn_A	24100041	260722	0	0
gen_assertions_per_power_domains[1].LcHandshakeOff_A	24100041	5830	0	0
gen_assertions_per_power_domains[1].LcHandshakeOn_A	24100041	260720	0	0
gen_assertions_per_power_domains[1].SysHandshakeOff_A	24100041	9845015	0	0
gen_assertions_per_power_domains[1].SysHandshakeOn_A	24100041	260722	0	0

gen_assertions_per_power_domains[0].LcHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24100041	5830	0	0
T6	6719	6	0	0
T7	3482	0	0	0
T8	54552	16	0	0
T9	15827	0	0	0
T10	35003	4	0	0
T13	293287	55	0	0
T15	3320	0	0	0
T21	0	39	0	0
T23	27649	21	0	0
T37	0	9	0	0
T76	0	27	0	0
T77	0	6	0	0
T78	0	15	0	0
T79	4134	0	0	0
T80	16318	0	0	0

gen_assertions_per_power_domains[0].LcHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24100041	260720	0	0
T6	6719	147	0	0
T7	3482	0	0	0
T8	54552	1143	0	0
T9	15827	0	0	0
T10	35003	72	0	0
T13	293287	1786	0	0
T15	3320	0	0	0
T21	0	2298	0	0
T23	27649	672	0	0
T37	0	253	0	0
T76	0	1834	0	0
T77	0	211	0	0
T78	0	831	0	0
T79	4134	0	0	0
T80	16318	0	0	0

gen_assertions_per_power_domains[0].SysHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24100041	9845015	0	0
T2	1431	1109	0	0
T3	7436	3958	0	0
T4	1112	0	0	0
T5	2740	0	0	0
T6	6719	3072	0	0
T7	3482	0	0	0
T8	54552	24417	0	0
T9	15827	0	0	0
T10	35003	12380	0	0
T13	293287	128865	0	0
T23	0	16346	0	0
T79	0	2265	0	0
T80	0	9317	0	0
T81	0	1420	0	0

gen_assertions_per_power_domains[0].SysHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24100041	260722	0	0
T6	6719	147	0	0
T7	3482	0	0	0
T8	54552	1143	0	0
T9	15827	0	0	0
T10	35003	72	0	0
T13	293287	1794	0	0
T15	3320	0	0	0
T21	0	2298	0	0
T23	27649	672	0	0
T37	0	253	0	0
T76	0	1834	0	0
T77	0	211	0	0
T78	0	831	0	0
T79	4134	0	0	0
T80	16318	0	0	0

gen_assertions_per_power_domains[1].LcHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24100041	5830	0	0
T6	6719	6	0	0
T7	3482	0	0	0
T8	54552	16	0	0
T9	15827	0	0	0
T10	35003	4	0	0
T13	293287	55	0	0
T15	3320	0	0	0
T21	0	39	0	0
T23	27649	21	0	0
T37	0	9	0	0
T76	0	27	0	0
T77	0	6	0	0
T78	0	15	0	0
T79	4134	0	0	0
T80	16318	0	0	0

gen_assertions_per_power_domains[1].LcHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24100041	260720	0	0
T6	6719	147	0	0
T7	3482	0	0	0
T8	54552	1143	0	0
T9	15827	0	0	0
T10	35003	72	0	0
T13	293287	1786	0	0
T15	3320	0	0	0
T21	0	2298	0	0
T23	27649	672	0	0
T37	0	253	0	0
T76	0	1834	0	0
T77	0	211	0	0
T78	0	831	0	0
T79	4134	0	0	0
T80	16318	0	0	0

gen_assertions_per_power_domains[1].SysHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24100041	9845015	0	0
T2	1431	1109	0	0
T3	7436	3958	0	0
T4	1112	0	0	0
T5	2740	0	0	0
T6	6719	3072	0	0
T7	3482	0	0	0
T8	54552	24417	0	0
T9	15827	0	0	0
T10	35003	12380	0	0
T13	293287	128865	0	0
T23	0	16346	0	0
T79	0	2265	0	0
T80	0	9317	0	0
T81	0	1420	0	0

gen_assertions_per_power_domains[1].SysHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24100041	260722	0	0
T6	6719	147	0	0
T7	3482	0	0	0
T8	54552	1143	0	0
T9	15827	0	0	0
T10	35003	72	0	0
T13	293287	1794	0	0
T15	3320	0	0	0
T21	0	2298	0	0
T23	27649	672	0	0
T37	0	253	0	0
T76	0	1834	0	0
T77	0	211	0	0
T78	0	831	0	0
T79	4134	0	0	0
T80	16318	0	0	0