Unified Coverage Report :: Module :: pwrmgr_csr_assert_fpv

Module : pwrmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_pwrmgr_csr_assert_0/pwrmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.pwrmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : pwrmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	24663012	15491	0	0
intr_enable_rd_A	24663012	30524	0	0
reset_en_rd_A	24663012	1261	0	0
reset_en_regwen_rd_A	24663012	1132	0	0
wake_info_capture_dis_rd_A	24663012	1079	0	0
wakeup_en_rd_A	24663012	2318	0	0
wakeup_en_regwen_rd_A	24663012	1086	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24663012	15491	0	0
T13	293287	24	0	0
T14	2615	0	0	0
T15	3320	0	0	0
T21	179808	82	0	0
T22	0	47	0	0
T23	27649	0	0	0
T24	1971	0	0	0
T47	0	27	0	0
T79	4134	0	0	0
T80	16318	0	0	0
T81	1851	0	0	0
T82	0	99	0	0
T83	0	33	0	0
T86	1165	0	0	0
T87	0	1	0	0
T118	0	118	0	0
T119	0	27	0	0
T120	0	8	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24663012	30524	0	0
T14	2615	58	0	0
T15	3320	0	0	0
T21	179808	0	0	0
T24	1971	0	0	0
T37	34001	0	0	0
T44	0	180	0	0
T53	0	56	0	0
T79	4134	22	0	0
T80	16318	0	0	0
T81	1851	7	0	0
T86	1165	0	0	0
T91	2231	0	0	0
T94	0	39	0	0
T96	0	40	0	0
T115	0	25	0	0
T121	0	36	0	0
T122	0	61	0	0

reset_en_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24663012	1261	0	0
T45	0	23	0	0
T46	0	55	0	0
T71	0	6	0	0
T82	717427	0	0	0
T83	185820	0	0	0
T84	0	23	0	0
T90	0	9	0	0
T120	164161	2	0	0
T123	0	6	0	0
T124	0	1	0	0
T125	0	23	0	0
T126	0	4	0	0
T127	2221	0	0	0
T128	1717	0	0	0
T129	10572	0	0	0
T130	1443	0	0	0
T131	2151	0	0	0
T132	7547	0	0	0
T133	1702	0	0	0

reset_en_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24663012	1132	0	0
T45	0	21	0	0
T46	0	38	0	0
T57	0	21	0	0
T71	0	1	0	0
T82	717427	0	0	0
T83	185820	0	0	0
T84	0	27	0	0
T90	0	22	0	0
T120	164161	6	0	0
T125	0	19	0	0
T126	0	3	0	0
T127	2221	0	0	0
T128	1717	0	0	0
T129	10572	0	0	0
T130	1443	0	0	0
T131	2151	0	0	0
T132	7547	0	0	0
T133	1702	0	0	0
T134	0	3	0	0

wake_info_capture_dis_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24663012	1079	0	0
T26	45714	0	0	0
T45	0	14	0	0
T46	0	38	0	0
T84	186738	22	0	0
T90	0	13	0	0
T123	0	5	0	0
T124	0	8	0	0
T125	0	13	0	0
T126	0	1	0	0
T134	0	9	0	0
T135	0	9	0	0
T136	5458	0	0	0
T137	7227	0	0	0
T138	4180	0	0	0
T139	11019	0	0	0
T140	3134	0	0	0
T141	3723	0	0	0
T142	1763	0	0	0
T143	6425	0	0	0

wakeup_en_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24663012	2318	0	0
T45	0	6	0	0
T71	0	4	0	0
T82	717427	0	0	0
T83	185820	0	0	0
T84	0	20	0	0
T90	0	2	0	0
T120	164161	1	0	0
T123	0	7	0	0
T124	0	2	0	0
T125	0	9	0	0
T127	2221	0	0	0
T128	1717	0	0	0
T129	10572	0	0	0
T130	1443	0	0	0
T131	2151	0	0	0
T132	7547	0	0	0
T133	1702	0	0	0
T134	0	2	0	0
T135	0	8	0	0

wakeup_en_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24663012	1086	0	0
T26	45714	0	0	0
T46	0	40	0	0
T57	0	17	0	0
T71	0	6	0	0
T84	186738	18	0	0
T90	0	10	0	0
T123	0	9	0	0
T125	0	23	0	0
T126	0	18	0	0
T134	0	1	0	0
T136	5458	0	0	0
T137	7227	0	0	0
T138	4180	0	0	0
T139	11019	0	0	0
T140	3134	0	0	0
T141	3723	0	0	0
T142	1763	0	0	0
T143	6425	0	0	0
T144	0	6	0	0