Unified Coverage Report :: Module :: pwrmgr_fsm

Module : pwrmgr_fsm

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.66	100.00	98.44		94.87	100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_pwrmgr_component_0.1/rtl/pwrmgr_fsm.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_fsm	98.66	100.00	98.44		94.87	100.00	100.00

---

Module Instance : tb.dut.u_fsm

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.66	100.00	98.44		94.87	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.66	100.00	98.44		94.87	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_fetch_en	100.00	100.00				100.00
u_reg_lc_init	100.00	100.00				100.00
u_reg_otp_init	100.00	100.00				100.00
u_slow_sync_lc_done	100.00	100.00				100.00
u_state_regs	100.00	100.00				100.00	100.00
u_sync_lc_done	100.00	100.00				100.00
u_usb_ip_clk_en	100.00	100.00				100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : pwrmgr_fsm

	Line No.	Total	Covered	Percent
TOTAL		149	149	100.00
CONT_ASSIGN	122	1	1	100.00
CONT_ASSIGN	126	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00
CONT_ASSIGN	135	1	1	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	141	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	148	1	1	100.00
CONT_ASSIGN	153	1	1	100.00
ALWAYS	157	17	17	100.00
ALWAYS	179	3	3	100.00
ALWAYS	182	6	6	100.00
CONT_ASSIGN	197	1	1	100.00
CONT_ASSIGN	233	1	1	100.00
CONT_ASSIGN	240	1	1	100.00
CONT_ASSIGN	250	1	1	100.00
CONT_ASSIGN	256	1	1	100.00
CONT_ASSIGN	258	1	1	100.00
ALWAYS	261	97	97	100.00
CONT_ASSIGN	497	1	1	100.00
CONT_ASSIGN	498	1	1	100.00
CONT_ASSIGN	499	1	1	100.00
CONT_ASSIGN	501	1	1	100.00
CONT_ASSIGN	502	1	1	100.00
CONT_ASSIGN	503	1	1	100.00
CONT_ASSIGN	504	1	1	100.00
CONT_ASSIGN	508	1	1	100.00
CONT_ASSIGN	509	1	1	100.00
CONT_ASSIGN	519	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_pwrmgr_component_0.1/rtl/pwrmgr_fsm.sv' or '../src/lowrisc_ip_pwrmgr_component_0.1/rtl/pwrmgr_fsm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
122	1	1
126	1	1
129	1	1
132	1	1
135	1	1
138	1	1
141	1	1
145	1	1
148	1	1
153	1	1
157	1	1
158	1	1
159	1	1
160	1	1
161	1	1
162	1	1
163	1	1
164	1	1
165	1	1
167	1	1
168	1	1
169	1	1
170	1	1
171	1	1
172	1	1
173	1	1
174	1	1
179	3	3
182	1	1
183	1	1
184	1	1
185	1	1
186	1	1
187	1	1
			MISSING_ELSE
197	1	1
233	1	1
240	1	1
250	1	1
256	1	1
258	1	1
261	1	1
262	1	1
263	1	1
264	1	1
265	1	1
266	1	1
267	1	1
268	1	1
269	1	1
271	1	1
272	1	1
273	1	1
274	1	1
275	1	1
276	1	1
277	1	1
278	1	1
279	1	1
280	1	1
282	1	1
285	1	1
286	1	1
			MISSING_ELSE
291	1	1
292	1	1
293	1	1
			MISSING_ELSE
298	1	1
299	1	1
301	1	1
302	1	1
			MISSING_ELSE
307	1	1
309	1	1
310	1	1
			MISSING_ELSE
315	1	1
317	1	1
318	1	1
			MISSING_ELSE
325	1	1
328	1	1
329	1	1
330	1	1
333	1	1
335	1	1
336	1	1
			MISSING_ELSE
341	1	1
342	1	1
347	1	1
348	1	1
351	1	1
352	1	1
			MISSING_ELSE
357	1	1
358	1	1
			MISSING_ELSE
364	1	1
368	1	1
369	1	1
370	1	1
371	1	1
			MISSING_ELSE
376	1	1
378	1	1
379	1	1
380	1	1
383	1	1
384	1	1
390	1	1
393	1	1
394	1	1
395	1	1
396	1	1
397	1	1
399	1	1
405	1	1
406	1	1
408	1	1
409	1	1
410	1	1
411	1	1
417	1	1
422	1	1
423	1	1
424	1	1
427	1	1
428	1	1
			MISSING_ELSE
433	1	1
435	1	1
436	1	1
437	1	1
			MISSING_ELSE
443	1	1
444	1	1
445	1	1
449	1	1
450	1	1
451	1	1
458	1	1
462	1	1
463	1	1
474	1	1
475	1	1
			MISSING_ELSE
489	1	1
491	1	1
			MISSING_ELSE
497	1	1
498	1	1
499	1	1
501	1	1
502	1	1
503	1	1
504	1	1
508	1	1
509	1	1
519	1	1

---

Cond Coverage for Module : pwrmgr_fsm

	Total	Covered	Percent
Conditions	64	63	98.44
Logical	64	63	98.44
Non-Logical	0	0
Event	0	0

 LINE       122
 EXPRESSION ((pwr_rst_i.rst_lc_src_n[1] == '0) & (pwr_rst_i.rst_sys_src_n[1] == '0))
             ----------------1----------------   -----------------2----------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       122
 SUB-EXPRESSION (pwr_rst_i.rst_lc_src_n[1] == '0)
                ----------------1----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       122
 SUB-EXPRESSION (pwr_rst_i.rst_sys_src_n[1] == '0)
                -----------------1----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       126
 EXPRESSION (((rst_lc_req_q & (~pwr_rst_i.rst_lc_src_n)) | ((~rst_lc_req_q) & pwr_rst_i.rst_lc_src_n)) == {pwrmgr_pkg::PowerDomains {1'b1}})
            ----------------------------------------------------------------1---------------------------------------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       129
 EXPRESSION (((rst_sys_req_q & (~pwr_rst_i.rst_sys_src_n)) | ((~rst_sys_req_q) & pwr_rst_i.rst_sys_src_n)) == {pwrmgr_pkg::PowerDomains {1'b1}})
            ------------------------------------------------------------------1-----------------------------------------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (lc_rsts_valid & sys_rsts_valid)
             ------1------   -------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T2,T3

 LINE       141
 EXPRESSION (reset_reqs_i[pwrmgr_reg_pkg::ResetEscIdx] | reset_reqs_i[pwrmgr_reg_pkg::ResetMainPwrIdx])
             --------------------1--------------------   ----------------------2----------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T4,T6
1	0	Covered	T1,T4,T5

 LINE       153
 EXPRESSION ((reset_cause_q == LowPwrEntry) ? (main_pd_ni | pd_n_rsts_asserted) : ((reset_cause_q == HwReq) ? all_rsts_asserted : 1'b0))
             ---------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T6

 LINE       153
 SUB-EXPRESSION (reset_cause_q == LowPwrEntry)
                ---------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T6

 LINE       153
 SUB-EXPRESSION (main_pd_ni | pd_n_rsts_asserted)
                 -----1----   ---------2--------

-1-	-2-	Status	Tests
0	0	Covered	T3,T6,T8
0	1	Covered	T3,T6,T8
1	0	Covered	T2,T3,T6

 LINE       153
 SUB-EXPRESSION ((reset_cause_q == HwReq) ? all_rsts_asserted : 1'b0)
                 ------------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T4,T6

 LINE       153
 SUB-EXPRESSION (reset_cause_q == HwReq)
                ------------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T4,T6

 LINE       233
 EXPRESSION (ip_clk_en_q && ((&((ips_clk_en_o & clk_en_status_i) | (~ips_clk_en_o)))))
             -----1-----    ----------------------------2----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       240
 EXPRESSION (((~ip_clk_en_q)) && ((&(((~ips_clk_en_o) & (~clk_en_status_i)) | ips_clk_en_o))))
             --------1-------    ------------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       285
 EXPRESSION (req_pwrup_i || reset_ongoing_q)
             -----1-----    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T4,T6
1	0	Covered	T1,T2,T3

 LINE       328
 EXPRESSION (((!req_pwrup_i)) || reset_ongoing_q)
             --------1-------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T1,T2,T3

 LINE       333
 EXPRESSION ((pwrup_cause_i == Wake) & (reset_cause_q == LowPwrEntry))
             -----------1-----------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T6,T8,T10
1	0	Covered	T6,T8,T10
1	1	Covered	T2,T3,T6

 LINE       333
 SUB-EXPRESSION (pwrup_cause_i == Wake)
                -----------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T6

 LINE       333
 SUB-EXPRESSION (reset_cause_q == LowPwrEntry)
                ---------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T6

 LINE       368
 EXPRESSION (reset_req || low_power_entry_i)
             ----1----    --------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T6
1	0	Covered	T1,T4,T5

 LINE       379
 EXPRESSION (reset_req ? FastPwrStateNvmShutDown : FastPwrStateFallThrough)
             ----1----

-1-	Status	Tests
0	Covered	T2,T3,T6
1	Covered	T1,T4,T6

 LINE       383
 EXPRESSION (direct_rst_req ? FastPwrStateNvmShutDown : state_q)
             -------1------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T4,T5

 LINE       405
 EXPRESSION (otp_idle_i && lc_idle_i && flash_idle_i)
             -----1----    ----2----    ------3-----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T10,T13,T14
1	0	1	Covered	T10,T13,T21
1	1	0	Covered	T10,T13,T14
1	1	1	Covered	T2,T3,T6

 LINE       474
 EXPRESSION (reset_valid && ((!reset_reqs_i[pwrmgr_reg_pkg::ResetMainPwrIdx])))
             -----1-----    -------------------------2------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T6
1	0	Covered	T1,T4,T6
1	1	Covered	T1,T4,T6

 LINE       513
 EXPRESSION (ip_clk_en_d & usb_ip_clk_en_i)
             -----1-----   -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T6
1	1	Covered	T1,T2,T3

---

FSM Coverage for Module : pwrmgr_fsm

Summary for FSM :: state_q

	Total	Covered	Percent
States	19	19	100.00	(Not included in score)
Transitions	39	37	94.87
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FastPwrStateAckPwrUp	318	Covered	T1,T2,T3
FastPwrStateActive	358	Covered	T1,T2,T3
FastPwrStateDisClks	371	Covered	T1,T2,T3
FastPwrStateEnableClocks	286	Covered	T1,T2,T3
FastPwrStateFallThrough	379	Covered	T2,T3,T6
FastPwrStateInvalid	491	Covered	T41,T42,T43
FastPwrStateLcInit	310	Covered	T1,T2,T3
FastPwrStateLowPower	437	Covered	T1,T2,T3
FastPwrStateLowPowerPrep	406	Covered	T2,T3,T6
FastPwrStateNvmIdleChk	399	Covered	T2,T3,T6
FastPwrStateNvmShutDown	379	Covered	T1,T4,T6
FastPwrStateOtpInit	302	Covered	T1,T2,T3
FastPwrStateReleaseLcRst	293	Covered	T1,T2,T3
FastPwrStateReqPwrDn	428	Covered	T2,T3,T6
FastPwrStateResetPrep	445	Covered	T1,T4,T6
FastPwrStateResetWait	458	Covered	T1,T4,T6
FastPwrStateRomCheckDone	342	Covered	T1,T2,T3
FastPwrStateRomCheckGood	352	Covered	T1,T2,T3
FastPwrStateStrap	336	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
FastPwrStateAckPwrUp->FastPwrStateInvalid	491	Covered	T28,T32,T33
FastPwrStateAckPwrUp->FastPwrStateStrap	336	Covered	T1,T2,T3
FastPwrStateActive->FastPwrStateDisClks	371	Covered	T1,T2,T3
FastPwrStateActive->FastPwrStateInvalid	491	Covered	T18,T19,T20
FastPwrStateDisClks->FastPwrStateFallThrough	379	Covered	T2,T3,T6
FastPwrStateDisClks->FastPwrStateInvalid	491	Covered	T28,T32,T33
FastPwrStateDisClks->FastPwrStateNvmShutDown	379	Covered	T1,T4,T6
FastPwrStateEnableClocks->FastPwrStateInvalid	491	Covered	T28,T32,T33
FastPwrStateEnableClocks->FastPwrStateReleaseLcRst	293	Covered	T1,T2,T3
FastPwrStateFallThrough->FastPwrStateInvalid	491	Covered	T41,T42,T43
FastPwrStateFallThrough->FastPwrStateNvmIdleChk	399	Covered	T2,T3,T6
FastPwrStateFallThrough->FastPwrStateRomCheckDone	397	Covered	T10,T13,T14
FastPwrStateLcInit->FastPwrStateAckPwrUp	318	Covered	T1,T2,T3
FastPwrStateLcInit->FastPwrStateInvalid	491	Covered	T28,T32,T33
FastPwrStateLowPower->FastPwrStateEnableClocks	286	Covered	T1,T2,T3
FastPwrStateLowPower->FastPwrStateInvalid	491	Covered	T28,T32,T33
FastPwrStateLowPowerPrep->FastPwrStateInvalid	491	Covered	T41,T42,T43
FastPwrStateLowPowerPrep->FastPwrStateReqPwrDn	428	Covered	T2,T3,T6
FastPwrStateNvmIdleChk->FastPwrStateInvalid	491	Covered	T41,T42,T43
FastPwrStateNvmIdleChk->FastPwrStateLowPowerPrep	406	Covered	T2,T3,T6
FastPwrStateNvmIdleChk->FastPwrStateRomCheckDone	411	Covered	T10,T13,T14
FastPwrStateNvmShutDown->FastPwrStateInvalid	491	Covered	T28,T32,T33
FastPwrStateNvmShutDown->FastPwrStateResetPrep	445	Covered	T1,T4,T6
FastPwrStateOtpInit->FastPwrStateInvalid	491	Covered	T28,T32,T33
FastPwrStateOtpInit->FastPwrStateLcInit	310	Covered	T1,T2,T3
FastPwrStateReleaseLcRst->FastPwrStateInvalid	491	Covered	T28,T32,T33
FastPwrStateReleaseLcRst->FastPwrStateOtpInit	302	Covered	T1,T2,T3
FastPwrStateReqPwrDn->FastPwrStateInvalid	491	Covered	T41,T42,T43
FastPwrStateReqPwrDn->FastPwrStateLowPower	437	Covered	T2,T3,T6
FastPwrStateResetPrep->FastPwrStateInvalid	491	Covered	T28,T32,T33
FastPwrStateResetPrep->FastPwrStateResetWait	458	Covered	T1,T4,T6
FastPwrStateResetWait->FastPwrStateInvalid	491	Not Covered
FastPwrStateResetWait->FastPwrStateLowPower	475	Covered	T1,T4,T6
FastPwrStateRomCheckDone->FastPwrStateInvalid	491	Covered	T28,T32,T33
FastPwrStateRomCheckDone->FastPwrStateRomCheckGood	352	Covered	T1,T2,T3
FastPwrStateRomCheckGood->FastPwrStateActive	358	Covered	T1,T2,T3
FastPwrStateRomCheckGood->FastPwrStateInvalid	491	Not Covered
FastPwrStateStrap->FastPwrStateInvalid	491	Covered	T28,T32,T33
FastPwrStateStrap->FastPwrStateRomCheckDone	342	Covered	T1,T2,T3

---

Branch Coverage for Module : pwrmgr_fsm

	Line No.	Total	Covered	Percent
Branches		49	49	100.00
TERNARY	153	3	3	100.00
IF	157	2	2	100.00
IF	179	2	2	100.00
IF	182	4	4	100.00
CASE	282	36	36	100.00
IF	489	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_pwrmgr_component_0.1/rtl/pwrmgr_fsm.sv' or '../src/lowrisc_ip_pwrmgr_component_0.1/rtl/pwrmgr_fsm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	153	((reset_cause_q == LowPwrEntry)) ? 
-2-:	153	((reset_cause_q == HwReq)) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T2,T3,T6
0	1	Covered	T1,T4,T6
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	157	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	179	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	182	if ((!rst_ni))
-2-:	184	if ((&rst_sys_req_q))
-3-:	186	if (strap_o)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	282	case (state_q)
-2-:	285	if ((req_pwrup_i || reset_ongoing_q))
-3-:	292	if (clks_enabled)
-4-:	301	if ((&pwr_rst_i.rst_lc_src_n))
-5-:	309	if (otp_done_i)
-6-:	317	if (lc_done)
-7-:	328	if (((!req_pwrup_i) || reset_ongoing_q))
-8-:	351	if (prim_mubi_pkg::mubi4_test_true_strict(rom_intg_chk_done))
-9-:	357	if (prim_mubi_pkg::mubi4_test_true_strict(rom_intg_chk_good))
-10-:	368	if ((reset_req || low_power_entry_i))
-11-:	378	if (clks_disabled)
-12-:	379	(reset_req) ? 
-13-:	383	(direct_rst_req) ? 
-14-:	393	if ((!low_power_entry_i))
-15-:	405	if (((otp_idle_i && lc_idle_i) && flash_idle_i))
-16-:	427	if (reset_valid)
-17-:	435	if (ack_pwrdn_i)
-18-:	474	if ((reset_valid && (!reset_reqs_i[pwrmgr_reg_pkg::ResetMainPwrIdx])))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	-17-	-18-	Status	Tests
FastPwrStateLowPower	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
FastPwrStateLowPower	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
FastPwrStateEnableClocks	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
FastPwrStateEnableClocks	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
FastPwrStateReleaseLcRst	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
FastPwrStateReleaseLcRst	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
FastPwrStateOtpInit	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
FastPwrStateOtpInit	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
FastPwrStateLcInit	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
FastPwrStateLcInit	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
FastPwrStateAckPwrUp	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
FastPwrStateAckPwrUp	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
FastPwrStateStrap	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
FastPwrStateRomCheckDone	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
FastPwrStateRomCheckDone	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	Covered	T6,T8,T10
FastPwrStateRomCheckGood	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
FastPwrStateRomCheckGood	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	Covered	T24,T25,T44
FastPwrStateActive	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
FastPwrStateActive	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
FastPwrStateDisClks	-	-	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	Covered	T1,T4,T6
FastPwrStateDisClks	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	Covered	T2,T3,T6
FastPwrStateDisClks	-	-	-	-	-	-	-	-	-	0	-	1	-	-	-	-	-	Covered	T1,T4,T5
FastPwrStateDisClks	-	-	-	-	-	-	-	-	-	0	-	0	-	-	-	-	-	Covered	T1,T2,T3
FastPwrStateFallThrough	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T10,T13,T14
FastPwrStateFallThrough	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	Covered	T2,T3,T6
FastPwrStateNvmIdleChk	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	Covered	T2,T3,T6
FastPwrStateNvmIdleChk	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	Covered	T10,T13,T14
FastPwrStateLowPowerPrep	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T2,T3,T6
FastPwrStateLowPowerPrep	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	Covered	T2,T3,T6
FastPwrStateReqPwrDn	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T2,T3,T6
FastPwrStateReqPwrDn	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	Covered	T2,T3,T6
FastPwrStateNvmShutDown	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T4,T6
FastPwrStateResetPrep	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T4,T6
FastPwrStateResetWait	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T1,T4,T6
FastPwrStateResetWait	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T4,T6
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T41,T42,T43

	LineNo.	Expression
-1-:	489	if (fsm_invalid_i)

Branches:

-1-	Status	Tests
1	Covered	T41,T42,T43
0	Covered	T1,T2,T3

---

Assert Coverage for Module : pwrmgr_fsm

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AlwaysOnIndex_A	945	945	0	0
u_state_regs_A	24100041	23606256	0	0

AlwaysOnIndex_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	945	945	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24100041	23606256	0	0
T1	2119	1962	0	0
T2	1431	1335	0	0
T3	7436	7345	0	0
T4	1112	982	0	0
T5	2740	2387	0	0
T6	6719	6654	0	0
T7	3482	3418	0	0
T8	54552	54392	0	0
T9	15827	15727	0	0
T10	35003	33624	0	0