Unified Coverage Report :: Module :: clkmgr_pwrmgr_sva_if

Module : clkmgr_pwrmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_pwrmgr_sva_if_0.1/clkmgr_pwrmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_pwrmgr_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_pwrmgr_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : clkmgr_pwrmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
IoStatusFall_A	24100041	50087	0	0
IoStatusRise_A	24100041	55734	0	0
MainStatusFall_A	24100041	50087	0	0
MainStatusRise_A	24100041	55753	0	0
UsbStatusFall_A	24100041	34936	0	0
UsbStatusRise_A	24100041	39295	0	0

IoStatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24100041	50087	0	0
T1	2119	20	0	0
T2	1431	1	0	0
T3	7436	16	0	0
T4	1112	5	0	0
T5	2740	0	0	0
T6	6719	25	0	0
T7	3482	1	0	0
T8	54552	81	0	0
T9	15827	1	0	0
T10	35003	146	0	0
T13	0	762	0	0

IoStatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24100041	55734	0	0
T1	2119	22	0	0
T2	1431	2	0	0
T3	7436	17	0	0
T4	1112	7	0	0
T5	2740	5	0	0
T6	6719	26	0	0
T7	3482	2	0	0
T8	54552	83	0	0
T9	15827	2	0	0
T10	35003	165	0	0

MainStatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24100041	50087	0	0
T1	2119	20	0	0
T2	1431	1	0	0
T3	7436	16	0	0
T4	1112	5	0	0
T5	2740	0	0	0
T6	6719	25	0	0
T7	3482	1	0	0
T8	54552	81	0	0
T9	15827	1	0	0
T10	35003	146	0	0
T13	0	762	0	0

MainStatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24100041	55753	0	0
T1	2119	22	0	0
T2	1431	2	0	0
T3	7436	17	0	0
T4	1112	7	0	0
T5	2740	5	0	0
T6	6719	26	0	0
T7	3482	2	0	0
T8	54552	83	0	0
T9	15827	2	0	0
T10	35003	165	0	0

UsbStatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24100041	34936	0	0
T1	2119	20	0	0
T2	1431	1	0	0
T3	7436	10	0	0
T4	1112	5	0	0
T5	2740	0	0	0
T6	6719	9	0	0
T7	3482	1	0	0
T8	54552	48	0	0
T9	15827	1	0	0
T10	35003	121	0	0
T13	0	567	0	0

UsbStatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24100041	39295	0	0
T1	2119	22	0	0
T2	1431	1	0	0
T3	7436	11	0	0
T4	1112	7	0	0
T5	2740	5	0	0
T6	6719	10	0	0
T7	3482	2	0	0
T8	54552	50	0	0
T9	15827	2	0	0
T10	35003	133	0	0