Unified Coverage Report :: Module :: pwrmgr_sec_cm_checker_assert

Module : pwrmgr_sec_cm_checker_assert

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_sec_cm_checker_assert	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.pwrmgr_sec_cm_checker_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : pwrmgr_sec_cm_checker_assert

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	39	1	1	100.00
ALWAYS	40	1	1	100.00
ALWAYS	41	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv' or '../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
39	1	1
40	1	1
41	1	1

---

Cond Coverage for Module : pwrmgr_sec_cm_checker_assert

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       39
 EXPRESSION (((!rst_ni)) || disable_sva)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       40
 EXPRESSION (((!rst_esc_ni)) || disable_sva)
             -------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       41
 EXPRESSION (((!rst_slow_ni)) || disable_sva)
             --------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

---

Assert Coverage for Module : pwrmgr_sec_cm_checker_assert

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	10	10	100.00	10	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	10	10	100.00	10	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
RomAllowActiveState_A	24100041	55352	0	0
RomAllowCheckGoodState_A	24100041	55402	0	0
RomBlockActiveState_A	24100041	26877	0	0
RomBlockCheckGoodState_A	24100041	420266	0	0
RomIntgChkDisFalse_A	24100041	23485057	0	0
RomIntgChkDisTrue_A	24100041	121199	0	0
RstreqChkEsctimeout_A	24100041	4084	0	0
RstreqChkFsmterm_A	24100041	160	0	0
RstreqChkGlbesc_A	24100041	4084	0	0
RstreqChkMainpd_A	24100041	981231	0	0

RomAllowActiveState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24100041	55352	0	0
T1	2119	22	0	0
T2	1431	2	0	0
T3	7436	17	0	0
T4	1112	7	0	0
T5	2740	5	0	0
T6	6719	26	0	0
T7	3482	2	0	0
T8	54552	83	0	0
T9	15827	2	0	0
T10	35003	165	0	0

RomAllowCheckGoodState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24100041	55402	0	0
T1	2119	22	0	0
T2	1431	2	0	0
T3	7436	17	0	0
T4	1112	7	0	0
T5	2740	5	0	0
T6	6719	26	0	0
T7	3482	2	0	0
T8	54552	83	0	0
T9	15827	2	0	0
T10	35003	165	0	0

RomBlockActiveState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24100041	26877	0	0
T14	2615	0	0	0
T21	179808	0	0	0
T24	1971	83	0	0
T25	0	297	0	0
T37	34001	0	0	0
T38	2511	0	0	0
T39	1027	0	0	0
T44	0	15	0	0
T76	59174	0	0	0
T77	8276	0	0	0
T86	1165	0	0	0
T91	2231	0	0	0
T145	0	13	0	0
T146	0	181	0	0
T147	0	13	0	0
T148	0	16	0	0
T149	0	1521	0	0
T150	0	12	0	0
T151	0	274	0	0

RomBlockCheckGoodState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24100041	420266	0	0
T6	6719	342	0	0
T7	3482	0	0	0
T8	54552	4066	0	0
T9	15827	0	0	0
T10	35003	228	0	0
T13	293287	1765	0	0
T15	3320	0	0	0
T21	0	2106	0	0
T23	27649	2235	0	0
T24	0	62	0	0
T37	0	345	0	0
T76	0	4000	0	0
T77	0	297	0	0
T79	4134	0	0	0
T80	16318	0	0	0

RomIntgChkDisFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24100041	23485057	0	0
T1	2119	1962	0	0
T2	1431	1335	0	0
T3	7436	7345	0	0
T4	1112	982	0	0
T5	2740	2387	0	0
T6	6719	6654	0	0
T7	3482	3418	0	0
T8	54552	52396	0	0
T9	15827	15727	0	0
T10	35003	33624	0	0

RomIntgChkDisTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24100041	121199	0	0
T8	54552	1996	0	0
T9	15827	0	0	0
T10	35003	0	0	0
T13	293287	0	0	0
T15	3320	0	0	0
T23	27649	1501	0	0
T24	1971	931	0	0
T25	0	168	0	0
T44	0	289	0	0
T79	4134	0	0	0
T80	16318	0	0	0
T81	1851	0	0	0
T146	0	29	0	0
T147	0	465	0	0
T149	0	1426	0	0
T151	0	674	0	0
T152	0	1328	0	0

RstreqChkEsctimeout_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24100041	4084	0	0
T1	2119	9	0	0
T2	1431	0	0	0
T3	7436	0	0	0
T4	1112	4	0	0
T5	2740	4	0	0
T6	6719	0	0	0
T7	3482	0	0	0
T8	54552	0	0	0
T9	15827	1	0	0
T10	35003	29	0	0
T13	0	87	0	0
T21	0	11	0	0
T24	0	3	0	0
T37	0	10	0	0
T39	0	1	0	0

RstreqChkFsmterm_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24100041	160	0	0
T18	8852	20	0	0
T19	0	40	0	0
T20	0	20	0	0
T26	0	40	0	0
T27	0	40	0	0
T28	6806	0	0	0
T29	2728	0	0	0
T30	1390	0	0	0
T31	2845	0	0	0
T32	7604	0	0	0
T33	4588	0	0	0
T34	3253	0	0	0
T35	8165	0	0	0
T36	1164	0	0	0

RstreqChkGlbesc_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24100041	4084	0	0
T1	2119	9	0	0
T2	1431	0	0	0
T3	7436	0	0	0
T4	1112	4	0	0
T5	2740	4	0	0
T6	6719	0	0	0
T7	3482	0	0	0
T8	54552	0	0	0
T9	15827	1	0	0
T10	35003	29	0	0
T13	0	87	0	0
T21	0	11	0	0
T24	0	3	0	0
T37	0	10	0	0
T39	0	1	0	0

RstreqChkMainpd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24100041	981231	0	0
T1	2119	160	0	0
T2	1431	0	0	0
T3	7436	0	0	0
T4	1112	44	0	0
T5	2740	0	0	0
T6	6719	430	0	0
T7	3482	0	0	0
T8	54552	4346	0	0
T9	15827	0	0	0
T10	35003	879	0	0
T13	0	8179	0	0
T15	0	17	0	0
T23	0	2268	0	0
T24	0	66	0	0
T86	0	10	0	0