Unified Coverage Report :: Group :: pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

Group : pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_env_0.1/pwrmgr_env_cov.sv

---

Summary for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	64	0	64	100.00

Variables for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
core_cp	2	0	2	100.00	100	1	1	2
io_cp	2	0	2	100.00	100	1	1	2
main_pd_n_cp	2	0	2	100.00	100	1	1	2
sleep_cp	2	0	2	100.00	100	1	1	2
usb_active_cp	2	0	2	100.00	100	1	1	2
usb_lp_cp	2	0	2	100.00	100	1	1	2

Crosses for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
control_cross	64	0	64	100.00	100	1	1	0

Summary for Variable core_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for core_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

30829

1

T1

26

T2

20

T3

66

auto[1]

29564

1

T1

10

T2

12

T3

34

---

Summary for Variable io_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for io_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

30981

1

T1

20

T2

20

T3

48

auto[1]

29412

1

T1

16

T2

12

T3

52

---

Summary for Variable main_pd_n_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for main_pd_n_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

29422

1

T1

18

T2

20

T3

40

auto[1]

30971

1

T1

18

T2

12

T3

60

---

Summary for Variable sleep_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sleep_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

34381

1

T1

18

T2

16

T3

50

auto[1]

26012

1

T1

18

T2

16

T3

50

---

Summary for Variable usb_active_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for usb_active_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

29669

1

T1

18

T2

14

T3

54

auto[1]

30724

1

T1

18

T2

18

T3

46

---

Summary for Variable usb_lp_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for usb_lp_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

30664

1

T1

18

T2

18

T3

64

auto[1]

29729

1

T1

18

T2

14

T3

36

---

Summary for Cross control_cross

Samples crossed: core_cp io_cp usb_lp_cp usb_active_cp main_pd_n_cp sleep_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for control_cross

Bins

core_cp

io_cp

usb_lp_cp

usb_active_cp

main_pd_n_cp

sleep_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

1069

1

T2

1

T3

2

T32

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

814

1

T2

1

T3

2

T32

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

1090

1

T1

1

T2

1

T3

3

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

793

1

T1

1

T2

1

T3

3

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

1028

1

T1

1

T4

1

T32

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

782

1

T1

1

T22

7

T51

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

1690

1

T1

1

T2

2

T3

3

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

1414

1

T1

1

T2

2

T3

3

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

1024

1

T1

2

T2

1

T3

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

763

1

T1

2

T2

1

T3

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

1074

1

T3

2

T15

1

T32

3

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

829

1

T3

2

T32

2

T22

10

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

1026

1

T2

2

T3

1

T16

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

755

1

T2

2

T3

1

T22

10

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

1071

1

T2

1

T3

1

T32

5

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

799

1

T2

1

T3

1

T32

3

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

1031

1

T1

1

T3

3

T7

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

795

1

T1

1

T3

3

T7

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

1003

1

T1

2

T3

5

T4

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

771

1

T1

2

T3

5

T32

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

1050

1

T2

1

T32

4

T22

17

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

793

1

T2

1

T32

2

T22

8

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

1026

1

T3

5

T7

1

T16

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

791

1

T3

5

T7

1

T22

16

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

1070

1

T3

2

T7

1

T16

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

804

1

T3

2

T7

1

T32

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

1075

1

T1

1

T3

1

T7

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

817

1

T1

1

T3

1

T7

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

1078

1

T1

3

T2

1

T3

3

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

814

1

T1

3

T2

1

T3

3

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

1087

1

T1

1

T3

1

T16

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

803

1

T1

1

T3

1

T32

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

1065

1

T1

1

T2

1

T3

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

804

1

T1

1

T2

1

T3

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

1064

1

T3

3

T7

1

T10

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

803

1

T3

3

T7

1

T10

1

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

1051

1

T1

1

T3

2

T4

1

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

800

1

T1

1

T3

2

T32

4

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

1084

1

T1

1

T3

2

T16

1

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

814

1

T1

1

T3

2

T32

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

1099

1

T2

1

T7

1

T32

2

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

829

1

T2

1

T7

1

T32

2

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

1077

1

T1

1

T3

1

T4

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

834

1

T1

1

T3

1

T32

3

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

1039

1

T3

1

T7

2

T22

16

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

766

1

T3

1

T7

2

T22

8

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

1046

1

T1

1

T3

1

T7

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

785

1

T1

1

T3

1

T7

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

1052

1

T2

1

T3

1

T4

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

777

1

T2

1

T3

1

T7

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

1041

1

T2

1

T4

1

T7

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

759

1

T2

1

T7

1

T32

1

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

1007

1

T2

1

T3

1

T16

1

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

767

1

T2

1

T3

1

T22

9

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

1055

1

T3

1

T32

1

T22

17

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

781

1

T3

1

T32

1

T22

8

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

1018

1

T3

2

T16

1

T32

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

790

1

T3

2

T22

8

T51

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

1041

1

T16

1

T32

2

T22

16

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

794

1

T32

1

T22

10

T25

3

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

1074

1

T4

1

T16

3

T32

3

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

788

1

T32

1

T22

11

T25

2

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

1076

1

T2

1

T3

1

T15

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

784

1

T2

1

T3

1

T32

2