Group : pwrmgr_env_pkg::pwrmgr_env_cov::hw_reset_0_cg
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Group : pwrmgr_env_pkg::pwrmgr_env_cov::hw_reset_0_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_env_0.1/pwrmgr_env_cov.sv


Summary for Group pwrmgr_env_pkg::pwrmgr_env_cov::hw_reset_0_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 6 0 6 100.00
Crosses 6 0 6 100.00


Variables for Group pwrmgr_env_pkg::pwrmgr_env_cov::hw_reset_0_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
enable_cp 2 0 2 100.00 100 1 1 2
reset_cp 2 0 2 100.00 100 1 1 2
sleep_cp 2 0 2 100.00 100 1 1 2


Crosses for Group pwrmgr_env_pkg::pwrmgr_env_cov::hw_reset_0_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
reset_cross 6 0 6 100.00 100 1 1 0


Summary for Variable enable_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for enable_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 16144 1 T1 7 T3 33 T6 2
auto[1] 24800 1 T1 25 T3 53 T6 5


Summary for Variable reset_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for reset_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 34367 1 T1 22 T2 16 T3 58
auto[1] 9164 1 T1 10 T3 28 T6 5


Summary for Variable sleep_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for sleep_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 17629 1 T1 14 T3 36 T6 7
auto[1] 25902 1 T1 18 T2 16 T3 50


Summary for Cross reset_cross

Samples crossed: reset_cp enable_cp sleep_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 6 0 6 100.00
Automatically Generated Cross Bins 6 0 6 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for reset_cross

Bins
reset_cpenable_cpsleep_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] auto[0] 3909 1 T3 6 T6 1 T9 3
auto[0] auto[0] auto[1] 8990 1 T1 4 T3 20 T32 7
auto[0] auto[1] auto[0] 4272 1 T1 4 T3 2 T6 1
auto[0] auto[1] auto[1] 14609 1 T1 14 T3 30 T10 1
auto[1] auto[0] auto[0] 3245 1 T1 3 T3 7 T6 1
auto[1] auto[1] auto[0] 5919 1 T1 7 T3 21 T6 4


User Defined Cross Bins for reset_cross

Excluded/Illegal bins
NAMECOUNTSTATUS
illegal 0 Illegal

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%