Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	437656	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

168417

1

T1

32

T2

1

T3

21

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	316270	1			T1	63		T2	1		T3	82
values[0x0]	144706	1			T1	13		T3	26		T4	4
values[0x1]	145097	1			T1	9		T3	24		T4	6

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	346313	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

259760

1

T1

45

T2

1

T3

46

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	2570	1			T7	91		T8	66		T37	1
valid_sources[0x01]	2465	1			T8	57		T13	2		T62	1
valid_sources[0x02]	2910	1			T8	41		T10	5		T37	3
valid_sources[0x03]	2090	1			T8	58		T10	1		T13	1
valid_sources[0x04]	1915	1			T8	43		T13	1		T56	1
valid_sources[0x05]	2069	1			T1	1		T8	45		T35	1
valid_sources[0x06]	1960	1			T8	42		T13	6		T62	1
valid_sources[0x07]	2376	1			T7	17		T8	69		T13	5
valid_sources[0x08]	1784	1			T8	50		T10	3		T13	2
valid_sources[0x09]	2014	1			T8	46		T35	1		T13	7
valid_sources[0x0a]	2287	1			T1	1		T8	53		T35	3
valid_sources[0x0b]	3101	1			T8	61		T35	1		T14	6
valid_sources[0x0c]	1866	1			T8	53		T9	2		T13	1
valid_sources[0x0d]	1950	1			T8	49		T13	1		T62	2
valid_sources[0x0e]	2115	1			T8	51		T9	1		T35	2
valid_sources[0x0f]	2380	1			T7	47		T8	49		T14	3
valid_sources[0x10]	1954	1			T8	55		T13	1		T62	1
valid_sources[0x11]	1830	1			T8	44		T37	7		T14	1
valid_sources[0x12]	4667	1			T1	1		T8	64		T14	4
valid_sources[0x13]	3280	1			T8	56		T35	1		T14	3
valid_sources[0x14]	1929	1			T1	1		T8	46		T13	2
valid_sources[0x15]	1966	1			T1	1		T8	54		T9	1
valid_sources[0x16]	2000	1			T8	57		T35	1		T13	1
valid_sources[0x17]	2279	1			T8	54		T62	2		T14	8
valid_sources[0x18]	1998	1			T1	1		T8	46		T10	1
valid_sources[0x19]	4109	1			T8	44		T62	2		T14	4
valid_sources[0x1a]	2819	1			T8	50		T35	1		T13	4
valid_sources[0x1b]	2000	1			T8	49		T35	1		T13	3
valid_sources[0x1c]	2239	1			T8	50		T35	3		T62	2
valid_sources[0x1d]	1986	1			T8	50		T13	4		T62	1
valid_sources[0x1e]	1849	1			T8	37		T14	2		T73	1
valid_sources[0x1f]	2357	1			T8	62		T35	1		T14	16
valid_sources[0x20]	2005	1			T8	55		T35	2		T13	1
valid_sources[0x21]	1974	1			T8	75		T10	19		T13	11
valid_sources[0x22]	2521	1			T8	49		T13	1		T14	5
valid_sources[0x23]	2079	1			T8	54		T35	1		T62	1
valid_sources[0x24]	2589	1			T8	50		T62	1		T37	17
valid_sources[0x25]	2773	1			T8	48		T13	3		T14	10
valid_sources[0x26]	2205	1			T1	1		T8	57		T14	5
valid_sources[0x27]	1957	1			T8	56		T35	2		T13	3
valid_sources[0x28]	2517	1			T8	58		T13	1		T62	1
valid_sources[0x29]	3255	1			T8	57		T13	1		T62	1
valid_sources[0x2a]	3025	1			T1	1		T8	66		T9	4
valid_sources[0x2b]	5070	1			T8	35		T35	1		T62	1
valid_sources[0x2c]	6319	1			T8	51		T35	1		T13	1
valid_sources[0x2d]	1953	1			T1	2		T8	46		T13	1
valid_sources[0x2e]	2820	1			T8	39		T9	1		T13	2
valid_sources[0x2f]	3813	1			T8	59		T14	7		T38	5
valid_sources[0x30]	1954	1			T8	62		T62	2		T14	6
valid_sources[0x31]	2266	1			T8	54		T35	2		T13	1
valid_sources[0x32]	2408	1			T8	54		T35	1		T13	4
valid_sources[0x33]	2025	1			T2	1		T8	49		T56	1
valid_sources[0x34]	1975	1			T1	1		T8	54		T35	1
valid_sources[0x35]	3167	1			T7	18		T8	51		T10	3
valid_sources[0x36]	2110	1			T8	44		T14	3		T38	7
valid_sources[0x37]	2286	1			T8	52		T13	2		T56	1
valid_sources[0x38]	1947	1			T8	64		T13	8		T62	3
valid_sources[0x39]	1849	1			T8	58		T13	2		T62	1
valid_sources[0x3a]	2033	1			T5	5		T7	17		T8	56
valid_sources[0x3b]	1941	1			T8	38		T13	2		T56	2
valid_sources[0x3c]	2289	1			T1	1		T8	63		T9	2
valid_sources[0x3d]	2003	1			T8	56		T13	1		T62	1
valid_sources[0x3e]	3995	1			T8	45		T10	4		T35	1
valid_sources[0x3f]	2110	1			T8	42		T35	1		T13	2
valid_sources[0x40]	2363	1			T8	44		T62	3		T14	3
valid_sources[0x41]	1851	1			T7	32		T8	40		T13	1
valid_sources[0x42]	1987	1			T1	2		T8	55		T10	1
valid_sources[0x43]	2521	1			T8	60		T62	1		T37	1
valid_sources[0x44]	1863	1			T8	44		T13	2		T14	4
valid_sources[0x45]	1692	1			T1	1		T8	62		T14	3
valid_sources[0x46]	2098	1			T1	1		T8	55		T35	2
valid_sources[0x47]	1817	1			T1	1		T8	55		T13	1
valid_sources[0x48]	2225	1			T1	2		T8	68		T62	1
valid_sources[0x49]	1823	1			T8	52		T35	1		T62	1
valid_sources[0x4a]	2210	1			T8	52		T35	1		T14	5
valid_sources[0x4b]	2093	1			T8	41		T37	9		T14	3
valid_sources[0x4c]	2462	1			T1	1		T8	50		T62	1
valid_sources[0x4d]	2160	1			T8	48		T13	1		T62	1
valid_sources[0x4e]	2180	1			T8	52		T14	12		T168	1
valid_sources[0x4f]	2597	1			T8	41		T62	1		T38	7
valid_sources[0x50]	2270	1			T1	1		T8	49		T37	6
valid_sources[0x51]	1993	1			T8	59		T14	3		T72	14
valid_sources[0x52]	1984	1			T8	42		T62	1		T56	1
valid_sources[0x53]	2790	1			T8	63		T35	2		T13	6
valid_sources[0x54]	2006	1			T8	62		T9	4		T13	3
valid_sources[0x55]	2483	1			T8	45		T35	1		T13	1
valid_sources[0x56]	2076	1			T8	48		T13	1		T62	1
valid_sources[0x57]	2918	1			T8	53		T13	1		T37	5
valid_sources[0x58]	2013	1			T4	27		T8	39		T35	1
valid_sources[0x59]	1982	1			T8	47		T35	1		T13	1
valid_sources[0x5a]	1855	1			T1	2		T8	51		T13	2
valid_sources[0x5b]	1883	1			T8	57		T37	1		T14	8
valid_sources[0x5c]	2170	1			T1	1		T3	132		T8	64
valid_sources[0x5d]	2115	1			T8	58		T10	6		T35	1
valid_sources[0x5e]	1855	1			T8	55		T13	1		T37	2
valid_sources[0x5f]	2700	1			T8	46		T13	2		T62	2
valid_sources[0x60]	3544	1			T8	46		T13	1		T37	2
valid_sources[0x61]	1843	1			T8	54		T13	2		T73	2
valid_sources[0x62]	1949	1			T8	39		T13	2		T62	3
valid_sources[0x63]	2166	1			T8	57		T35	1		T62	1
valid_sources[0x64]	1945	1			T8	49		T35	2		T13	1
valid_sources[0x65]	1796	1			T8	60		T13	2		T62	2
valid_sources[0x66]	2441	1			T8	50		T35	1		T14	8
valid_sources[0x67]	2066	1			T8	46		T35	1		T13	5
valid_sources[0x68]	1911	1			T7	17		T8	46		T62	4
valid_sources[0x69]	2562	1			T1	2		T8	41		T35	2
valid_sources[0x6a]	1933	1			T8	59		T13	1		T14	1
valid_sources[0x6b]	1985	1			T8	42		T62	1		T14	6
valid_sources[0x6c]	1963	1			T8	58		T35	1		T14	3
valid_sources[0x6d]	5191	1			T8	39		T35	1		T13	3
valid_sources[0x6e]	1993	1			T1	2		T8	44		T14	8
valid_sources[0x6f]	1925	1			T8	38		T35	2		T14	3
valid_sources[0x70]	1935	1			T8	49		T13	2		T36	1
valid_sources[0x71]	2206	1			T7	29		T8	38		T10	2
valid_sources[0x72]	3507	1			T8	48		T9	1		T13	2
valid_sources[0x73]	1782	1			T8	61		T62	1		T14	2
valid_sources[0x74]	1966	1			T1	1		T8	35		T10	5
valid_sources[0x75]	2139	1			T8	30		T35	1		T13	1
valid_sources[0x76]	1903	1			T8	56		T10	9		T13	1
valid_sources[0x77]	2857	1			T1	1		T8	54		T13	2
valid_sources[0x78]	2063	1			T8	56		T9	1		T35	1
valid_sources[0x79]	4138	1			T8	50		T9	1		T35	2
valid_sources[0x7a]	3155	1			T8	58		T35	2		T14	10
valid_sources[0x7b]	2328	1			T1	1		T8	53		T10	2
valid_sources[0x7c]	2129	1			T1	2		T8	43		T9	1
valid_sources[0x7d]	2401	1			T8	50		T13	2		T62	1
valid_sources[0x7e]	1994	1			T8	35		T35	1		T62	2
valid_sources[0x7f]	1975	1			T8	48		T35	1		T62	2
valid_sources[0x80]	2114	1			T1	1		T8	52		T14	3

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

85021

1

T1

23

T2

1

T3

10

values[0x0]

all_enables

biggest_size

53972

1

T1

7

T3

6

T4

2

values[0x1]

all_enables

biggest_size

29424

1

T1

2

T3

5

T4

2