SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING |
100.00 | 100.00 | 1 | 100 | 1 | 1 | 64 | 64 |
NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_rom_ctrl_done_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_rom_ctrl_good_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_sw_rst_req_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 35193 | 1 | T1 | 1 | T21 | 1 | T23 | 313 | ||||
others[1] | 35113 | 1 | T21 | 1 | T23 | 315 | T131 | 310 | ||||
others[2] | 34977 | 1 | T1 | 1 | T23 | 298 | T131 | 303 | ||||
others[3] | 58219 | 1 | T23 | 478 | T131 | 487 | T132 | 710 | ||||
false | 17349 | 1 | T1 | 3 | T6 | 3 | T7 | 44 | ||||
true | 26432 | 1 | T1 | 4 | T2 | 2 | T3 | 2 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 34999 | 1 | T6 | 1 | T23 | 302 | T131 | 283 | ||||
others[1] | 35008 | 1 | T1 | 2 | T21 | 1 | T23 | 278 | ||||
others[2] | 35385 | 1 | T21 | 1 | T23 | 298 | T131 | 314 | ||||
others[3] | 58278 | 1 | T21 | 1 | T23 | 528 | T131 | 502 | ||||
false | 11265 | 1 | T1 | 3 | T6 | 3 | T7 | 22 | ||||
true | 20420 | 1 | T1 | 6 | T2 | 2 | T3 | 2 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 582 | 1 | T7 | 2 | T8 | 11 | T10 | 2 | ||||
others[1] | 560 | 1 | T3 | 1 | T6 | 1 | T7 | 2 | ||||
others[2] | 578 | 1 | T1 | 1 | T3 | 2 | T8 | 7 | ||||
others[3] | 949 | 1 | T1 | 1 | T7 | 1 | T8 | 13 | ||||
false | 11111 | 1 | T1 | 6 | T2 | 2 | T3 | 10 | ||||
true | 3004 | 1 | T1 | 3 | T3 | 5 | T6 | 3 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |