Unified Coverage Report :: Module :: pwrmgr_rstmgr_sva_if

Module : pwrmgr_rstmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_rstmgr_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.pwrmgr_rstmgr_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : pwrmgr_rstmgr_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	33	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv' or '../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
33	1	1

---

Cond Coverage for Module : pwrmgr_rstmgr_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       33
 EXPRESSION (((!rst_slow_ni)) || disable_sva)
             --------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T7
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T7,T8

---

Assert Coverage for Module : pwrmgr_rstmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_assertions_per_power_domains[0].LcHandshakeOff_A	21646800	5687	0	0
gen_assertions_per_power_domains[0].LcHandshakeOn_A	21646800	243648	0	0
gen_assertions_per_power_domains[0].SysHandshakeOff_A	21646800	9011419	0	0
gen_assertions_per_power_domains[0].SysHandshakeOn_A	21646800	243649	0	0
gen_assertions_per_power_domains[1].LcHandshakeOff_A	21646800	5687	0	0
gen_assertions_per_power_domains[1].LcHandshakeOn_A	21646800	243648	0	0
gen_assertions_per_power_domains[1].SysHandshakeOff_A	21646800	9011419	0	0
gen_assertions_per_power_domains[1].SysHandshakeOn_A	21646800	243649	0	0

gen_assertions_per_power_domains[0].LcHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21646800	5687	0	0
T4	1632	1	0	0
T5	1925	2	0	0
T6	2215	0	0	0
T7	19395	13	0	0
T8	299326	83	0	0
T9	3421	2	0	0
T10	5170	0	0	0
T13	10484	0	0	0
T14	0	14	0	0
T35	5223	0	0	0
T37	0	5	0	0
T38	0	10	0	0
T62	17375	0	0	0
T72	0	4	0	0
T73	0	9	0	0

gen_assertions_per_power_domains[0].LcHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21646800	243648	0	0
T4	1632	12	0	0
T5	1925	245	0	0
T6	2215	0	0	0
T7	19395	354	0	0
T8	299326	1622	0	0
T9	3421	490	0	0
T10	5170	0	0	0
T13	10484	0	0	0
T14	0	856	0	0
T35	5223	0	0	0
T37	0	242	0	0
T38	0	249	0	0
T62	17375	0	0	0
T72	0	392	0	0
T73	0	188	0	0

gen_assertions_per_power_domains[0].SysHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21646800	9011419	0	0
T4	1632	1143	0	0
T5	1925	729	0	0
T6	2215	0	0	0
T7	19395	7649	0	0
T8	299326	132403	0	0
T9	3421	1078	0	0
T10	5170	0	0	0
T13	10484	3731	0	0
T14	0	35349	0	0
T35	5223	0	0	0
T37	0	4115	0	0
T62	17375	9571	0	0
T72	0	7777	0	0

gen_assertions_per_power_domains[0].SysHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21646800	243649	0	0
T4	1632	12	0	0
T5	1925	245	0	0
T6	2215	0	0	0
T7	19395	354	0	0
T8	299326	1622	0	0
T9	3421	490	0	0
T10	5170	0	0	0
T13	10484	0	0	0
T14	0	856	0	0
T35	5223	0	0	0
T37	0	242	0	0
T38	0	249	0	0
T62	17375	0	0	0
T72	0	392	0	0
T73	0	188	0	0

gen_assertions_per_power_domains[1].LcHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21646800	5687	0	0
T4	1632	1	0	0
T5	1925	2	0	0
T6	2215	0	0	0
T7	19395	13	0	0
T8	299326	83	0	0
T9	3421	2	0	0
T10	5170	0	0	0
T13	10484	0	0	0
T14	0	14	0	0
T35	5223	0	0	0
T37	0	5	0	0
T38	0	10	0	0
T62	17375	0	0	0
T72	0	4	0	0
T73	0	9	0	0

gen_assertions_per_power_domains[1].LcHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21646800	243648	0	0
T4	1632	12	0	0
T5	1925	245	0	0
T6	2215	0	0	0
T7	19395	354	0	0
T8	299326	1622	0	0
T9	3421	490	0	0
T10	5170	0	0	0
T13	10484	0	0	0
T14	0	856	0	0
T35	5223	0	0	0
T37	0	242	0	0
T38	0	249	0	0
T62	17375	0	0	0
T72	0	392	0	0
T73	0	188	0	0

gen_assertions_per_power_domains[1].SysHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21646800	9011419	0	0
T4	1632	1143	0	0
T5	1925	729	0	0
T6	2215	0	0	0
T7	19395	7649	0	0
T8	299326	132403	0	0
T9	3421	1078	0	0
T10	5170	0	0	0
T13	10484	3731	0	0
T14	0	35349	0	0
T35	5223	0	0	0
T37	0	4115	0	0
T62	17375	9571	0	0
T72	0	7777	0	0

gen_assertions_per_power_domains[1].SysHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21646800	243649	0	0
T4	1632	12	0	0
T5	1925	245	0	0
T6	2215	0	0	0
T7	19395	354	0	0
T8	299326	1622	0	0
T9	3421	490	0	0
T10	5170	0	0	0
T13	10484	0	0	0
T14	0	856	0	0
T35	5223	0	0	0
T37	0	242	0	0
T38	0	249	0	0
T62	17375	0	0	0
T72	0	392	0	0
T73	0	188	0	0