Unified Coverage Report :: Module :: pwrmgr_csr_assert_fpv

Module : pwrmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_pwrmgr_csr_assert_0/pwrmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.pwrmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : pwrmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	22175680	12676	0	0
intr_enable_rd_A	22175680	39898	0	0
reset_en_rd_A	22175680	1520	0	0
reset_en_regwen_rd_A	22175680	1302	0	0
wake_info_capture_dis_rd_A	22175680	1260	0	0
wakeup_en_rd_A	22175680	2785	0	0
wakeup_en_regwen_rd_A	22175680	1210	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22175680	12676	0	0
T8	299326	1	0	0
T9	3421	0	0	0
T10	5170	0	0	0
T13	10484	0	0	0
T21	0	44	0	0
T22	0	34	0	0
T33	0	12	0	0
T35	5223	0	0	0
T36	1422	0	0	0
T37	10360	0	0	0
T43	0	25	0	0
T47	0	39	0	0
T56	1818	0	0	0
T62	17375	0	0	0
T75	1285	0	0	0
T123	0	42	0	0
T124	0	10	0	0
T125	0	4	0	0
T126	0	10	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22175680	39898	0	0
T4	1632	3	0	0
T5	1925	0	0	0
T6	2215	25	0	0
T7	19395	0	0	0
T8	299326	2097	0	0
T9	3421	0	0	0
T10	5170	24	0	0
T13	10484	71	0	0
T14	0	349	0	0
T35	5223	0	0	0
T56	0	1	0	0
T62	17375	31	0	0
T74	0	62	0	0
T81	0	81	0	0

reset_en_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22175680	1520	0	0
T15	793	0	0	0
T33	0	16	0	0
T39	3253	0	0	0
T43	836055	5	0	0
T60	0	34	0	0
T63	0	6	0	0
T67	0	5	0	0
T77	0	3	0	0
T83	1984	0	0	0
T85	1991	0	0	0
T86	2174	0	0	0
T87	1836	0	0	0
T127	0	17	0	0
T128	0	10	0	0
T129	0	2	0	0
T130	0	39	0	0
T131	52325	0	0	0
T132	54715	0	0	0
T133	2683	0	0	0

reset_en_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22175680	1302	0	0
T15	793	0	0	0
T33	0	13	0	0
T39	3253	0	0	0
T43	836055	7	0	0
T60	0	31	0	0
T67	0	6	0	0
T77	0	2	0	0
T83	1984	0	0	0
T85	1991	0	0	0
T86	2174	0	0	0
T87	1836	0	0	0
T127	0	8	0	0
T128	0	12	0	0
T131	52325	0	0	0
T132	54715	0	0	0
T133	2683	0	0	0
T134	0	1	0	0
T135	0	2	0	0
T136	0	5	0	0

wake_info_capture_dis_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22175680	1260	0	0
T15	793	0	0	0
T33	0	3	0	0
T39	3253	0	0	0
T43	836055	6	0	0
T60	0	19	0	0
T77	0	2	0	0
T83	1984	0	0	0
T85	1991	0	0	0
T86	2174	0	0	0
T87	1836	0	0	0
T127	0	17	0	0
T128	0	5	0	0
T130	0	13	0	0
T131	52325	0	0	0
T132	54715	0	0	0
T133	2683	0	0	0
T135	0	7	0	0
T136	0	9	0	0
T137	0	2	0	0

wakeup_en_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22175680	2785	0	0
T15	793	0	0	0
T33	0	13	0	0
T39	3253	0	0	0
T43	836055	8	0	0
T60	0	37	0	0
T63	0	9	0	0
T67	0	22	0	0
T77	0	4	0	0
T83	1984	0	0	0
T85	1991	0	0	0
T86	2174	0	0	0
T87	1836	0	0	0
T126	0	5	0	0
T127	0	24	0	0
T128	0	6	0	0
T131	52325	0	0	0
T132	54715	0	0	0
T133	2683	0	0	0
T135	0	3	0	0

wakeup_en_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22175680	1210	0	0
T15	793	0	0	0
T33	0	4	0	0
T39	3253	0	0	0
T43	836055	7	0	0
T60	0	17	0	0
T63	0	2	0	0
T67	0	7	0	0
T77	0	1	0	0
T83	1984	0	0	0
T85	1991	0	0	0
T86	2174	0	0	0
T87	1836	0	0	0
T127	0	23	0	0
T128	0	8	0	0
T130	0	20	0	0
T131	52325	0	0	0
T132	54715	0	0	0
T133	2683	0	0	0
T135	0	11	0	0