Unified Coverage Report :: Module :: clkmgr_pwrmgr_sva_if

Module : clkmgr_pwrmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_pwrmgr_sva_if_0.1/clkmgr_pwrmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_pwrmgr_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_pwrmgr_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : clkmgr_pwrmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
IoStatusFall_A	21646800	45823	0	0
IoStatusRise_A	21646800	50957	0	0
MainStatusFall_A	21646800	45823	0	0
MainStatusRise_A	21646800	50959	0	0
UsbStatusFall_A	21646800	30963	0	0
UsbStatusRise_A	21646800	34911	0	0

IoStatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21646800	45823	0	0
T1	5430	7	0	0
T2	1376	1	0	0
T3	1921	12	0	0
T4	1632	2	0	0
T5	1925	4	0	0
T6	2215	6	0	0
T7	19395	99	0	0
T8	299326	1110	0	0
T9	3421	4	0	0
T10	5170	12	0	0

IoStatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21646800	50957	0	0
T1	5430	8	0	0
T2	1376	3	0	0
T3	1921	14	0	0
T4	1632	3	0	0
T5	1925	5	0	0
T6	2215	7	0	0
T7	19395	112	0	0
T8	299326	1248	0	0
T9	3421	5	0	0
T10	5170	14	0	0

MainStatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21646800	45823	0	0
T1	5430	7	0	0
T2	1376	1	0	0
T3	1921	12	0	0
T4	1632	2	0	0
T5	1925	4	0	0
T6	2215	6	0	0
T7	19395	99	0	0
T8	299326	1110	0	0
T9	3421	4	0	0
T10	5170	12	0	0

MainStatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21646800	50959	0	0
T1	5430	8	0	0
T2	1376	3	0	0
T3	1921	14	0	0
T4	1632	3	0	0
T5	1925	5	0	0
T6	2215	7	0	0
T7	19395	112	0	0
T8	299326	1248	0	0
T9	3421	5	0	0
T10	5170	14	0	0

UsbStatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21646800	30963	0	0
T1	5430	7	0	0
T2	1376	1	0	0
T3	1921	12	0	0
T4	1632	2	0	0
T5	1925	4	0	0
T6	2215	6	0	0
T7	19395	71	0	0
T8	299326	815	0	0
T9	3421	4	0	0
T10	5170	12	0	0

UsbStatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21646800	34911	0	0
T1	5430	8	0	0
T2	1376	3	0	0
T3	1921	14	0	0
T4	1632	3	0	0
T5	1925	5	0	0
T6	2215	7	0	0
T7	19395	78	0	0
T8	299326	908	0	0
T9	3421	5	0	0
T10	5170	14	0	0