Unified Coverage Report :: Module :: pwrmgr_sec_cm_checker_assert

Module : pwrmgr_sec_cm_checker_assert

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_sec_cm_checker_assert	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.pwrmgr_sec_cm_checker_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : pwrmgr_sec_cm_checker_assert

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	39	1	1	100.00
ALWAYS	40	1	1	100.00
ALWAYS	41	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv' or '../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
39	1	1
40	1	1
41	1	1

---

Cond Coverage for Module : pwrmgr_sec_cm_checker_assert

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       39
 EXPRESSION (((!rst_ni)) || disable_sva)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       40
 EXPRESSION (((!rst_esc_ni)) || disable_sva)
             -------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       41
 EXPRESSION (((!rst_slow_ni)) || disable_sva)
             --------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

---

Assert Coverage for Module : pwrmgr_sec_cm_checker_assert

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	10	10	100.00	10	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	10	10	100.00	10	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
RomAllowActiveState_A	21646800	50576	0	0
RomAllowCheckGoodState_A	21646800	50626	0	0
RomBlockActiveState_A	21646800	27724	0	0
RomBlockCheckGoodState_A	21646800	388789	0	0
RomIntgChkDisFalse_A	21646800	21090255	0	0
RomIntgChkDisTrue_A	21646800	102894	0	0
RstreqChkEsctimeout_A	21646800	3262	0	0
RstreqChkFsmterm_A	21646800	140	0	0
RstreqChkGlbesc_A	21646800	3266	0	0
RstreqChkMainpd_A	21646800	881778	0	0

RomAllowActiveState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21646800	50576	0	0
T1	5430	8	0	0
T2	1376	3	0	0
T3	1921	14	0	0
T4	1632	3	0	0
T5	1925	5	0	0
T6	2215	7	0	0
T7	19395	112	0	0
T8	299326	1248	0	0
T9	3421	5	0	0
T10	5170	14	0	0

RomAllowCheckGoodState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21646800	50626	0	0
T1	5430	8	0	0
T2	1376	3	0	0
T3	1921	14	0	0
T4	1632	3	0	0
T5	1925	5	0	0
T6	2215	7	0	0
T7	19395	112	0	0
T8	299326	1248	0	0
T9	3421	5	0	0
T10	5170	14	0	0

RomBlockActiveState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21646800	27724	0	0
T1	5430	1538	0	0
T2	1376	0	0	0
T3	1921	0	0	0
T4	1632	0	0	0
T5	1925	0	0	0
T6	2215	159	0	0
T7	19395	0	0	0
T8	299326	0	0	0
T9	3421	0	0	0
T10	5170	0	0	0
T23	0	3	0	0
T138	0	283	0	0
T139	0	670	0	0
T140	0	376	0	0
T141	0	231	0	0
T142	0	168	0	0
T143	0	2	0	0
T144	0	784	0	0

RomBlockCheckGoodState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21646800	388789	0	0
T1	5430	1040	0	0
T2	1376	0	0	0
T3	1921	0	0	0
T4	1632	0	0	0
T5	1925	0	0	0
T6	2215	82	0	0
T7	19395	503	0	0
T8	299326	3208	0	0
T9	3421	0	0	0
T10	5170	0	0	0
T14	0	687	0	0
T21	0	3670	0	0
T37	0	275	0	0
T38	0	389	0	0
T72	0	276	0	0
T73	0	342	0	0

RomIntgChkDisFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21646800	21090255	0	0
T1	5430	5189	0	0
T2	1376	1202	0	0
T3	1921	1765	0	0
T4	1632	1556	0	0
T5	1925	1604	0	0
T6	2215	1938	0	0
T7	19395	18496	0	0
T8	299326	289132	0	0
T9	3421	3042	0	0
T10	5170	5014	0	0

RomIntgChkDisTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21646800	102894	0	0
T1	5430	190	0	0
T2	1376	0	0	0
T3	1921	0	0	0
T4	1632	0	0	0
T5	1925	0	0	0
T6	2215	195	0	0
T7	19395	0	0	0
T8	299326	0	0	0
T9	3421	0	0	0
T10	5170	0	0	0
T23	0	260	0	0
T131	0	5029	0	0
T138	0	605	0	0
T139	0	560	0	0
T140	0	1115	0	0
T141	0	105	0	0
T145	0	1146	0	0
T146	0	56	0	0

RstreqChkEsctimeout_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21646800	3262	0	0
T1	5430	3	0	0
T2	1376	1	0	0
T3	1921	7	0	0
T4	1632	0	0	0
T5	1925	0	0	0
T6	2215	2	0	0
T7	19395	10	0	0
T8	299326	88	0	0
T9	3421	0	0	0
T10	5170	1	0	0
T14	0	21	0	0
T35	0	3	0	0
T36	0	4	0	0

RstreqChkFsmterm_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21646800	140	0	0
T18	14634	40	0	0
T19	0	20	0	0
T20	0	40	0	0
T24	0	20	0	0
T25	0	20	0	0
T26	6436	0	0	0
T27	8724	0	0	0
T28	2517	0	0	0
T29	1150	0	0	0
T30	21972	0	0	0
T31	1922	0	0	0
T32	9561	0	0	0
T33	319130	0	0	0
T34	7436	0	0	0

RstreqChkGlbesc_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21646800	3266	0	0
T1	5430	3	0	0
T2	1376	1	0	0
T3	1921	7	0	0
T4	1632	0	0	0
T5	1925	0	0	0
T6	2215	2	0	0
T7	19395	10	0	0
T8	299326	88	0	0
T9	3421	0	0	0
T10	5170	1	0	0
T14	0	21	0	0
T35	0	3	0	0
T36	0	4	0	0

RstreqChkMainpd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21646800	881778	0	0
T1	5430	1400	0	0
T2	1376	0	0	0
T3	1921	150	0	0
T4	1632	0	0	0
T5	1925	0	0	0
T6	2215	268	0	0
T7	19395	1070	0	0
T8	299326	4313	0	0
T9	3421	0	0	0
T10	5170	574	0	0
T35	0	184	0	0
T36	0	44	0	0
T37	0	761	0	0
T75	0	15	0	0