Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	466470	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

184859

1

T2

47

T3

27

T4

35

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	342373	1			T1	1		T2	86		T3	37
values[0x0]	154050	1			T2	16		T3	26		T4	9
values[0x1]	154906	1			T2	17		T3	22		T4	1

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	369259	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

282070

1

T2

60

T3

38

T4

38

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	2055	1			T6	2		T11	2		T13	32
valid_sources[0x01]	1591	1			T2	1		T11	4		T13	12
valid_sources[0x02]	2797	1			T3	1		T11	1		T13	35
valid_sources[0x03]	2107	1			T11	2		T13	31		T84	20
valid_sources[0x04]	1878	1			T3	1		T11	9		T13	44
valid_sources[0x05]	2479	1			T2	1		T18	1		T11	2
valid_sources[0x06]	4032	1			T2	1		T11	2		T13	41
valid_sources[0x07]	1902	1			T2	1		T6	1		T11	3
valid_sources[0x08]	2589	1			T11	1		T13	43		T37	2
valid_sources[0x09]	2035	1			T11	1		T13	29		T14	5
valid_sources[0x0a]	2179	1			T3	1		T11	5		T12	1
valid_sources[0x0b]	2543	1			T11	1		T12	1		T13	29
valid_sources[0x0c]	3306	1			T11	3		T13	45		T37	1
valid_sources[0x0d]	1858	1			T18	1		T11	3		T13	17
valid_sources[0x0e]	1805	1			T2	2		T18	1		T11	3
valid_sources[0x0f]	1971	1			T11	3		T13	20		T14	5
valid_sources[0x10]	1756	1			T3	1		T11	3		T13	46
valid_sources[0x11]	1975	1			T2	2		T11	5		T13	36
valid_sources[0x12]	2223	1			T2	1		T6	1		T11	2
valid_sources[0x13]	3130	1			T2	1		T11	8		T13	35
valid_sources[0x14]	3894	1			T11	1		T13	40		T14	6
valid_sources[0x15]	3345	1			T2	1		T11	5		T13	33
valid_sources[0x16]	1838	1			T11	2		T13	49		T37	3
valid_sources[0x17]	3189	1			T11	1		T13	30		T84	1
valid_sources[0x18]	3007	1			T11	3		T13	34		T37	1
valid_sources[0x19]	3369	1			T11	3		T13	30		T37	1
valid_sources[0x1a]	2031	1			T11	3		T13	42		T14	2
valid_sources[0x1b]	2054	1			T2	3		T11	3		T13	24
valid_sources[0x1c]	3292	1			T2	1		T11	2		T13	18
valid_sources[0x1d]	4626	1			T11	3		T13	30		T37	1
valid_sources[0x1e]	1942	1			T3	1		T6	2		T11	3
valid_sources[0x1f]	3481	1			T2	2		T11	8		T13	28
valid_sources[0x20]	2630	1			T41	1		T11	3		T13	45
valid_sources[0x21]	2635	1			T3	1		T11	5		T13	33
valid_sources[0x22]	1854	1			T2	1		T3	1		T11	4
valid_sources[0x23]	2009	1			T11	3		T13	43		T37	6
valid_sources[0x24]	1913	1			T18	1		T11	3		T13	40
valid_sources[0x25]	2038	1			T11	1		T12	6		T13	18
valid_sources[0x26]	1935	1			T10	1		T18	1		T11	2
valid_sources[0x27]	1975	1			T11	2		T13	29		T84	3
valid_sources[0x28]	1811	1			T2	1		T3	4		T11	4
valid_sources[0x29]	3931	1			T3	1		T18	4		T22	1
valid_sources[0x2a]	2593	1			T2	1		T11	2		T13	21
valid_sources[0x2b]	1967	1			T2	1		T11	3		T13	30
valid_sources[0x2c]	1804	1			T2	1		T3	1		T11	4
valid_sources[0x2d]	1741	1			T11	4		T13	26		T37	3
valid_sources[0x2e]	1941	1			T2	2		T6	1		T11	3
valid_sources[0x2f]	2877	1			T11	1		T13	47		T14	9
valid_sources[0x30]	1958	1			T2	1		T11	6		T13	28
valid_sources[0x31]	2221	1			T11	4		T13	45		T14	20
valid_sources[0x32]	1848	1			T2	2		T11	4		T13	11
valid_sources[0x33]	2652	1			T11	7		T13	23		T14	2
valid_sources[0x34]	2540	1			T11	6		T13	27		T37	1
valid_sources[0x35]	1896	1			T3	2		T11	2		T13	34
valid_sources[0x36]	1809	1			T11	4		T13	31		T84	9
valid_sources[0x37]	1885	1			T11	9		T13	25		T14	1
valid_sources[0x38]	4509	1			T2	1		T3	1		T11	5
valid_sources[0x39]	1856	1			T2	1		T3	1		T11	2
valid_sources[0x3a]	1912	1			T2	1		T11	3		T13	32
valid_sources[0x3b]	1966	1			T11	1		T12	3		T13	24
valid_sources[0x3c]	1914	1			T18	1		T11	1		T13	12
valid_sources[0x3d]	2328	1			T11	6		T13	21		T14	21
valid_sources[0x3e]	3407	1			T11	3		T13	34		T14	7
valid_sources[0x3f]	2153	1			T3	1		T18	1		T11	3
valid_sources[0x40]	2555	1			T11	1		T13	49		T84	8
valid_sources[0x41]	2150	1			T3	1		T18	1		T11	1
valid_sources[0x42]	1891	1			T2	1		T11	3		T13	23
valid_sources[0x43]	2486	1			T2	1		T3	1		T11	2
valid_sources[0x44]	2206	1			T11	2		T13	22		T14	8
valid_sources[0x45]	1768	1			T11	3		T13	21		T37	1
valid_sources[0x46]	2685	1			T18	1		T11	2		T13	33
valid_sources[0x47]	2293	1			T2	2		T11	2		T13	21
valid_sources[0x48]	2059	1			T11	1		T13	37		T14	7
valid_sources[0x49]	1850	1			T3	1		T11	5		T13	18
valid_sources[0x4a]	2758	1			T3	2		T11	6		T13	40
valid_sources[0x4b]	4913	1			T3	1		T18	1		T13	34
valid_sources[0x4c]	1850	1			T2	1		T11	3		T13	36
valid_sources[0x4d]	1907	1			T6	2		T11	3		T13	38
valid_sources[0x4e]	2945	1			T11	5		T13	35		T37	2
valid_sources[0x4f]	2808	1			T3	2		T11	6		T13	29
valid_sources[0x50]	2757	1			T11	4		T13	37		T14	6
valid_sources[0x51]	2487	1			T3	1		T11	3		T13	32
valid_sources[0x52]	1992	1			T18	1		T11	2		T13	48
valid_sources[0x53]	3288	1			T11	2		T13	26		T37	1
valid_sources[0x54]	1808	1			T18	1		T13	38		T37	2
valid_sources[0x55]	1807	1			T3	1		T11	3		T13	35
valid_sources[0x56]	2087	1			T2	1		T11	1		T13	48
valid_sources[0x57]	1707	1			T3	1		T11	4		T13	23
valid_sources[0x58]	2073	1			T11	5		T13	35		T37	6
valid_sources[0x59]	1768	1			T2	1		T11	1		T13	20
valid_sources[0x5a]	2749	1			T2	4		T3	1		T11	2
valid_sources[0x5b]	2033	1			T11	2		T13	21		T14	10
valid_sources[0x5c]	2598	1			T1	1		T2	1		T3	1
valid_sources[0x5d]	9354	1			T2	3		T6	2		T13	26
valid_sources[0x5e]	3126	1			T2	1		T3	1		T7	1
valid_sources[0x5f]	2387	1			T2	2		T11	6		T13	31
valid_sources[0x60]	2457	1			T3	1		T11	1		T13	32
valid_sources[0x61]	2167	1			T18	1		T11	6		T13	35
valid_sources[0x62]	5479	1			T3	3		T11	2		T13	39
valid_sources[0x63]	1921	1			T3	1		T11	2		T13	22
valid_sources[0x64]	2067	1			T2	2		T11	3		T13	33
valid_sources[0x65]	1814	1			T11	4		T13	21		T84	4
valid_sources[0x66]	2076	1			T3	1		T11	3		T13	29
valid_sources[0x67]	1759	1			T2	1		T11	2		T13	19
valid_sources[0x68]	3257	1			T18	1		T11	5		T13	21
valid_sources[0x69]	3677	1			T3	1		T11	3		T13	27
valid_sources[0x6a]	3778	1			T2	1		T18	1		T11	3
valid_sources[0x6b]	1694	1			T11	2		T13	27		T37	3
valid_sources[0x6c]	2272	1			T11	6		T13	29		T37	1
valid_sources[0x6d]	1902	1			T11	4		T13	38		T14	1
valid_sources[0x6e]	1721	1			T2	2		T3	2		T11	2
valid_sources[0x6f]	2706	1			T5	76		T11	4		T12	1
valid_sources[0x70]	2486	1			T11	9		T13	32		T14	7
valid_sources[0x71]	2201	1			T11	10		T13	29		T14	7
valid_sources[0x72]	1964	1			T6	1		T11	3		T13	21
valid_sources[0x73]	2421	1			T11	2		T12	5		T13	31
valid_sources[0x74]	1884	1			T3	1		T18	1		T11	7
valid_sources[0x75]	3018	1			T18	1		T11	2		T13	29
valid_sources[0x76]	3425	1			T2	2		T3	1		T6	2
valid_sources[0x77]	3933	1			T3	1		T11	2		T13	27
valid_sources[0x78]	2014	1			T11	2		T13	18		T37	2
valid_sources[0x79]	1943	1			T11	5		T13	32		T14	4
valid_sources[0x7a]	2171	1			T18	3		T11	5		T13	25
valid_sources[0x7b]	3299	1			T11	7		T13	27		T44	1
valid_sources[0x7c]	2812	1			T11	5		T13	33		T84	4
valid_sources[0x7d]	2138	1			T2	1		T11	6		T13	38
valid_sources[0x7e]	2146	1			T6	1		T11	4		T13	34
valid_sources[0x7f]	3324	1			T11	2		T13	30		T37	2
valid_sources[0x80]	1999	1			T11	3		T13	40		T14	5

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

93850

1

T2

45

T3

13

T4

32

values[0x0]

all_enables

biggest_size

58141

1

T3

11

T4

3

T5

5

values[0x1]

all_enables

biggest_size

32868

1

T2

2

T3

3

T5

2