SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING |
100.00 | 100.00 | 1 | 100 | 1 | 1 | 64 | 64 |
NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_rom_ctrl_done_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_rom_ctrl_good_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_sw_rst_req_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 34831 | 1 | T11 | 298 | T13 | 1 | T25 | 302 | ||||
others[1] | 35029 | 1 | T5 | 1 | T11 | 308 | T25 | 308 | ||||
others[2] | 35305 | 1 | T11 | 312 | T25 | 297 | T47 | 272 | ||||
others[3] | 58285 | 1 | T11 | 492 | T25 | 486 | T47 | 509 | ||||
false | 16948 | 1 | T5 | 3 | T11 | 50 | T13 | 180 | ||||
true | 26411 | 1 | T1 | 4 | T2 | 12 | T3 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 35113 | 1 | T11 | 304 | T25 | 316 | T47 | 311 | ||||
others[1] | 34980 | 1 | T11 | 281 | T13 | 2 | T25 | 322 | ||||
others[2] | 34906 | 1 | T11 | 319 | T25 | 285 | T47 | 314 | ||||
others[3] | 58211 | 1 | T11 | 506 | T25 | 484 | T47 | 489 | ||||
false | 11074 | 1 | T5 | 5 | T11 | 50 | T13 | 92 | ||||
true | 20593 | 1 | T1 | 4 | T2 | 12 | T3 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 691 | 1 | T18 | 1 | T13 | 8 | T84 | 7 | ||||
others[1] | 653 | 1 | T13 | 3 | T84 | 3 | T112 | 5 | ||||
others[2] | 633 | 1 | T2 | 1 | T13 | 4 | T84 | 10 | ||||
others[3] | 1017 | 1 | T2 | 3 | T18 | 1 | T13 | 7 | ||||
false | 12403 | 1 | T1 | 4 | T2 | 20 | T3 | 1 | ||||
true | 3576 | 1 | T2 | 4 | T5 | 2 | T18 | 7 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |