Unified Coverage Report :: Module :: pwrmgr_csr_assert_fpv

Module : pwrmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_pwrmgr_csr_assert_0/pwrmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.pwrmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : pwrmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	23743497	15792	0	0
intr_enable_rd_A	23743497	42901	0	0
reset_en_rd_A	23743497	1622	0	0
reset_en_regwen_rd_A	23743497	1440	0	0
wake_info_capture_dis_rd_A	23743497	1494	0	0
wakeup_en_rd_A	23743497	2099	0	0
wakeup_en_regwen_rd_A	23743497	1538	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23743497	15792	0	0
T13	269448	73	0	0
T14	52459	0	0	0
T15	2492	0	0	0
T23	0	35	0	0
T24	0	10	0	0
T37	5170	0	0	0
T38	28744	0	0	0
T42	15873	0	0	0
T44	1295	0	0	0
T52	0	131	0	0
T84	3158	0	0	0
T86	6615	0	0	0
T105	0	50	0	0
T112	1857	0	0	0
T146	0	73	0	0
T147	0	6	0	0
T148	0	4	0	0
T149	0	9	0	0
T150	0	6	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23743497	42901	0	0
T11	55645	182	0	0
T12	2374	2	0	0
T13	269448	0	0	0
T14	52459	0	0	0
T15	2492	0	0	0
T37	5170	59	0	0
T38	28744	0	0	0
T40	0	18	0	0
T43	0	19	0	0
T44	1295	0	0	0
T65	0	2	0	0
T84	3158	0	0	0
T86	6615	0	0	0
T89	0	85	0	0
T97	0	35	0	0
T99	0	9	0	0
T151	0	99	0	0

reset_en_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23743497	1622	0	0
T24	166657	8	0	0
T45	2861	0	0	0
T62	0	57	0	0
T68	0	8	0	0
T100	0	12	0	0
T146	518341	0	0	0
T149	0	5	0	0
T150	0	9	0	0
T152	0	6	0	0
T153	0	1	0	0
T154	0	6	0	0
T155	0	1	0	0
T156	14726	0	0	0
T157	2219	0	0	0
T158	15809	0	0	0
T159	20848	0	0	0
T160	2171	0	0	0
T161	2317	0	0	0
T162	866	0	0	0

reset_en_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23743497	1440	0	0
T24	166657	13	0	0
T45	2861	0	0	0
T62	0	25	0	0
T68	0	9	0	0
T92	0	6	0	0
T100	0	10	0	0
T146	518341	0	0	0
T150	0	19	0	0
T152	0	1	0	0
T153	0	4	0	0
T154	0	7	0	0
T155	0	6	0	0
T156	14726	0	0	0
T157	2219	0	0	0
T158	15809	0	0	0
T159	20848	0	0	0
T160	2171	0	0	0
T161	2317	0	0	0
T162	866	0	0	0

wake_info_capture_dis_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23743497	1494	0	0
T24	166657	7	0	0
T45	2861	0	0	0
T62	0	98	0	0
T68	0	9	0	0
T92	0	4	0	0
T100	0	10	0	0
T146	518341	0	0	0
T150	0	11	0	0
T152	0	1	0	0
T153	0	3	0	0
T154	0	7	0	0
T155	0	12	0	0
T156	14726	0	0	0
T157	2219	0	0	0
T158	15809	0	0	0
T159	20848	0	0	0
T160	2171	0	0	0
T161	2317	0	0	0
T162	866	0	0	0

wakeup_en_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23743497	2099	0	0
T24	166657	3	0	0
T45	2861	0	0	0
T62	0	37	0	0
T68	0	2	0	0
T92	0	5	0	0
T100	0	11	0	0
T146	518341	0	0	0
T150	0	15	0	0
T152	0	4	0	0
T153	0	8	0	0
T154	0	9	0	0
T155	0	5	0	0
T156	14726	0	0	0
T157	2219	0	0	0
T158	15809	0	0	0
T159	20848	0	0	0
T160	2171	0	0	0
T161	2317	0	0	0
T162	866	0	0	0

wakeup_en_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23743497	1538	0	0
T24	166657	6	0	0
T45	2861	0	0	0
T62	0	71	0	0
T68	0	3	0	0
T92	0	8	0	0
T100	0	6	0	0
T146	518341	0	0	0
T150	0	12	0	0
T152	0	5	0	0
T153	0	5	0	0
T154	0	2	0	0
T155	0	7	0	0
T156	14726	0	0	0
T157	2219	0	0	0
T158	15809	0	0	0
T159	20848	0	0	0
T160	2171	0	0	0
T161	2317	0	0	0
T162	866	0	0	0