Unified Coverage Report :: Module :: pwrmgr_sec_cm_checker_assert

Module : pwrmgr_sec_cm_checker_assert

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_sec_cm_checker_assert	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.pwrmgr_sec_cm_checker_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : pwrmgr_sec_cm_checker_assert

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	39	1	1	100.00
ALWAYS	40	1	1	100.00
ALWAYS	41	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv' or '../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
39	1	1
40	1	1
41	1	1

---

Cond Coverage for Module : pwrmgr_sec_cm_checker_assert

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       39
 EXPRESSION (((!rst_ni)) || disable_sva)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       40
 EXPRESSION (((!rst_esc_ni)) || disable_sva)
             -------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       41
 EXPRESSION (((!rst_slow_ni)) || disable_sva)
             --------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

---

Assert Coverage for Module : pwrmgr_sec_cm_checker_assert

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	10	10	100.00	10	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	10	10	100.00	10	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
RomAllowActiveState_A	23153058	53732	0	0
RomAllowCheckGoodState_A	23153058	53782	0	0
RomBlockActiveState_A	23153058	26157	0	0
RomBlockCheckGoodState_A	23153058	404889	0	0
RomIntgChkDisFalse_A	23153058	22553462	0	0
RomIntgChkDisTrue_A	23153058	116946	0	0
RstreqChkEsctimeout_A	23153058	3942	0	0
RstreqChkFsmterm_A	23153058	140	0	0
RstreqChkGlbesc_A	23153058	3944	0	0
RstreqChkMainpd_A	23153058	923826	0	0

RomAllowActiveState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23153058	53732	0	0
T1	1338	4	0	0
T2	3111	12	0	0
T3	1561	7	0	0
T4	2217	3	0	0
T5	5383	9	0	0
T6	3054	5	0	0
T7	845	3	0	0
T8	15467	4	0	0
T9	1288	5	0	0
T10	15818	2	0	0

RomAllowCheckGoodState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23153058	53782	0	0
T1	1338	4	0	0
T2	3111	13	0	0
T3	1561	7	0	0
T4	2217	3	0	0
T5	5383	9	0	0
T6	3054	5	0	0
T7	845	3	0	0
T8	15467	4	0	0
T9	1288	5	0	0
T10	15818	2	0	0

RomBlockActiveState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23153058	26157	0	0
T5	5383	1487	0	0
T6	3054	0	0	0
T7	845	0	0	0
T8	15467	0	0	0
T9	1288	0	0	0
T10	15818	0	0	0
T11	55645	0	0	0
T18	2820	0	0	0
T22	1485	0	0	0
T41	15189	0	0	0
T47	0	9	0	0
T48	0	584	0	0
T95	0	611	0	0
T98	0	24	0	0
T157	0	167	0	0
T162	0	78	0	0
T163	0	128	0	0
T164	0	12	0	0
T165	0	6	0	0

RomBlockCheckGoodState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23153058	404889	0	0
T5	5383	1062	0	0
T6	3054	0	0	0
T7	845	0	0	0
T8	15467	0	0	0
T9	1288	0	0	0
T10	15818	0	0	0
T11	55645	4161	0	0
T13	0	2313	0	0
T14	0	298	0	0
T18	2820	0	0	0
T22	1485	0	0	0
T23	0	4152	0	0
T25	0	1308	0	0
T37	0	276	0	0
T38	0	390	0	0
T41	15189	0	0	0
T64	0	69	0	0
T166	0	161	0	0

RomIntgChkDisFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23153058	22553462	0	0
T1	1338	1032	0	0
T2	3111	2095	0	0
T3	1561	1483	0	0
T4	2217	2141	0	0
T5	5383	5128	0	0
T6	3054	2708	0	0
T7	845	707	0	0
T8	15467	15393	0	0
T9	1288	920	0	0
T10	15818	15723	0	0

RomIntgChkDisTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23153058	116946	0	0
T5	5383	188	0	0
T6	3054	0	0	0
T7	845	0	0	0
T8	15467	0	0	0
T9	1288	0	0	0
T10	15818	0	0	0
T11	55645	1989	0	0
T18	2820	0	0	0
T22	1485	0	0	0
T25	0	141	0	0
T41	15189	0	0	0
T47	0	144	0	0
T48	0	1196	0	0
T95	0	1270	0	0
T98	0	234	0	0
T163	0	27	0	0
T167	0	3126	0	0
T168	0	201	0	0

RstreqChkEsctimeout_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23153058	3942	0	0
T1	1338	3	0	0
T2	3111	7	0	0
T3	1561	0	0	0
T4	2217	0	0	0
T5	5383	3	0	0
T6	3054	0	0	0
T7	845	1	0	0
T8	15467	1	0	0
T9	1288	4	0	0
T10	15818	1	0	0
T18	0	4	0	0
T22	0	4	0	0
T41	0	1	0	0

RstreqChkFsmterm_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23153058	140	0	0
T19	15915	40	0	0
T20	0	20	0	0
T21	0	20	0	0
T26	0	40	0	0
T27	0	20	0	0
T28	15978	0	0	0
T29	5443	0	0	0
T30	1638	0	0	0
T31	3614	0	0	0
T32	3212	0	0	0
T33	4279	0	0	0
T34	4337	0	0	0
T35	15918	0	0	0
T36	5629	0	0	0

RstreqChkGlbesc_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23153058	3944	0	0
T1	1338	3	0	0
T2	3111	7	0	0
T3	1561	0	0	0
T4	2217	0	0	0
T5	5383	3	0	0
T6	3054	0	0	0
T7	845	1	0	0
T8	15467	1	0	0
T9	1288	4	0	0
T10	15818	1	0	0
T18	0	4	0	0
T22	0	4	0	0
T41	0	1	0	0

RstreqChkMainpd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23153058	923826	0	0
T2	3111	114	0	0
T3	1561	0	0	0
T4	2217	0	0	0
T5	5383	1920	0	0
T6	3054	0	0	0
T7	845	0	0	0
T8	15467	0	0	0
T9	1288	0	0	0
T10	15818	0	0	0
T11	0	5403	0	0
T13	0	13189	0	0
T14	0	1103	0	0
T15	0	17	0	0
T16	0	23	0	0
T18	0	66	0	0
T37	0	92	0	0
T38	0	531	0	0
T41	15189	0	0	0