Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	483246	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

186730

1

T1

144

T2

19

T3

8

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	350317	1			T1	251		T2	29		T3	16
values[0x0]	159713	1			T1	17		T2	10		T3	6
values[0x1]	159946	1			T1	16		T2	6		T3	2

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	382498	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

287478

1

T1

163

T2

27

T3

11

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	3402	1			T4	2		T25	1		T27	1
valid_sources[0x01]	2207	1			T4	1		T13	14		T25	2
valid_sources[0x02]	2282	1			T25	2		T43	5		T47	1
valid_sources[0x03]	3633	1			T1	4		T4	1		T13	18
valid_sources[0x04]	2390	1			T4	1		T25	2		T26	1
valid_sources[0x05]	2047	1			T3	3		T4	2		T5	1
valid_sources[0x06]	2379	1			T4	1		T25	3		T27	2
valid_sources[0x07]	1775	1			T1	3		T10	2		T25	2
valid_sources[0x08]	2268	1			T4	3		T25	3		T40	1
valid_sources[0x09]	2090	1			T4	1		T25	5		T27	1
valid_sources[0x0a]	2303	1			T4	3		T25	2		T43	2
valid_sources[0x0b]	2307	1			T4	2		T25	4		T26	1
valid_sources[0x0c]	3009	1			T1	1		T4	1		T25	1
valid_sources[0x0d]	2900	1			T5	1		T25	1		T56	2
valid_sources[0x0e]	2249	1			T13	17		T25	1		T27	1
valid_sources[0x0f]	1907	1			T3	4		T4	2		T13	9
valid_sources[0x10]	3000	1			T2	4		T4	2		T25	5
valid_sources[0x11]	2024	1			T1	1		T4	4		T25	6
valid_sources[0x12]	2267	1			T2	8		T4	2		T13	5
valid_sources[0x13]	2484	1			T4	2		T5	1		T13	17
valid_sources[0x14]	2329	1			T4	1		T25	2		T27	1
valid_sources[0x15]	1966	1			T4	2		T13	20		T25	1
valid_sources[0x16]	2112	1			T4	2		T25	8		T26	2
valid_sources[0x17]	2521	1			T1	5		T13	14		T25	3
valid_sources[0x18]	3327	1			T4	3		T25	1		T43	1
valid_sources[0x19]	2851	1			T4	2		T25	5		T56	1
valid_sources[0x1a]	1971	1			T1	1		T4	1		T25	4
valid_sources[0x1b]	2623	1			T4	2		T13	14		T25	4
valid_sources[0x1c]	3651	1			T4	1		T25	2		T26	1
valid_sources[0x1d]	2887	1			T2	2		T4	1		T26	1
valid_sources[0x1e]	2574	1			T4	1		T25	1		T56	1
valid_sources[0x1f]	1973	1			T4	4		T5	1		T25	2
valid_sources[0x20]	2259	1			T4	1		T25	1		T26	6
valid_sources[0x21]	3417	1			T4	1		T13	6		T25	7
valid_sources[0x22]	1907	1			T1	5		T4	3		T25	1
valid_sources[0x23]	2753	1			T1	3		T3	2		T25	1
valid_sources[0x24]	2377	1			T4	3		T10	4		T13	9
valid_sources[0x25]	2676	1			T4	3		T13	1		T25	3
valid_sources[0x26]	3142	1			T4	2		T25	1		T26	2
valid_sources[0x27]	2091	1			T1	1		T4	3		T5	1
valid_sources[0x28]	2167	1			T4	4		T25	1		T26	1
valid_sources[0x29]	2399	1			T13	20		T25	2		T56	1
valid_sources[0x2a]	3413	1			T4	1		T25	5		T26	1
valid_sources[0x2b]	2082	1			T4	3		T13	14		T25	5
valid_sources[0x2c]	2313	1			T1	3		T4	1		T10	3
valid_sources[0x2d]	3061	1			T4	3		T25	2		T26	1
valid_sources[0x2e]	2789	1			T4	1		T13	10		T25	5
valid_sources[0x2f]	2122	1			T4	4		T25	5		T40	1
valid_sources[0x30]	2259	1			T1	2		T4	1		T25	3
valid_sources[0x31]	2144	1			T4	2		T25	1		T27	1
valid_sources[0x32]	2116	1			T4	3		T13	15		T25	1
valid_sources[0x33]	1968	1			T1	6		T4	1		T5	1
valid_sources[0x34]	2104	1			T4	1		T25	5		T27	2
valid_sources[0x35]	1991	1			T4	3		T25	3		T43	4
valid_sources[0x36]	2197	1			T4	2		T13	1		T25	1
valid_sources[0x37]	2867	1			T1	5		T4	2		T26	1
valid_sources[0x38]	2258	1			T25	5		T26	3		T133	2
valid_sources[0x39]	2262	1			T4	1		T25	1		T40	2
valid_sources[0x3a]	2084	1			T1	3		T4	3		T25	4
valid_sources[0x3b]	2065	1			T10	4		T25	6		T56	2
valid_sources[0x3c]	2392	1			T25	3		T15	5		T56	2
valid_sources[0x3d]	3190	1			T4	3		T5	1		T25	2
valid_sources[0x3e]	2090	1			T25	5		T26	2		T27	1
valid_sources[0x3f]	2098	1			T1	1		T4	3		T13	14
valid_sources[0x40]	3602	1			T13	9		T25	4		T133	2
valid_sources[0x41]	2672	1			T5	1		T13	10		T25	3
valid_sources[0x42]	2189	1			T4	1		T9	1		T25	4
valid_sources[0x43]	2430	1			T2	6		T4	2		T25	4
valid_sources[0x44]	3055	1			T1	12		T4	1		T13	4
valid_sources[0x45]	2336	1			T1	2		T4	1		T25	4
valid_sources[0x46]	2015	1			T4	5		T5	2		T13	3
valid_sources[0x47]	4246	1			T4	1		T25	3		T41	1
valid_sources[0x48]	2736	1			T4	2		T40	1		T42	11
valid_sources[0x49]	2099	1			T1	4		T5	3		T13	10
valid_sources[0x4a]	1886	1			T4	3		T10	5		T25	4
valid_sources[0x4b]	1940	1			T4	1		T13	1		T25	5
valid_sources[0x4c]	2260	1			T4	4		T5	1		T13	12
valid_sources[0x4d]	2410	1			T1	7		T25	1		T27	1
valid_sources[0x4e]	2530	1			T4	2		T25	2		T15	5
valid_sources[0x4f]	2410	1			T1	1		T4	3		T25	3
valid_sources[0x50]	1881	1			T1	2		T4	1		T13	1
valid_sources[0x51]	3522	1			T4	5		T56	3		T43	3
valid_sources[0x52]	2566	1			T25	2		T26	1		T56	2
valid_sources[0x53]	2141	1			T4	1		T13	25		T25	6
valid_sources[0x54]	2911	1			T4	2		T25	6		T66	74
valid_sources[0x55]	2780	1			T1	3		T4	2		T13	2
valid_sources[0x56]	3827	1			T25	3		T56	3		T43	3
valid_sources[0x57]	2094	1			T1	1		T5	1		T25	4
valid_sources[0x58]	1947	1			T4	6		T10	4		T25	2
valid_sources[0x59]	1964	1			T1	3		T4	3		T25	3
valid_sources[0x5a]	2502	1			T1	6		T13	2		T25	3
valid_sources[0x5b]	2119	1			T4	1		T25	5		T26	1
valid_sources[0x5c]	2040	1			T4	3		T25	2		T56	1
valid_sources[0x5d]	2414	1			T1	8		T25	3		T27	1
valid_sources[0x5e]	2194	1			T3	4		T25	1		T56	1
valid_sources[0x5f]	4124	1			T1	3		T4	3		T25	5
valid_sources[0x60]	2425	1			T4	6		T25	6		T43	4
valid_sources[0x61]	2581	1			T4	1		T13	6		T25	2
valid_sources[0x62]	2110	1			T4	1		T25	2		T56	1
valid_sources[0x63]	3180	1			T5	2		T25	3		T26	1
valid_sources[0x64]	2486	1			T3	2		T4	3		T25	5
valid_sources[0x65]	1964	1			T1	3		T4	2		T25	6
valid_sources[0x66]	4683	1			T1	10		T25	1		T27	1
valid_sources[0x67]	5485	1			T4	5		T5	1		T25	2
valid_sources[0x68]	2582	1			T1	2		T4	3		T25	2
valid_sources[0x69]	2115	1			T1	4		T4	2		T25	7
valid_sources[0x6a]	1955	1			T4	1		T25	2		T43	3
valid_sources[0x6b]	2849	1			T4	1		T25	1		T27	1
valid_sources[0x6c]	2400	1			T4	2		T11	1		T25	6
valid_sources[0x6d]	2276	1			T4	3		T25	2		T27	2
valid_sources[0x6e]	2233	1			T1	4		T4	1		T25	4
valid_sources[0x6f]	2392	1			T4	2		T13	10		T25	3
valid_sources[0x70]	2163	1			T1	5		T25	6		T40	1
valid_sources[0x71]	3157	1			T1	1		T43	1		T47	1
valid_sources[0x72]	2944	1			T13	15		T25	2		T27	1
valid_sources[0x73]	3045	1			T1	3		T2	3		T4	1
valid_sources[0x74]	2130	1			T4	2		T25	3		T26	4
valid_sources[0x75]	2461	1			T4	2		T13	16		T25	2
valid_sources[0x76]	2401	1			T4	3		T25	6		T26	1
valid_sources[0x77]	5464	1			T4	4		T5	1		T13	21
valid_sources[0x78]	2981	1			T4	2		T56	1		T41	1
valid_sources[0x79]	1972	1			T4	2		T25	2		T43	2
valid_sources[0x7a]	2124	1			T4	4		T25	7		T41	1
valid_sources[0x7b]	2561	1			T25	6		T28	244		T40	2
valid_sources[0x7c]	4011	1			T4	5		T13	17		T25	4
valid_sources[0x7d]	1915	1			T1	2		T25	3		T43	10
valid_sources[0x7e]	2593	1			T4	2		T25	7		T27	1
valid_sources[0x7f]	2155	1			T1	3		T4	1		T25	4
valid_sources[0x80]	2160	1			T13	12		T25	7		T27	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

94408

1

T1

135

T2

13

T3

7

values[0x0]

all_enables

biggest_size

59590

1

T1

4

T2

6

T3

1

values[0x1]

all_enables

biggest_size

32732

1

T1

5

T4

20

T7

1