SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING |
100.00 | 100.00 | 1 | 100 | 1 | 1 | 64 | 64 |
NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_rom_ctrl_done_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_rom_ctrl_good_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_sw_rst_req_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 34991 | 1 | T13 | 286 | T25 | 294 | T43 | 410 | ||||
others[1] | 34951 | 1 | T13 | 301 | T25 | 321 | T27 | 1 | ||||
others[2] | 34859 | 1 | T13 | 324 | T25 | 284 | T43 | 390 | ||||
others[3] | 58769 | 1 | T13 | 500 | T25 | 504 | T43 | 658 | ||||
false | 17866 | 1 | T13 | 50 | T25 | 50 | T26 | 16 | ||||
true | 27551 | 1 | T1 | 12 | T2 | 5 | T3 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 34974 | 1 | T13 | 278 | T25 | 297 | T43 | 372 | ||||
others[1] | 35055 | 1 | T13 | 324 | T25 | 305 | T27 | 1 | ||||
others[2] | 34866 | 1 | T13 | 298 | T25 | 291 | T43 | 409 | ||||
others[3] | 58627 | 1 | T13 | 494 | T25 | 505 | T27 | 1 | ||||
false | 11534 | 1 | T13 | 50 | T25 | 50 | T26 | 8 | ||||
true | 21291 | 1 | T1 | 12 | T2 | 5 | T3 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 586 | 1 | T28 | 3 | T41 | 1 | T42 | 1 | ||||
others[1] | 656 | 1 | T1 | 1 | T14 | 3 | T28 | 8 | ||||
others[2] | 725 | 1 | T1 | 1 | T14 | 1 | T28 | 6 | ||||
others[3] | 1107 | 1 | T14 | 1 | T28 | 9 | T40 | 3 | ||||
false | 13006 | 1 | T1 | 18 | T2 | 5 | T3 | 1 | ||||
true | 3874 | 1 | T1 | 4 | T14 | 5 | T28 | 1 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |