Unified Coverage Report :: Module :: pwrmgr_rstmgr_sva_if

Module : pwrmgr_rstmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_rstmgr_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.pwrmgr_rstmgr_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : pwrmgr_rstmgr_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	33	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv' or '../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
33	1	1

---

Cond Coverage for Module : pwrmgr_rstmgr_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       33
 EXPRESSION (((!rst_slow_ni)) || disable_sva)
             --------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T4
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T10,T13

---

Assert Coverage for Module : pwrmgr_rstmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_assertions_per_power_domains[0].LcHandshakeOff_A	24082728	5931	0	0
gen_assertions_per_power_domains[0].LcHandshakeOn_A	24082728	264080	0	0
gen_assertions_per_power_domains[0].SysHandshakeOff_A	24082728	10033844	0	0
gen_assertions_per_power_domains[0].SysHandshakeOn_A	24082728	264085	0	0
gen_assertions_per_power_domains[1].LcHandshakeOff_A	24082728	5931	0	0
gen_assertions_per_power_domains[1].LcHandshakeOn_A	24082728	264080	0	0
gen_assertions_per_power_domains[1].SysHandshakeOff_A	24082728	10033844	0	0
gen_assertions_per_power_domains[1].SysHandshakeOn_A	24082728	264085	0	0

gen_assertions_per_power_domains[0].LcHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24082728	5931	0	0
T2	2722	1	0	0
T3	1110	0	0	0
T4	2528	0	0	0
T5	2295	1	0	0
T6	2298	0	0	0
T7	1136	0	0	0
T8	15653	0	0	0
T9	4233	0	0	0
T10	1206	3	0	0
T11	15035	0	0	0
T13	0	23	0	0
T25	0	22	0	0
T26	0	5	0	0
T43	0	27	0	0
T66	0	1	0	0
T82	0	1	0	0
T83	0	2	0	0

gen_assertions_per_power_domains[0].LcHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24082728	264080	0	0
T2	2722	177	0	0
T3	1110	0	0	0
T4	2528	0	0	0
T5	2295	13	0	0
T6	2298	0	0	0
T7	1136	0	0	0
T8	15653	0	0	0
T9	4233	0	0	0
T10	1206	265	0	0
T11	15035	0	0	0
T13	0	784	0	0
T25	0	1688	0	0
T26	0	147	0	0
T43	0	1844	0	0
T66	0	11	0	0
T82	0	12	0	0
T83	0	53	0	0

gen_assertions_per_power_domains[0].SysHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24082728	10033844	0	0
T2	2722	119	0	0
T3	1110	904	0	0
T4	2528	240	0	0
T5	2295	1424	0	0
T6	2298	0	0	0
T7	1136	836	0	0
T8	15653	0	0	0
T9	4233	0	0	0
T10	1206	632	0	0
T11	15035	0	0	0
T13	0	10906	0	0
T25	0	28433	0	0
T26	0	1868	0	0
T66	0	1257	0	0

gen_assertions_per_power_domains[0].SysHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24082728	264085	0	0
T2	2722	177	0	0
T3	1110	0	0	0
T4	2528	0	0	0
T5	2295	13	0	0
T6	2298	0	0	0
T7	1136	0	0	0
T8	15653	0	0	0
T9	4233	0	0	0
T10	1206	265	0	0
T11	15035	0	0	0
T13	0	784	0	0
T25	0	1688	0	0
T26	0	149	0	0
T43	0	1844	0	0
T66	0	11	0	0
T82	0	12	0	0
T83	0	53	0	0

gen_assertions_per_power_domains[1].LcHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24082728	5931	0	0
T2	2722	1	0	0
T3	1110	0	0	0
T4	2528	0	0	0
T5	2295	1	0	0
T6	2298	0	0	0
T7	1136	0	0	0
T8	15653	0	0	0
T9	4233	0	0	0
T10	1206	3	0	0
T11	15035	0	0	0
T13	0	23	0	0
T25	0	22	0	0
T26	0	5	0	0
T43	0	27	0	0
T66	0	1	0	0
T82	0	1	0	0
T83	0	2	0	0

gen_assertions_per_power_domains[1].LcHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24082728	264080	0	0
T2	2722	177	0	0
T3	1110	0	0	0
T4	2528	0	0	0
T5	2295	13	0	0
T6	2298	0	0	0
T7	1136	0	0	0
T8	15653	0	0	0
T9	4233	0	0	0
T10	1206	265	0	0
T11	15035	0	0	0
T13	0	784	0	0
T25	0	1688	0	0
T26	0	147	0	0
T43	0	1844	0	0
T66	0	11	0	0
T82	0	12	0	0
T83	0	53	0	0

gen_assertions_per_power_domains[1].SysHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24082728	10033844	0	0
T2	2722	119	0	0
T3	1110	904	0	0
T4	2528	240	0	0
T5	2295	1424	0	0
T6	2298	0	0	0
T7	1136	836	0	0
T8	15653	0	0	0
T9	4233	0	0	0
T10	1206	632	0	0
T11	15035	0	0	0
T13	0	10906	0	0
T25	0	28433	0	0
T26	0	1868	0	0
T66	0	1257	0	0

gen_assertions_per_power_domains[1].SysHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24082728	264085	0	0
T2	2722	177	0	0
T3	1110	0	0	0
T4	2528	0	0	0
T5	2295	13	0	0
T6	2298	0	0	0
T7	1136	0	0	0
T8	15653	0	0	0
T9	4233	0	0	0
T10	1206	265	0	0
T11	15035	0	0	0
T13	0	784	0	0
T25	0	1688	0	0
T26	0	149	0	0
T43	0	1844	0	0
T66	0	11	0	0
T82	0	12	0	0
T83	0	53	0	0