Unified Coverage Report :: Module :: pwrmgr_csr_assert_fpv

Module : pwrmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_pwrmgr_csr_assert_0/pwrmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.pwrmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : pwrmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	24657309	15915	0	0
intr_enable_rd_A	24657309	51524	0	0
reset_en_rd_A	24657309	1244	0	0
reset_en_regwen_rd_A	24657309	991	0	0
wake_info_capture_dis_rd_A	24657309	934	0	0
wakeup_en_rd_A	24657309	1923	0	0
wakeup_en_regwen_rd_A	24657309	1018	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24657309	15915	0	0
T22	731958	23	0	0
T23	572562	22	0	0
T24	0	15	0	0
T49	6335	0	0	0
T53	0	148	0	0
T54	0	33	0	0
T79	0	37	0	0
T85	12455	0	0	0
T86	3476	0	0	0
T87	29729	0	0	0
T94	3052	0	0	0
T95	4251	0	0	0
T96	2962	0	0	0
T97	29040	0	0	0
T98	0	30	0	0
T129	0	26	0	0
T130	0	28	0	0
T131	0	27	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24657309	51524	0	0
T15	2219	0	0	0
T17	3633	0	0	0
T22	0	3285	0	0
T25	54592	177	0	0
T26	3893	0	0	0
T27	4658	0	0	0
T28	2192	0	0	0
T40	2537	0	0	0
T44	0	420	0	0
T45	1782	0	0	0
T47	0	44	0	0
T49	0	6	0	0
T56	0	27	0	0
T66	2129	0	0	0
T83	0	4	0	0
T85	0	38	0	0
T88	2227	0	0	0
T132	0	16	0	0
T133	0	93	0	0

reset_en_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24657309	1244	0	0
T22	731958	6	0	0
T23	572562	2	0	0
T24	0	9	0	0
T49	6335	0	0	0
T85	12455	0	0	0
T86	3476	0	0	0
T87	29729	0	0	0
T90	0	8	0	0
T94	3052	0	0	0
T95	4251	0	0	0
T96	2962	0	0	0
T97	29040	0	0	0
T99	0	2	0	0
T130	0	10	0	0
T134	0	3	0	0
T135	0	6	0	0
T136	0	7	0	0
T137	0	5	0	0

reset_en_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24657309	991	0	0
T22	731958	9	0	0
T23	572562	13	0	0
T24	0	12	0	0
T49	6335	0	0	0
T85	12455	0	0	0
T86	3476	0	0	0
T87	29729	0	0	0
T90	0	1	0	0
T94	3052	0	0	0
T95	4251	0	0	0
T96	2962	0	0	0
T97	29040	0	0	0
T98	0	11	0	0
T130	0	9	0	0
T134	0	5	0	0
T135	0	2	0	0
T136	0	3	0	0
T138	0	9	0	0

wake_info_capture_dis_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24657309	934	0	0
T22	731958	1	0	0
T23	572562	4	0	0
T24	0	5	0	0
T49	6335	0	0	0
T85	12455	0	0	0
T86	3476	0	0	0
T87	29729	0	0	0
T90	0	3	0	0
T94	3052	0	0	0
T95	4251	0	0	0
T96	2962	0	0	0
T97	29040	0	0	0
T98	0	3	0	0
T130	0	2	0	0
T134	0	4	0	0
T135	0	4	0	0
T136	0	4	0	0
T138	0	2	0	0

wakeup_en_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24657309	1923	0	0
T22	731958	15	0	0
T23	572562	1	0	0
T24	0	8	0	0
T49	6335	0	0	0
T85	12455	0	0	0
T86	3476	0	0	0
T87	29729	0	0	0
T90	0	11	0	0
T94	3052	0	0	0
T95	4251	0	0	0
T96	2962	0	0	0
T97	29040	0	0	0
T98	0	4	0	0
T130	0	6	0	0
T134	0	8	0	0
T136	0	6	0	0
T137	0	10	0	0
T138	0	4	0	0

wakeup_en_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24657309	1018	0	0
T22	731958	9	0	0
T23	572562	9	0	0
T49	6335	0	0	0
T85	12455	0	0	0
T86	3476	0	0	0
T87	29729	0	0	0
T90	0	3	0	0
T94	3052	0	0	0
T95	4251	0	0	0
T96	2962	0	0	0
T97	29040	0	0	0
T98	0	3	0	0
T130	0	5	0	0
T134	0	5	0	0
T135	0	5	0	0
T136	0	10	0	0
T137	0	5	0	0
T138	0	1	0	0