Unified Coverage Report :: Module :: pwrmgr_sec_cm_checker_assert

Module : pwrmgr_sec_cm_checker_assert

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_sec_cm_checker_assert	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.pwrmgr_sec_cm_checker_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : pwrmgr_sec_cm_checker_assert

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	39	1	1	100.00
ALWAYS	40	1	1	100.00
ALWAYS	41	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv' or '../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
39	1	1
40	1	1
41	1	1

---

Cond Coverage for Module : pwrmgr_sec_cm_checker_assert

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       39
 EXPRESSION (((!rst_ni)) || disable_sva)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       40
 EXPRESSION (((!rst_esc_ni)) || disable_sva)
             -------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       41
 EXPRESSION (((!rst_slow_ni)) || disable_sva)
             --------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

---

Assert Coverage for Module : pwrmgr_sec_cm_checker_assert

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	10	10	100.00	10	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	10	10	100.00	10	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
RomAllowActiveState_A	24082728	55964	0	0
RomAllowCheckGoodState_A	24082728	56014	0	0
RomBlockActiveState_A	24082728	29508	0	0
RomBlockCheckGoodState_A	24082728	436657	0	0
RomIntgChkDisFalse_A	24082728	23452611	0	0
RomIntgChkDisTrue_A	24082728	130366	0	0
RstreqChkEsctimeout_A	24082728	4020	0	0
RstreqChkFsmterm_A	24082728	160	0	0
RstreqChkGlbesc_A	24082728	4021	0	0
RstreqChkMainpd_A	24082728	994437	0	0

RomAllowActiveState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24082728	55964	0	0
T1	6654	12	0	0
T2	2722	5	0	0
T3	1110	2	0	0
T4	2528	19	0	0
T5	2295	3	0	0
T6	2298	3	0	0
T7	1136	2	0	0
T8	15653	2	0	0
T9	4233	7	0	0
T10	1206	5	0	0

RomAllowCheckGoodState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24082728	56014	0	0
T1	6654	13	0	0
T2	2722	5	0	0
T3	1110	2	0	0
T4	2528	19	0	0
T5	2295	3	0	0
T6	2298	3	0	0
T7	1136	2	0	0
T8	15653	2	0	0
T9	4233	7	0	0
T10	1206	5	0	0

RomBlockActiveState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24082728	29508	0	0
T16	1803	0	0	0
T17	3633	0	0	0
T27	4658	882	0	0
T40	2537	0	0	0
T41	7691	0	0	0
T42	3215	0	0	0
T43	58478	0	0	0
T46	0	351	0	0
T49	0	1248	0	0
T56	6452	0	0	0
T57	3871	0	0	0
T82	2435	0	0	0
T101	0	443	0	0
T139	0	12	0	0
T140	0	262	0	0
T141	0	635	0	0
T142	0	1416	0	0
T143	0	1203	0	0
T144	0	88	0	0

RomBlockCheckGoodState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24082728	436657	0	0
T13	22310	1749	0	0
T15	2219	0	0	0
T22	0	4125	0	0
T25	54592	3976	0	0
T26	3893	183	0	0
T27	4658	970	0	0
T28	2192	0	0	0
T40	2537	0	0	0
T43	0	4015	0	0
T44	0	137	0	0
T45	1782	0	0	0
T46	0	55	0	0
T66	2129	0	0	0
T83	0	138	0	0
T88	2227	0	0	0
T133	0	3993	0	0

RomIntgChkDisFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24082728	23452611	0	0
T1	6654	5730	0	0
T2	2722	2308	0	0
T3	1110	1055	0	0
T4	2528	2430	0	0
T5	2295	2214	0	0
T6	2298	2064	0	0
T7	1136	1043	0	0
T8	15653	15589	0	0
T9	4233	3670	0	0
T10	1206	835	0	0

RomIntgChkDisTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24082728	130366	0	0
T13	22310	953	0	0
T15	2219	0	0	0
T25	54592	3560	0	0
T26	3893	0	0	0
T27	4658	0	0	0
T28	2192	0	0	0
T40	2537	0	0	0
T45	1782	0	0	0
T46	0	531	0	0
T49	0	2628	0	0
T66	2129	0	0	0
T88	2227	0	0	0
T101	0	1221	0	0
T133	0	1735	0	0
T140	0	122	0	0
T141	0	52	0	0
T142	0	2069	0	0
T145	0	983	0	0

RstreqChkEsctimeout_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24082728	4020	0	0
T1	6654	3	0	0
T2	2722	0	0	0
T3	1110	0	0	0
T4	2528	0	0	0
T5	2295	0	0	0
T6	2298	2	0	0
T7	1136	0	0	0
T8	15653	1	0	0
T9	4233	0	0	0
T10	1206	0	0	0
T11	0	1	0	0
T14	0	8	0	0
T27	0	4	0	0
T40	0	5	0	0
T41	0	4	0	0
T42	0	2	0	0
T45	0	4	0	0

RstreqChkFsmterm_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24082728	160	0	0
T19	47175	40	0	0
T20	0	20	0	0
T21	0	20	0	0
T29	0	40	0	0
T30	0	40	0	0
T31	4085	0	0	0
T32	19491	0	0	0
T33	1210	0	0	0
T34	2553	0	0	0
T35	1675	0	0	0
T36	18762	0	0	0
T37	14012	0	0	0
T38	9534	0	0	0
T39	3821	0	0	0

RstreqChkGlbesc_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24082728	4021	0	0
T1	6654	3	0	0
T2	2722	0	0	0
T3	1110	0	0	0
T4	2528	0	0	0
T5	2295	0	0	0
T6	2298	2	0	0
T7	1136	0	0	0
T8	15653	1	0	0
T9	4233	0	0	0
T10	1206	0	0	0
T11	0	1	0	0
T14	0	8	0	0
T27	0	4	0	0
T40	0	5	0	0
T41	0	4	0	0
T42	0	2	0	0
T45	0	4	0	0

RstreqChkMainpd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24082728	994437	0	0
T1	6654	290	0	0
T2	2722	0	0	0
T3	1110	0	0	0
T4	2528	0	0	0
T5	2295	0	0	0
T6	2298	0	0	0
T7	1136	0	0	0
T8	15653	0	0	0
T9	4233	27	0	0
T10	1206	0	0	0
T13	0	2749	0	0
T14	0	175	0	0
T17	0	26	0	0
T25	0	6101	0	0
T26	0	130	0	0
T27	0	1302	0	0
T40	0	107	0	0
T88	0	11	0	0