Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	416545	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

160634

1

T1

8

T2

62

T3

220

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	299996	1			T1	15		T2	79		T3	410
values[0x0]	138272	1			T1	6		T2	35		T3	207
values[0x1]	138911	1			T1	4		T2	33		T3	245

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	330090	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

247089

1

T1

13

T2

83

T3

374

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	2740	1			T9	5		T36	3		T39	22
valid_sources[0x01]	1762	1			T9	1		T13	1		T56	1
valid_sources[0x02]	4734	1			T9	1		T36	1		T13	2
valid_sources[0x03]	3488	1			T9	3		T36	3		T13	5
valid_sources[0x04]	1911	1			T13	1		T39	7		T14	47
valid_sources[0x05]	2405	1			T2	2		T36	1		T13	3
valid_sources[0x06]	4657	1			T1	5		T3	71		T9	2
valid_sources[0x07]	2589	1			T36	1		T13	1		T56	2
valid_sources[0x08]	2062	1			T9	1		T39	15		T14	47
valid_sources[0x09]	1741	1			T36	3		T39	1		T14	29
valid_sources[0x0a]	2758	1			T36	1		T13	1		T39	6
valid_sources[0x0b]	1687	1			T2	3		T13	2		T14	37
valid_sources[0x0c]	1737	1			T36	2		T13	1		T39	8
valid_sources[0x0d]	2755	1			T36	2		T13	2		T39	1
valid_sources[0x0e]	2505	1			T4	1		T13	2		T39	2
valid_sources[0x0f]	1773	1			T2	1		T4	2		T7	1
valid_sources[0x10]	2015	1			T2	2		T4	1		T9	2
valid_sources[0x11]	2365	1			T4	3		T9	4		T36	1
valid_sources[0x12]	1883	1			T3	3		T9	2		T13	1
valid_sources[0x13]	2084	1			T4	1		T9	2		T36	1
valid_sources[0x14]	1769	1			T7	1		T13	1		T14	42
valid_sources[0x15]	1733	1			T9	1		T13	1		T39	3
valid_sources[0x16]	2862	1			T9	1		T13	1		T39	2
valid_sources[0x17]	3449	1			T4	1		T7	1		T9	2
valid_sources[0x18]	2299	1			T4	1		T13	7		T14	80
valid_sources[0x19]	2057	1			T3	16		T7	1		T36	1
valid_sources[0x1a]	1943	1			T36	3		T13	2		T39	11
valid_sources[0x1b]	2660	1			T3	11		T14	45		T15	12
valid_sources[0x1c]	1719	1			T7	1		T9	1		T36	2
valid_sources[0x1d]	1843	1			T1	2		T9	1		T36	2
valid_sources[0x1e]	1782	1			T7	1		T9	1		T13	1
valid_sources[0x1f]	1902	1			T2	2		T4	2		T9	2
valid_sources[0x20]	1664	1			T3	56		T9	2		T36	1
valid_sources[0x21]	2836	1			T36	2		T13	2		T39	1
valid_sources[0x22]	2032	1			T36	4		T39	1		T56	1
valid_sources[0x23]	1816	1			T7	1		T13	4		T14	46
valid_sources[0x24]	2036	1			T2	2		T14	17		T15	21
valid_sources[0x25]	1948	1			T2	3		T36	1		T11	1
valid_sources[0x26]	1726	1			T2	1		T8	1		T13	2
valid_sources[0x27]	1956	1			T1	3		T36	1		T13	2
valid_sources[0x28]	2220	1			T9	1		T13	3		T37	256
valid_sources[0x29]	1911	1			T36	1		T13	1		T39	2
valid_sources[0x2a]	1774	1			T7	1		T9	5		T56	4
valid_sources[0x2b]	4366	1			T4	3		T7	2		T9	1
valid_sources[0x2c]	1890	1			T9	2		T13	1		T39	3
valid_sources[0x2d]	3373	1			T3	60		T36	1		T13	1
valid_sources[0x2e]	2536	1			T4	1		T7	1		T9	2
valid_sources[0x2f]	2512	1			T9	4		T36	1		T39	8
valid_sources[0x30]	2085	1			T2	1		T39	14		T14	40
valid_sources[0x31]	1824	1			T2	5		T36	1		T13	1
valid_sources[0x32]	1860	1			T4	1		T13	1		T39	10
valid_sources[0x33]	1846	1			T9	1		T13	1		T39	9
valid_sources[0x34]	1851	1			T2	5		T3	43		T4	1
valid_sources[0x35]	2137	1			T14	41		T15	31		T81	1
valid_sources[0x36]	1944	1			T9	4		T36	2		T13	3
valid_sources[0x37]	1671	1			T2	2		T9	1		T14	38
valid_sources[0x38]	2802	1			T36	1		T13	1		T39	7
valid_sources[0x39]	1863	1			T4	2		T36	2		T13	1
valid_sources[0x3a]	1745	1			T9	2		T13	1		T39	3
valid_sources[0x3b]	3033	1			T3	10		T4	1		T6	861
valid_sources[0x3c]	1957	1			T2	2		T36	2		T13	2
valid_sources[0x3d]	2630	1			T4	2		T9	1		T36	1
valid_sources[0x3e]	1890	1			T4	1		T7	1		T9	1
valid_sources[0x3f]	2570	1			T2	4		T36	3		T13	1
valid_sources[0x40]	2109	1			T4	1		T7	2		T9	1
valid_sources[0x41]	1861	1			T4	1		T9	2		T36	1
valid_sources[0x42]	2055	1			T3	32		T4	1		T36	1
valid_sources[0x43]	2377	1			T36	3		T42	1		T14	38
valid_sources[0x44]	1729	1			T2	2		T13	3		T56	2
valid_sources[0x45]	1991	1			T9	2		T13	1		T56	1
valid_sources[0x46]	1897	1			T9	3		T13	2		T39	2
valid_sources[0x47]	1719	1			T2	1		T7	1		T14	27
valid_sources[0x48]	1892	1			T2	1		T13	2		T14	58
valid_sources[0x49]	2586	1			T9	4		T36	1		T14	56
valid_sources[0x4a]	2416	1			T7	1		T13	1		T56	2
valid_sources[0x4b]	2025	1			T4	1		T13	2		T56	1
valid_sources[0x4c]	1956	1			T2	1		T13	1		T56	1
valid_sources[0x4d]	1837	1			T7	1		T36	1		T13	1
valid_sources[0x4e]	1827	1			T39	6		T14	37		T15	29
valid_sources[0x4f]	1706	1			T4	3		T7	1		T9	2
valid_sources[0x50]	1791	1			T9	1		T36	2		T13	1
valid_sources[0x51]	1631	1			T2	1		T9	2		T13	2
valid_sources[0x52]	2788	1			T7	1		T9	1		T36	1
valid_sources[0x53]	1925	1			T2	6		T4	2		T7	2
valid_sources[0x54]	1848	1			T39	8		T14	32		T15	39
valid_sources[0x55]	2926	1			T2	2		T36	1		T13	1
valid_sources[0x56]	2299	1			T7	2		T13	1		T14	47
valid_sources[0x57]	3942	1			T2	3		T36	1		T13	1
valid_sources[0x58]	1978	1			T36	1		T13	1		T56	1
valid_sources[0x59]	1734	1			T7	2		T10	5		T13	2
valid_sources[0x5a]	2822	1			T13	3		T39	7		T14	39
valid_sources[0x5b]	1793	1			T9	2		T13	3		T14	66
valid_sources[0x5c]	2411	1			T2	6		T9	2		T13	1
valid_sources[0x5d]	1718	1			T4	2		T9	2		T36	2
valid_sources[0x5e]	1655	1			T36	1		T13	1		T56	2
valid_sources[0x5f]	1942	1			T3	22		T36	1		T13	1
valid_sources[0x60]	1775	1			T13	1		T39	2		T14	30
valid_sources[0x61]	1650	1			T4	2		T36	1		T13	3
valid_sources[0x62]	1779	1			T9	1		T36	2		T13	4
valid_sources[0x63]	1989	1			T2	1		T36	1		T13	1
valid_sources[0x64]	4889	1			T1	4		T2	1		T13	4
valid_sources[0x65]	1966	1			T4	1		T7	2		T36	2
valid_sources[0x66]	1784	1			T9	1		T36	1		T13	2
valid_sources[0x67]	1780	1			T2	1		T9	2		T36	1
valid_sources[0x68]	4633	1			T4	1		T9	5		T39	1
valid_sources[0x69]	1991	1			T2	1		T3	6		T36	1
valid_sources[0x6a]	4199	1			T4	1		T36	1		T13	1
valid_sources[0x6b]	1821	1			T9	1		T36	1		T13	4
valid_sources[0x6c]	3094	1			T9	1		T36	2		T39	1
valid_sources[0x6d]	1769	1			T7	1		T9	3		T36	2
valid_sources[0x6e]	2411	1			T3	59		T7	2		T9	2
valid_sources[0x6f]	2198	1			T9	3		T36	1		T13	4
valid_sources[0x70]	1811	1			T4	1		T7	1		T9	3
valid_sources[0x71]	1804	1			T2	3		T7	1		T13	1
valid_sources[0x72]	2875	1			T4	1		T9	3		T36	1
valid_sources[0x73]	2810	1			T2	2		T7	2		T13	1
valid_sources[0x74]	3026	1			T1	1		T9	2		T13	1
valid_sources[0x75]	1751	1			T3	11		T9	1		T13	1
valid_sources[0x76]	2078	1			T36	3		T56	1		T14	26
valid_sources[0x77]	2610	1			T36	1		T13	1		T14	37
valid_sources[0x78]	1950	1			T9	1		T36	2		T39	2
valid_sources[0x79]	1829	1			T3	6		T7	1		T9	3
valid_sources[0x7a]	1878	1			T2	3		T9	6		T36	1
valid_sources[0x7b]	2264	1			T9	2		T36	1		T14	43
valid_sources[0x7c]	2204	1			T2	2		T9	3		T36	2
valid_sources[0x7d]	2743	1			T2	1		T3	3		T4	1
valid_sources[0x7e]	1673	1			T9	3		T39	3		T14	30
valid_sources[0x7f]	4311	1			T9	1		T13	1		T39	3
valid_sources[0x80]	3729	1			T36	2		T39	4		T14	40

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

80587

1

T1

6

T2

39

T3

95

values[0x0]

all_enables

biggest_size

51586

1

T1

2

T2

13

T3

87

values[0x1]

all_enables

biggest_size

28461

1

T2

10

T3

38

T4

1