SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING |
100.00 | 100.00 | 1 | 100 | 1 | 1 | 64 | 64 |
NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_rom_ctrl_done_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_rom_ctrl_good_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_sw_rst_req_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 35012 | 1 | T3 | 394 | T6 | 404 | T38 | 418 | ||||
others[1] | 34928 | 1 | T3 | 400 | T6 | 414 | T38 | 408 | ||||
others[2] | 34958 | 1 | T3 | 391 | T6 | 402 | T38 | 348 | ||||
others[3] | 58382 | 1 | T3 | 654 | T6 | 667 | T7 | 1 | ||||
false | 16667 | 1 | T3 | 50 | T4 | 10 | T6 | 50 | ||||
true | 25424 | 1 | T1 | 1 | T2 | 1 | T3 | 102 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 35024 | 1 | T3 | 396 | T6 | 386 | T7 | 1 | ||||
others[1] | 34965 | 1 | T3 | 396 | T6 | 411 | T38 | 359 | ||||
others[2] | 34917 | 1 | T3 | 389 | T6 | 395 | T38 | 430 | ||||
others[3] | 58487 | 1 | T3 | 690 | T6 | 681 | T7 | 1 | ||||
false | 10927 | 1 | T3 | 50 | T4 | 5 | T6 | 50 | ||||
true | 19749 | 1 | T1 | 1 | T2 | 1 | T3 | 102 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 555 | 1 | T10 | 2 | T13 | 1 | T23 | 1 | ||||
others[1] | 572 | 1 | T7 | 1 | T10 | 1 | T23 | 1 | ||||
others[2] | 534 | 1 | T14 | 4 | T15 | 5 | T40 | 2 | ||||
others[3] | 1002 | 1 | T7 | 1 | T10 | 2 | T13 | 1 | ||||
false | 10756 | 1 | T1 | 1 | T2 | 1 | T3 | 2 | ||||
true | 2979 | 1 | T7 | 2 | T10 | 6 | T13 | 8 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |