Unified Coverage Report :: Group :: pwrmgr_env_pkg::pwrmgr_wakeup_ctrl_cg_wrap::wakeup_ctrl_cg

Group : pwrmgr_env_pkg::pwrmgr_wakeup_ctrl_cg_wrap::wakeup_ctrl_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_env_0.1/pwrmgr_env_cov.sv

6 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
WakeupAonTimer_ctrl_cg	100.00	1	100	1	64	64
WakeupDbgCable_ctrl_cg	100.00	1	100	1	64	64
WakeupPin_ctrl_cg	100.00	1	100	1	64	64
WakeupSensorCtrl_ctrl_cg	100.00	1	100	1	64	64
WakeupSysrst_ctrl_cg	100.00	1	100	1	64	64
WakeupUsb_ctrl_cg	100.00	1	100	1	64	64

---

Group Instance : WakeupAonTimer_ctrl_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance WakeupAonTimer_ctrl_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	6	0	6	100.00
Crosses	8	0	8	100.00

Variables for Group Instance WakeupAonTimer_ctrl_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
capture_cp	2	0	2	100.00	100	1	1	2
enable_cp	2	0	2	100.00	100	1	1	2
wakeup_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance WakeupAonTimer_ctrl_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
wakeup_cross	8	0	8	100.00	100	1	1	0

---

Group Instance : WakeupDbgCable_ctrl_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance WakeupDbgCable_ctrl_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	6	0	6	100.00
Crosses	8	0	8	100.00

Variables for Group Instance WakeupDbgCable_ctrl_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
capture_cp	2	0	2	100.00	100	1	1	2
enable_cp	2	0	2	100.00	100	1	1	2
wakeup_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance WakeupDbgCable_ctrl_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
wakeup_cross	8	0	8	100.00	100	1	1	0

---

Group Instance : WakeupPin_ctrl_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance WakeupPin_ctrl_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	6	0	6	100.00
Crosses	8	0	8	100.00

Variables for Group Instance WakeupPin_ctrl_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
capture_cp	2	0	2	100.00	100	1	1	2
enable_cp	2	0	2	100.00	100	1	1	2
wakeup_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance WakeupPin_ctrl_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
wakeup_cross	8	0	8	100.00	100	1	1	0

---

Group Instance : WakeupSensorCtrl_ctrl_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance WakeupSensorCtrl_ctrl_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	6	0	6	100.00
Crosses	8	0	8	100.00

Variables for Group Instance WakeupSensorCtrl_ctrl_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
capture_cp	2	0	2	100.00	100	1	1	2
enable_cp	2	0	2	100.00	100	1	1	2
wakeup_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance WakeupSensorCtrl_ctrl_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
wakeup_cross	8	0	8	100.00	100	1	1	0

---

Group Instance : WakeupSysrst_ctrl_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance WakeupSysrst_ctrl_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	6	0	6	100.00
Crosses	8	0	8	100.00

Variables for Group Instance WakeupSysrst_ctrl_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
capture_cp	2	0	2	100.00	100	1	1	2
enable_cp	2	0	2	100.00	100	1	1	2
wakeup_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance WakeupSysrst_ctrl_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
wakeup_cross	8	0	8	100.00	100	1	1	0

---

Group Instance : WakeupUsb_ctrl_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance WakeupUsb_ctrl_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	6	0	6	100.00
Crosses	8	0	8	100.00

Variables for Group Instance WakeupUsb_ctrl_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
capture_cp	2	0	2	100.00	100	1	1	2
enable_cp	2	0	2	100.00	100	1	1	2
wakeup_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance WakeupUsb_ctrl_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
wakeup_cross	8	0	8	100.00	100	1	1	0

Summary for Variable capture_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for capture_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

6288

1

T5

3

T7

7

T8

15

auto[1]

17909

1

T4

1

T5

3

T6

1

---

Summary for Variable enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for enable_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

10796

1

T5

2

T7

9

T8

31

auto[1]

13401

1

T4

1

T5

4

T6

1

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

11317

1

T5

3

T6

1

T7

6

auto[1]

12880

1

T4

1

T5

3

T7

14

---

Summary for Cross wakeup_cross

Samples crossed: enable_cp capture_cp wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for wakeup_cross

Bins

enable_cp	capture_cp	wakeup_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	1413	1			T5	1		T7	2		T8	2
auto[0]	auto[0]	auto[1]	1470	1			T7	2		T8	2		T41	1
auto[0]	auto[1]	auto[0]	4037	1			T5	1		T7	2		T8	15
auto[0]	auto[1]	auto[1]	3876	1			T7	3		T8	12		T26	12
auto[1]	auto[0]	auto[0]	1469	1			T7	1		T8	4		T41	6
auto[1]	auto[0]	auto[1]	1936	1			T5	2		T7	2		T8	7
auto[1]	auto[1]	auto[0]	4398	1			T5	1		T6	1		T7	1
auto[1]	auto[1]	auto[1]	5598	1			T4	1		T5	1		T7	7

Summary for Variable capture_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for capture_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

6288

1

T5

3

T7

7

T8

15

auto[1]

17909

1

T4

1

T5

3

T6

1

---

Summary for Variable enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for enable_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

10750

1

T5

2

T7

9

T8

35

auto[1]

13447

1

T4

1

T5

4

T6

1

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

11477

1

T4

1

T5

2

T7

7

auto[1]

12720

1

T5

4

T6

1

T7

13

---

Summary for Cross wakeup_cross

Samples crossed: enable_cp capture_cp wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for wakeup_cross

Bins

enable_cp	capture_cp	wakeup_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	1427	1			T7	1		T8	7		T41	3
auto[0]	auto[0]	auto[1]	1411	1			T5	1		T7	3		T8	2
auto[0]	auto[1]	auto[0]	4076	1			T7	1		T8	14		T26	9
auto[0]	auto[1]	auto[1]	3836	1			T5	1		T7	4		T8	12
auto[1]	auto[0]	auto[0]	1430	1			T5	1		T7	1		T8	2
auto[1]	auto[0]	auto[1]	2020	1			T5	1		T7	2		T8	4
auto[1]	auto[1]	auto[0]	4544	1			T4	1		T5	1		T7	4
auto[1]	auto[1]	auto[1]	5453	1			T5	1		T6	1		T7	4

Summary for Variable capture_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for capture_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

6288

1

T5

3

T7

7

T8

15

auto[1]

17909

1

T4

1

T5

3

T6

1

---

Summary for Variable enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for enable_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

10941

1

T5

4

T7

10

T8

37

auto[1]

13256

1

T4

1

T5

2

T6

1

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

11482

1

T5

4

T6

1

T7

8

auto[1]

12715

1

T4

1

T5

2

T7

12

---

Summary for Cross wakeup_cross

Samples crossed: enable_cp capture_cp wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for wakeup_cross

Bins

enable_cp	capture_cp	wakeup_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	1433	1			T5	1		T7	1		T8	3
auto[0]	auto[0]	auto[1]	1494	1			T5	1		T7	3		T8	6
auto[0]	auto[1]	auto[0]	4188	1			T5	2		T7	3		T8	18
auto[0]	auto[1]	auto[1]	3826	1			T7	3		T8	10		T26	13
auto[1]	auto[0]	auto[0]	1439	1			T7	1		T8	3		T41	2
auto[1]	auto[0]	auto[1]	1922	1			T5	1		T7	2		T8	3
auto[1]	auto[1]	auto[0]	4422	1			T5	1		T6	1		T7	3
auto[1]	auto[1]	auto[1]	5473	1			T4	1		T7	4		T8	26

Summary for Variable capture_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for capture_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

6288

1

T5

3

T7

7

T8

15

auto[1]

17909

1

T4

1

T5

3

T6

1

---

Summary for Variable enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for enable_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

10871

1

T5

4

T7

8

T8

31

auto[1]

13326

1

T4

1

T5

2

T6

1

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

11585

1

T4

1

T5

3

T6

1

auto[1]

12612

1

T5

3

T7

13

T8

38

---

Summary for Cross wakeup_cross

Samples crossed: enable_cp capture_cp wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for wakeup_cross

Bins

enable_cp	capture_cp	wakeup_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	1424	1			T5	1		T7	1		T8	1
auto[0]	auto[0]	auto[1]	1386	1			T5	1		T7	1		T8	2
auto[0]	auto[1]	auto[0]	4288	1			T5	2		T7	2		T8	16
auto[0]	auto[1]	auto[1]	3773	1			T7	4		T8	12		T26	10
auto[1]	auto[0]	auto[0]	1511	1			T7	1		T8	7		T41	2
auto[1]	auto[0]	auto[1]	1967	1			T5	1		T7	4		T8	5
auto[1]	auto[1]	auto[0]	4362	1			T4	1		T6	1		T7	3
auto[1]	auto[1]	auto[1]	5486	1			T5	1		T7	4		T8	19

Summary for Variable capture_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for capture_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

6288

1

T5

3

T7

7

T8

15

auto[1]

17909

1

T4

1

T5

3

T6

1

---

Summary for Variable enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for enable_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

10868

1

T5

2

T7

13

T8

39

auto[1]

13329

1

T4

1

T5

4

T6

1

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

11538

1

T4

1

T5

3

T6

1

auto[1]

12659

1

T5

3

T7

11

T8

45

---

Summary for Cross wakeup_cross

Samples crossed: enable_cp capture_cp wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for wakeup_cross

Bins

enable_cp	capture_cp	wakeup_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	1414	1			T7	3		T8	1		T41	4
auto[0]	auto[0]	auto[1]	1440	1			T7	2		T8	7		T41	3
auto[0]	auto[1]	auto[0]	4211	1			T5	2		T7	3		T8	17
auto[0]	auto[1]	auto[1]	3803	1			T7	5		T8	14		T26	6
auto[1]	auto[0]	auto[0]	1446	1			T5	1		T7	2		T8	3
auto[1]	auto[0]	auto[1]	1988	1			T5	2		T8	4		T41	1
auto[1]	auto[1]	auto[0]	4467	1			T4	1		T6	1		T7	1
auto[1]	auto[1]	auto[1]	5428	1			T5	1		T7	4		T8	20

Summary for Variable capture_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for capture_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

6288

1

T5

3

T7

7

T8

15

auto[1]

17909

1

T4

1

T5

3

T6

1

---

Summary for Variable enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for enable_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

10875

1

T5

3

T7

8

T8

43

auto[1]

13322

1

T4

1

T5

3

T6

1

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

11659

1

T4

1

T5

2

T7

5

auto[1]

12538

1

T5

4

T6

1

T7

15

---

Summary for Cross wakeup_cross

Samples crossed: enable_cp capture_cp wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for wakeup_cross

Bins

enable_cp	capture_cp	wakeup_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	1466	1			T8	4		T41	1		T13	9
auto[0]	auto[0]	auto[1]	1403	1			T5	2		T7	2		T8	3
auto[0]	auto[1]	auto[0]	4201	1			T5	1		T7	3		T8	16
auto[0]	auto[1]	auto[1]	3805	1			T7	3		T8	20		T26	16
auto[1]	auto[0]	auto[0]	1462	1			T5	1		T7	2		T8	5
auto[1]	auto[0]	auto[1]	1957	1			T7	3		T8	3		T41	4
auto[1]	auto[1]	auto[0]	4530	1			T4	1		T8	17		T26	7
auto[1]	auto[1]	auto[1]	5373	1			T5	2		T6	1		T7	7