Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	458665	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

182562

1

T1

9

T2

39

T3

1

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	337735	1			T1	34		T2	182		T3	1
values[0x0]	151562	1			T1	16		T2	38		T4	4
values[0x1]	151930	1			T1	6		T2	24		T4	6

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	363477	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

277750

1

T1

21

T2

99

T3

1

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	1947	1			T2	6		T8	6		T26	14
valid_sources[0x01]	2072	1			T2	2		T8	11		T26	4
valid_sources[0x02]	1891	1			T8	2		T13	14		T20	2
valid_sources[0x03]	1961	1			T8	1		T26	1		T13	10
valid_sources[0x04]	1997	1			T7	1		T8	5		T26	3
valid_sources[0x05]	2120	1			T7	1		T8	5		T13	10
valid_sources[0x06]	2302	1			T2	1		T8	2		T26	6
valid_sources[0x07]	1986	1			T8	3		T13	16		T38	2
valid_sources[0x08]	3853	1			T8	11		T13	11		T20	2
valid_sources[0x09]	2104	1			T2	4		T8	13		T26	3
valid_sources[0x0a]	1920	1			T7	1		T8	4		T26	7
valid_sources[0x0b]	2985	1			T8	35		T13	15		T20	3
valid_sources[0x0c]	2206	1			T8	14		T26	5		T13	6
valid_sources[0x0d]	5713	1			T7	1		T8	3		T13	13
valid_sources[0x0e]	1968	1			T26	1		T13	14		T38	5
valid_sources[0x0f]	3343	1			T8	3		T26	5		T13	13
valid_sources[0x10]	2175	1			T2	1		T8	12		T26	4
valid_sources[0x11]	1828	1			T8	1		T26	3		T13	15
valid_sources[0x12]	1980	1			T8	6		T26	8		T13	9
valid_sources[0x13]	3547	1			T7	1		T8	5		T41	281
valid_sources[0x14]	3196	1			T2	3		T8	17		T13	17
valid_sources[0x15]	1925	1			T8	1		T26	2		T13	6
valid_sources[0x16]	2177	1			T8	12		T26	17		T13	11
valid_sources[0x17]	2372	1			T6	3		T8	5		T26	3
valid_sources[0x18]	1935	1			T7	4		T26	4		T13	14
valid_sources[0x19]	1905	1			T8	15		T26	2		T13	7
valid_sources[0x1a]	2251	1			T7	5		T8	2		T26	1
valid_sources[0x1b]	2456	1			T7	1		T8	5		T13	6
valid_sources[0x1c]	2067	1			T8	9		T26	3		T13	12
valid_sources[0x1d]	2494	1			T2	1		T8	4		T13	7
valid_sources[0x1e]	1749	1			T6	2		T26	7		T13	18
valid_sources[0x1f]	2146	1			T26	1		T13	13		T20	2
valid_sources[0x20]	1979	1			T8	6		T26	4		T13	14
valid_sources[0x21]	2091	1			T8	10		T26	1		T13	10
valid_sources[0x22]	2394	1			T7	2		T8	7		T26	3
valid_sources[0x23]	1935	1			T2	13		T8	12		T26	1
valid_sources[0x24]	2545	1			T7	11		T8	15		T26	2
valid_sources[0x25]	3014	1			T8	2		T26	4		T13	15
valid_sources[0x26]	2203	1			T8	6		T26	7		T13	7
valid_sources[0x27]	2913	1			T2	5		T8	2		T26	4
valid_sources[0x28]	2782	1			T8	8		T26	1		T13	7
valid_sources[0x29]	9292	1			T8	11		T26	5		T13	18
valid_sources[0x2a]	2374	1			T8	2		T26	5		T13	14
valid_sources[0x2b]	2069	1			T8	9		T13	13		T20	2
valid_sources[0x2c]	3762	1			T8	17		T26	1		T13	11
valid_sources[0x2d]	2075	1			T2	1		T7	3		T8	18
valid_sources[0x2e]	2599	1			T8	9		T13	8		T157	1
valid_sources[0x2f]	1942	1			T8	9		T26	11		T13	14
valid_sources[0x30]	1962	1			T2	1		T8	7		T26	1
valid_sources[0x31]	2584	1			T7	3		T8	13		T13	13
valid_sources[0x32]	2144	1			T6	6		T7	4		T8	21
valid_sources[0x33]	2040	1			T8	2		T13	16		T20	1
valid_sources[0x34]	2409	1			T2	1		T8	13		T26	5
valid_sources[0x35]	1996	1			T8	12		T26	5		T13	10
valid_sources[0x36]	2575	1			T2	1		T8	14		T26	4
valid_sources[0x37]	2619	1			T2	8		T26	11		T13	13
valid_sources[0x38]	10313	1			T2	1		T8	12		T26	7
valid_sources[0x39]	2648	1			T7	8		T8	8		T13	13
valid_sources[0x3a]	2374	1			T2	5		T8	7		T13	11
valid_sources[0x3b]	2312	1			T2	9		T7	2		T8	7
valid_sources[0x3c]	1991	1			T8	7		T26	11		T13	11
valid_sources[0x3d]	2087	1			T2	1		T7	2		T8	15
valid_sources[0x3e]	2758	1			T26	11		T13	11		T20	2
valid_sources[0x3f]	2080	1			T8	4		T13	9		T20	3
valid_sources[0x40]	2781	1			T2	1		T8	2		T26	8
valid_sources[0x41]	1943	1			T2	7		T8	5		T26	6
valid_sources[0x42]	1962	1			T1	56		T2	1		T8	1
valid_sources[0x43]	1924	1			T8	2		T26	2		T13	11
valid_sources[0x44]	2066	1			T8	7		T26	2		T13	3
valid_sources[0x45]	2160	1			T2	2		T8	2		T26	11
valid_sources[0x46]	4009	1			T8	5		T26	6		T13	12
valid_sources[0x47]	2208	1			T8	1		T26	7		T13	15
valid_sources[0x48]	2149	1			T2	1		T8	1		T26	4
valid_sources[0x49]	2094	1			T8	5		T26	6		T13	12
valid_sources[0x4a]	1994	1			T6	4		T8	22		T13	14
valid_sources[0x4b]	3587	1			T8	1		T13	4		T14	3
valid_sources[0x4c]	4515	1			T8	1		T26	2		T13	5
valid_sources[0x4d]	2066	1			T2	5		T8	13		T26	4
valid_sources[0x4e]	1998	1			T8	13		T13	12		T38	2
valid_sources[0x4f]	1880	1			T2	3		T7	7		T8	6
valid_sources[0x50]	2119	1			T26	2		T13	15		T20	1
valid_sources[0x51]	2251	1			T8	4		T26	4		T13	12
valid_sources[0x52]	2447	1			T8	9		T13	12		T11	1
valid_sources[0x53]	2011	1			T2	3		T7	12		T8	6
valid_sources[0x54]	2020	1			T2	2		T8	9		T13	12
valid_sources[0x55]	2028	1			T7	7		T8	1		T26	3
valid_sources[0x56]	2045	1			T2	1		T5	91		T8	3
valid_sources[0x57]	3862	1			T2	7		T8	19		T26	11
valid_sources[0x58]	1986	1			T7	6		T8	20		T26	4
valid_sources[0x59]	1898	1			T6	2		T8	5		T13	8
valid_sources[0x5a]	1898	1			T8	4		T10	1		T13	10
valid_sources[0x5b]	2352	1			T2	2		T8	9		T26	3
valid_sources[0x5c]	1816	1			T8	2		T13	15		T20	1
valid_sources[0x5d]	2927	1			T8	11		T13	11		T20	1
valid_sources[0x5e]	1862	1			T4	9		T7	5		T26	2
valid_sources[0x5f]	2471	1			T8	3		T13	10		T20	1
valid_sources[0x60]	2078	1			T8	3		T26	3		T13	6
valid_sources[0x61]	2786	1			T2	2		T6	1		T7	2
valid_sources[0x62]	2077	1			T2	4		T7	6		T8	8
valid_sources[0x63]	2780	1			T2	4		T3	1		T7	5
valid_sources[0x64]	1945	1			T2	1		T8	6		T13	11
valid_sources[0x65]	1886	1			T2	2		T8	7		T26	2
valid_sources[0x66]	2114	1			T8	8		T26	2		T13	17
valid_sources[0x67]	2909	1			T2	1		T7	3		T8	21
valid_sources[0x68]	1876	1			T8	5		T26	7		T13	9
valid_sources[0x69]	3383	1			T2	2		T8	25		T26	17
valid_sources[0x6a]	2035	1			T2	1		T8	4		T13	7
valid_sources[0x6b]	1946	1			T8	2		T26	4		T13	12
valid_sources[0x6c]	2457	1			T2	1		T26	2		T13	13
valid_sources[0x6d]	2139	1			T7	7		T13	8		T20	2
valid_sources[0x6e]	2412	1			T2	1		T8	2		T26	3
valid_sources[0x6f]	2573	1			T8	9		T26	1		T13	12
valid_sources[0x70]	2861	1			T8	1		T13	11		T20	3
valid_sources[0x71]	2081	1			T4	3		T8	12		T26	2
valid_sources[0x72]	2153	1			T8	5		T26	9		T13	11
valid_sources[0x73]	14299	1			T8	7		T13	10		T38	4
valid_sources[0x74]	1864	1			T2	1		T8	12		T26	19
valid_sources[0x75]	3384	1			T6	1		T7	1		T8	3
valid_sources[0x76]	2616	1			T8	18		T26	3		T13	15
valid_sources[0x77]	2007	1			T2	2		T8	9		T13	13
valid_sources[0x78]	2422	1			T2	1		T8	3		T26	5
valid_sources[0x79]	2103	1			T8	20		T26	8		T13	6
valid_sources[0x7a]	3088	1			T8	13		T26	1		T13	9
valid_sources[0x7b]	2390	1			T7	2		T8	13		T26	4
valid_sources[0x7c]	2950	1			T2	4		T8	1		T26	3
valid_sources[0x7d]	2057	1			T8	3		T13	9		T20	1
valid_sources[0x7e]	3167	1			T8	2		T26	1		T13	9
valid_sources[0x7f]	2200	1			T8	5		T9	115		T26	3
valid_sources[0x80]	3098	1			T8	24		T26	14		T13	11

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

93539

1

T1

2

T2

14

T3

1

values[0x0]

all_enables

biggest_size

57168

1

T1

4

T2

20

T5

9

values[0x1]

all_enables

biggest_size

31855

1

T1

3

T2

5

T5

2