SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING |
100.00 | 100.00 | 1 | 100 | 1 | 1 | 64 | 64 |
NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_rom_ctrl_done_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_rom_ctrl_good_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_sw_rst_req_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 35017 | 1 | T1 | 1 | T26 | 382 | T24 | 290 | ||||
others[1] | 35299 | 1 | T26 | 426 | T24 | 279 | T50 | 426 | ||||
others[2] | 34968 | 1 | T26 | 390 | T24 | 298 | T50 | 413 | ||||
others[3] | 58357 | 1 | T26 | 674 | T24 | 541 | T50 | 665 | ||||
false | 17313 | 1 | T1 | 3 | T8 | 82 | T26 | 50 | ||||
true | 26670 | 1 | T1 | 5 | T2 | 1 | T3 | 6 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 34945 | 1 | T26 | 408 | T24 | 297 | T50 | 389 | ||||
others[1] | 34828 | 1 | T26 | 421 | T24 | 315 | T50 | 402 | ||||
others[2] | 35070 | 1 | T26 | 377 | T24 | 297 | T50 | 423 | ||||
others[3] | 58760 | 1 | T26 | 653 | T24 | 508 | T50 | 657 | ||||
false | 11252 | 1 | T1 | 4 | T8 | 41 | T26 | 50 | ||||
true | 20658 | 1 | T1 | 6 | T2 | 1 | T3 | 6 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 591 | 1 | T2 | 6 | T42 | 5 | T157 | 6 | ||||
others[1] | 614 | 1 | T2 | 5 | T8 | 4 | T9 | 1 | ||||
others[2] | 603 | 1 | T2 | 6 | T8 | 3 | T9 | 3 | ||||
others[3] | 978 | 1 | T1 | 1 | T2 | 7 | T8 | 2 | ||||
false | 11843 | 1 | T1 | 7 | T2 | 5 | T3 | 6 | ||||
true | 3322 | 1 | T1 | 4 | T2 | 4 | T8 | 13 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |