Unified Coverage Report :: Module :: pwrmgr_csr_assert_fpv

Module : pwrmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_pwrmgr_csr_assert_0/pwrmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.pwrmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : pwrmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	23104563	16785	0	0
intr_enable_rd_A	23104563	36702	0	0
reset_en_rd_A	23104563	1321	0	0
reset_en_regwen_rd_A	23104563	1072	0	0
wake_info_capture_dis_rd_A	23104563	1246	0	0
wakeup_en_rd_A	23104563	2070	0	0
wakeup_en_regwen_rd_A	23104563	1140	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23104563	16785	0	0
T21	477150	8	0	0
T22	0	73	0	0
T23	0	2	0	0
T49	1925	0	0	0
T75	0	11	0	0
T76	0	9	0	0
T77	0	2	0	0
T87	0	6	0	0
T100	0	3	0	0
T145	48068	0	0	0
T148	0	1	0	0
T149	0	105	0	0
T150	2178	0	0	0
T151	15063	0	0	0
T152	7525	0	0	0
T153	825	0	0	0
T154	5031	0	0	0
T155	21740	0	0	0
T156	1765	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23104563	36702	0	0
T1	1561	12	0	0
T2	5202	0	0	0
T3	1224	0	0	0
T4	2529	0	0	0
T5	1550	0	0	0
T6	1789	0	0	0
T7	17825	55	0	0
T8	55026	498	0	0
T9	2730	51	0	0
T10	15374	0	0	0
T41	0	78	0	0
T84	0	35	0	0
T85	0	46	0	0
T114	0	52	0	0
T155	0	64	0	0
T157	0	92	0	0

reset_en_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23104563	1321	0	0
T57	0	144	0	0
T59	0	11	0	0
T63	0	14	0	0
T64	0	30	0	0
T87	343011	0	0	0
T100	162104	9	0	0
T101	0	9	0	0
T148	154977	0	0	0
T158	0	10	0	0
T159	0	5	0	0
T160	0	4	0	0
T161	0	8	0	0
T162	6534	0	0	0
T163	1579	0	0	0
T164	13906	0	0	0
T165	750	0	0	0
T166	60055	0	0	0
T167	2936	0	0	0
T168	14316	0	0	0

reset_en_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23104563	1072	0	0
T57	0	51	0	0
T59	0	11	0	0
T63	0	26	0	0
T87	343011	0	0	0
T100	162104	2	0	0
T101	0	13	0	0
T148	154977	0	0	0
T158	0	11	0	0
T159	0	4	0	0
T160	0	8	0	0
T161	0	3	0	0
T162	6534	0	0	0
T163	1579	0	0	0
T164	13906	0	0	0
T165	750	0	0	0
T166	60055	0	0	0
T167	2936	0	0	0
T168	14316	0	0	0
T169	0	7	0	0

wake_info_capture_dis_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23104563	1246	0	0
T57	0	79	0	0
T59	0	12	0	0
T63	0	18	0	0
T87	343011	0	0	0
T100	162104	2	0	0
T101	0	10	0	0
T148	154977	0	0	0
T158	0	13	0	0
T159	0	10	0	0
T160	0	12	0	0
T161	0	1	0	0
T162	6534	0	0	0
T163	1579	0	0	0
T164	13906	0	0	0
T165	750	0	0	0
T166	60055	0	0	0
T167	2936	0	0	0
T168	14316	0	0	0
T170	0	3	0	0

wakeup_en_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23104563	2070	0	0
T57	0	343	0	0
T59	0	3	0	0
T63	0	49	0	0
T87	343011	0	0	0
T100	162104	4	0	0
T101	0	10	0	0
T148	154977	0	0	0
T158	0	16	0	0
T159	0	13	0	0
T160	0	4	0	0
T161	0	10	0	0
T162	6534	0	0	0
T163	1579	0	0	0
T164	13906	0	0	0
T165	750	0	0	0
T166	60055	0	0	0
T167	2936	0	0	0
T168	14316	0	0	0
T169	0	2	0	0

wakeup_en_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23104563	1140	0	0
T57	0	68	0	0
T59	0	14	0	0
T63	0	10	0	0
T87	343011	0	0	0
T100	162104	6	0	0
T101	0	9	0	0
T148	154977	0	0	0
T158	0	7	0	0
T159	0	9	0	0
T160	0	5	0	0
T161	0	2	0	0
T162	6534	0	0	0
T163	1579	0	0	0
T164	13906	0	0	0
T165	750	0	0	0
T166	60055	0	0	0
T167	2936	0	0	0
T168	14316	0	0	0
T171	0	4	0	0