Unified Coverage Report :: Module :: pwrmgr_sec_cm_checker_assert

Module : pwrmgr_sec_cm_checker_assert

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_sec_cm_checker_assert	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.pwrmgr_sec_cm_checker_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : pwrmgr_sec_cm_checker_assert

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	39	1	1	100.00
ALWAYS	40	1	1	100.00
ALWAYS	41	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv' or '../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
39	1	1
40	1	1
41	1	1

---

Cond Coverage for Module : pwrmgr_sec_cm_checker_assert

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       39
 EXPRESSION (((!rst_ni)) || disable_sva)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       40
 EXPRESSION (((!rst_esc_ni)) || disable_sva)
             -------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       41
 EXPRESSION (((!rst_slow_ni)) || disable_sva)
             --------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

---

Assert Coverage for Module : pwrmgr_sec_cm_checker_assert

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	10	10	100.00	10	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	10	10	100.00	10	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
RomAllowActiveState_A	22531825	52526	0	0
RomAllowCheckGoodState_A	22531825	52578	0	0
RomBlockActiveState_A	22531825	27065	0	0
RomBlockCheckGoodState_A	22531825	404895	0	0
RomIntgChkDisFalse_A	22531825	21896705	0	0
RomIntgChkDisTrue_A	22531825	164021	0	0
RstreqChkEsctimeout_A	22531825	3589	0	0
RstreqChkFsmterm_A	22531825	140	0	0
RstreqChkGlbesc_A	22531825	3589	0	0
RstreqChkMainpd_A	22531825	891164	0	0

RomAllowActiveState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22531825	52526	0	0
T1	1561	8	0	0
T2	5202	5	0	0
T3	1224	6	0	0
T4	2529	3	0	0
T5	1550	7	0	0
T6	1789	3	0	0
T7	17825	21	0	0
T8	55026	183	0	0
T9	2730	13	0	0
T10	15374	2	0	0

RomAllowCheckGoodState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22531825	52578	0	0
T1	1561	8	0	0
T2	5202	5	0	0
T3	1224	6	0	0
T4	2529	3	0	0
T5	1550	7	0	0
T6	1789	3	0	0
T7	17825	21	0	0
T8	55026	183	0	0
T9	2730	13	0	0
T10	15374	2	0	0

RomBlockActiveState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22531825	27065	0	0
T1	1561	80	0	0
T2	5202	0	0	0
T3	1224	0	0	0
T4	2529	0	0	0
T5	1550	0	0	0
T6	1789	0	0	0
T7	17825	0	0	0
T8	55026	0	0	0
T9	2730	0	0	0
T10	15374	0	0	0
T25	0	302	0	0
T26	0	4	0	0
T50	0	7	0	0
T156	0	150	0	0
T172	0	1193	0	0
T173	0	80	0	0
T174	0	705	0	0
T175	0	1	0	0
T176	0	910	0	0

RomBlockCheckGoodState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22531825	404895	0	0
T1	1561	4	0	0
T2	5202	0	0	0
T3	1224	0	0	0
T4	2529	0	0	0
T5	1550	0	0	0
T6	1789	0	0	0
T7	17825	0	0	0
T8	55026	941	0	0
T9	2730	0	0	0
T10	15374	0	0	0
T13	0	528	0	0
T14	0	917	0	0
T24	0	4172	0	0
T25	0	65	0	0
T26	0	1353	0	0
T38	0	391	0	0
T50	0	1298	0	0
T84	0	457	0	0

RomIntgChkDisFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22531825	21896705	0	0
T1	1561	1178	0	0
T2	5202	5105	0	0
T3	1224	755	0	0
T4	2529	2456	0	0
T5	1550	1491	0	0
T6	1789	1709	0	0
T7	17825	17750	0	0
T8	55026	53505	0	0
T9	2730	2588	0	0
T10	15374	15303	0	0

RomIntgChkDisTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22531825	164021	0	0
T1	1561	281	0	0
T2	5202	0	0	0
T3	1224	0	0	0
T4	2529	0	0	0
T5	1550	0	0	0
T6	1789	0	0	0
T7	17825	0	0	0
T8	55026	0	0	0
T9	2730	0	0	0
T10	15374	0	0	0
T24	0	1903	0	0
T25	0	548	0	0
T156	0	902	0	0
T172	0	1169	0	0
T173	0	560	0	0
T174	0	306	0	0
T176	0	514	0	0
T177	0	30290	0	0
T178	0	744	0	0

RstreqChkEsctimeout_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22531825	3589	0	0
T1	1561	3	0	0
T2	5202	0	0	0
T3	1224	0	0	0
T4	2529	0	0	0
T5	1550	0	0	0
T6	1789	0	0	0
T7	17825	0	0	0
T8	55026	12	0	0
T9	2730	7	0	0
T10	15374	1	0	0
T11	0	1	0	0
T12	0	1	0	0
T13	0	33	0	0
T20	0	7	0	0
T43	0	2	0	0
T44	0	2	0	0

RstreqChkFsmterm_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22531825	140	0	0
T17	44174	40	0	0
T18	0	40	0	0
T19	0	20	0	0
T27	0	20	0	0
T28	0	20	0	0
T29	2216	0	0	0
T30	4848	0	0	0
T31	786	0	0	0
T32	5512	0	0	0
T33	17252	0	0	0
T34	3144	0	0	0
T35	3673	0	0	0
T36	13531	0	0	0
T37	2776	0	0	0

RstreqChkGlbesc_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22531825	3589	0	0
T1	1561	3	0	0
T2	5202	0	0	0
T3	1224	0	0	0
T4	2529	0	0	0
T5	1550	0	0	0
T6	1789	0	0	0
T7	17825	0	0	0
T8	55026	12	0	0
T9	2730	7	0	0
T10	15374	1	0	0
T11	0	1	0	0
T12	0	1	0	0
T13	0	33	0	0
T20	0	7	0	0
T43	0	2	0	0
T44	0	2	0	0

RstreqChkMainpd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22531825	891164	0	0
T1	1561	114	0	0
T2	5202	0	0	0
T3	1224	23	0	0
T4	2529	0	0	0
T5	1550	0	0	0
T6	1789	0	0	0
T7	17825	0	0	0
T8	55026	1727	0	0
T9	2730	177	0	0
T10	15374	0	0	0
T13	0	5364	0	0
T14	0	4572	0	0
T20	0	225	0	0
T24	0	3150	0	0
T26	0	1605	0	0
T38	0	885	0	0