Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	467790	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

174540

1

T1

79

T2

32

T3

25

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	330090	1			T1	114		T2	38		T3	32
values[0x0]	156093	1			T1	48		T2	7		T3	15
values[0x1]	156147	1			T1	41		T2	9		T3	18

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	370252	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

272078

1

T1

104

T2

33

T3

32

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	2250	1			T6	2		T13	5		T49	2
valid_sources[0x01]	1915	1			T13	11		T14	18		T40	36
valid_sources[0x02]	2253	1			T4	2		T13	8		T14	29
valid_sources[0x03]	2414	1			T13	11		T14	18		T37	1
valid_sources[0x04]	2408	1			T13	6		T49	2		T14	25
valid_sources[0x05]	3721	1			T4	1		T13	2		T49	2
valid_sources[0x06]	3271	1			T13	6		T14	22		T21	75
valid_sources[0x07]	2167	1			T4	1		T13	6		T14	38
valid_sources[0x08]	2881	1			T6	5		T13	5		T14	22
valid_sources[0x09]	2046	1			T6	3		T13	5		T49	2
valid_sources[0x0a]	2387	1			T9	1		T13	6		T14	31
valid_sources[0x0b]	2078	1			T13	9		T14	17		T40	38
valid_sources[0x0c]	2209	1			T3	1		T13	6		T14	22
valid_sources[0x0d]	2160	1			T6	3		T13	12		T14	24
valid_sources[0x0e]	3576	1			T13	5		T14	28		T20	1583
valid_sources[0x0f]	2105	1			T9	1		T13	6		T14	30
valid_sources[0x10]	2262	1			T13	2		T49	1		T14	33
valid_sources[0x11]	2070	1			T13	9		T14	31		T35	3
valid_sources[0x12]	1906	1			T4	2		T6	1		T13	7
valid_sources[0x13]	4002	1			T13	2		T14	37		T40	35
valid_sources[0x14]	2058	1			T13	5		T14	30		T37	1
valid_sources[0x15]	2162	1			T13	9		T14	33		T35	9
valid_sources[0x16]	3978	1			T6	3		T13	5		T49	1
valid_sources[0x17]	2050	1			T13	5		T14	29		T37	1
valid_sources[0x18]	1945	1			T2	54		T9	1		T13	2
valid_sources[0x19]	4640	1			T13	2		T14	34		T40	49
valid_sources[0x1a]	2268	1			T9	1		T13	8		T14	30
valid_sources[0x1b]	3120	1			T39	3		T13	11		T49	1
valid_sources[0x1c]	2067	1			T13	9		T14	26		T35	5
valid_sources[0x1d]	2403	1			T13	5		T49	1		T14	17
valid_sources[0x1e]	1928	1			T39	7		T13	4		T14	23
valid_sources[0x1f]	2500	1			T13	8		T49	1		T14	22
valid_sources[0x20]	2138	1			T13	6		T14	24		T40	54
valid_sources[0x21]	2044	1			T3	1		T4	5		T6	1
valid_sources[0x22]	2255	1			T3	5		T13	9		T14	33
valid_sources[0x23]	1943	1			T13	4		T14	25		T40	17
valid_sources[0x24]	2095	1			T6	4		T13	5		T49	1
valid_sources[0x25]	2658	1			T13	8		T14	23		T40	47
valid_sources[0x26]	2329	1			T13	3		T14	32		T20	39
valid_sources[0x27]	2934	1			T6	2		T13	7		T49	1
valid_sources[0x28]	4097	1			T13	3		T14	27		T20	15
valid_sources[0x29]	3044	1			T13	2		T14	27		T20	955
valid_sources[0x2a]	2948	1			T4	2		T13	7		T49	2
valid_sources[0x2b]	2042	1			T13	8		T49	2		T14	31
valid_sources[0x2c]	1887	1			T13	5		T14	21		T37	1
valid_sources[0x2d]	2527	1			T13	4		T14	28		T20	569
valid_sources[0x2e]	2380	1			T6	1		T13	10		T49	2
valid_sources[0x2f]	2312	1			T13	6		T49	1		T14	32
valid_sources[0x30]	2434	1			T13	5		T14	34		T35	12
valid_sources[0x31]	3776	1			T6	3		T9	1		T13	11
valid_sources[0x32]	2818	1			T13	5		T49	5		T14	18
valid_sources[0x33]	2391	1			T13	7		T49	2		T14	25
valid_sources[0x34]	2037	1			T13	4		T14	37		T20	15
valid_sources[0x35]	4325	1			T13	7		T49	1		T14	26
valid_sources[0x36]	2069	1			T6	2		T13	6		T14	16
valid_sources[0x37]	1999	1			T6	1		T13	5		T14	31
valid_sources[0x38]	4136	1			T3	1		T4	1		T6	1
valid_sources[0x39]	2064	1			T13	7		T49	1		T14	19
valid_sources[0x3a]	2069	1			T3	1		T4	1		T13	12
valid_sources[0x3b]	2021	1			T6	3		T13	10		T14	29
valid_sources[0x3c]	2265	1			T13	6		T49	1		T14	40
valid_sources[0x3d]	2240	1			T3	1		T39	10		T13	1
valid_sources[0x3e]	5187	1			T3	2		T6	1		T7	25
valid_sources[0x3f]	1984	1			T13	4		T49	1		T14	52
valid_sources[0x40]	4478	1			T6	4		T13	4		T14	28
valid_sources[0x41]	1924	1			T6	2		T13	12		T49	1
valid_sources[0x42]	2447	1			T13	11		T14	25		T35	4
valid_sources[0x43]	2027	1			T13	5		T49	1		T14	36
valid_sources[0x44]	2108	1			T3	3		T4	1		T13	10
valid_sources[0x45]	3118	1			T3	6		T13	3		T14	18
valid_sources[0x46]	3040	1			T4	1		T9	1		T13	1
valid_sources[0x47]	1971	1			T13	4		T14	30		T11	1
valid_sources[0x48]	2111	1			T6	4		T13	4		T14	20
valid_sources[0x49]	3880	1			T13	5		T49	3		T14	28
valid_sources[0x4a]	2053	1			T13	5		T14	28		T35	59
valid_sources[0x4b]	2152	1			T13	5		T14	23		T37	1
valid_sources[0x4c]	2674	1			T3	1		T13	7		T14	29
valid_sources[0x4d]	1918	1			T13	8		T14	36		T40	30
valid_sources[0x4e]	2098	1			T13	10		T14	17		T40	32
valid_sources[0x4f]	1878	1			T9	1		T13	7		T14	32
valid_sources[0x50]	2286	1			T6	1		T13	5		T14	32
valid_sources[0x51]	2024	1			T4	1		T13	8		T14	22
valid_sources[0x52]	2552	1			T13	3		T14	28		T20	241
valid_sources[0x53]	2827	1			T13	8		T14	22		T40	36
valid_sources[0x54]	2987	1			T9	1		T13	12		T14	21
valid_sources[0x55]	2133	1			T6	1		T14	24		T35	14
valid_sources[0x56]	2427	1			T13	11		T14	26		T20	14
valid_sources[0x57]	3229	1			T13	2		T14	13		T35	32
valid_sources[0x58]	2487	1			T5	2		T6	1		T13	4
valid_sources[0x59]	4692	1			T3	1		T13	4		T14	24
valid_sources[0x5a]	2033	1			T4	2		T13	5		T49	2
valid_sources[0x5b]	2128	1			T3	1		T4	2		T6	4
valid_sources[0x5c]	2056	1			T8	1		T13	5		T49	1
valid_sources[0x5d]	2008	1			T13	4		T49	1		T14	28
valid_sources[0x5e]	2635	1			T13	8		T49	2		T14	30
valid_sources[0x5f]	2073	1			T3	1		T13	4		T49	3
valid_sources[0x60]	2273	1			T6	1		T13	7		T14	32
valid_sources[0x61]	2007	1			T6	2		T39	24		T13	8
valid_sources[0x62]	1980	1			T6	4		T13	2		T14	25
valid_sources[0x63]	2345	1			T13	7		T14	20		T35	3
valid_sources[0x64]	2236	1			T13	5		T14	35		T40	33
valid_sources[0x65]	3248	1			T13	10		T14	16		T20	1017
valid_sources[0x66]	2058	1			T9	1		T13	6		T14	30
valid_sources[0x67]	1959	1			T13	15		T14	26		T40	33
valid_sources[0x68]	1928	1			T4	1		T5	4		T6	5
valid_sources[0x69]	2106	1			T39	5		T13	2		T14	30
valid_sources[0x6a]	2017	1			T4	1		T13	5		T49	1
valid_sources[0x6b]	2099	1			T3	2		T13	3		T14	25
valid_sources[0x6c]	2943	1			T4	1		T6	1		T13	6
valid_sources[0x6d]	2396	1			T13	8		T49	1		T14	25
valid_sources[0x6e]	3826	1			T13	11		T14	21		T20	16
valid_sources[0x6f]	2067	1			T3	3		T13	6		T14	35
valid_sources[0x70]	2032	1			T13	9		T14	25		T35	8
valid_sources[0x71]	1996	1			T3	3		T9	1		T13	4
valid_sources[0x72]	2089	1			T13	6		T14	31		T35	6
valid_sources[0x73]	2103	1			T6	3		T13	10		T14	19
valid_sources[0x74]	1985	1			T5	1		T13	6		T14	32
valid_sources[0x75]	1908	1			T13	15		T14	21		T40	47
valid_sources[0x76]	3943	1			T13	3		T14	16		T35	5
valid_sources[0x77]	2167	1			T6	3		T13	3		T49	2
valid_sources[0x78]	1988	1			T6	3		T13	11		T49	6
valid_sources[0x79]	2111	1			T6	2		T13	3		T14	26
valid_sources[0x7a]	2142	1			T9	1		T10	1		T13	3
valid_sources[0x7b]	1917	1			T6	1		T13	4		T49	1
valid_sources[0x7c]	3005	1			T6	2		T13	6		T49	2
valid_sources[0x7d]	2202	1			T13	8		T49	1		T14	22
valid_sources[0x7e]	2553	1			T6	1		T13	4		T14	27
valid_sources[0x7f]	2417	1			T13	3		T14	18		T37	1
valid_sources[0x80]	3061	1			T6	2		T13	9		T49	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

85286

1

T1

48

T2

27

T3

13

values[0x0]

all_enables

biggest_size

57882

1

T1

23

T2

3

T3

6

values[0x1]

all_enables

biggest_size

31372

1

T1

8

T2

2

T3

6