SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING |
100.00 | 100.00 | 1 | 100 | 1 | 1 | 64 | 64 |
NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_rom_ctrl_done_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_rom_ctrl_good_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_sw_rst_req_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 34891 | 1 | T35 | 398 | T22 | 297 | T153 | 298 | ||||
others[1] | 35127 | 1 | T35 | 422 | T22 | 310 | T23 | 1 | ||||
others[2] | 35147 | 1 | T35 | 384 | T22 | 292 | T23 | 1 | ||||
others[3] | 58322 | 1 | T35 | 650 | T22 | 507 | T23 | 2 | ||||
false | 18447 | 1 | T4 | 4 | T6 | 18 | T13 | 30 | ||||
true | 27988 | 1 | T1 | 1 | T2 | 5 | T3 | 13 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 35101 | 1 | T35 | 392 | T22 | 301 | T153 | 292 | ||||
others[1] | 34819 | 1 | T35 | 376 | T22 | 305 | T153 | 293 | ||||
others[2] | 35063 | 1 | T35 | 406 | T22 | 303 | T148 | 1 | ||||
others[3] | 58660 | 1 | T35 | 696 | T22 | 507 | T23 | 1 | ||||
false | 11817 | 1 | T4 | 5 | T6 | 9 | T13 | 15 | ||||
true | 21414 | 1 | T1 | 1 | T2 | 5 | T3 | 13 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 617 | 1 | T14 | 4 | T36 | 2 | T20 | 10 | ||||
others[1] | 637 | 1 | T3 | 1 | T13 | 2 | T14 | 1 | ||||
others[2] | 651 | 1 | T13 | 1 | T14 | 1 | T36 | 2 | ||||
others[3] | 1014 | 1 | T3 | 2 | T14 | 6 | T36 | 4 | ||||
false | 12397 | 1 | T1 | 1 | T2 | 5 | T3 | 21 | ||||
true | 3566 | 1 | T3 | 5 | T4 | 4 | T13 | 12 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |