Unified Coverage Report :: Module :: pwrmgr_rstmgr_sva_if

Module : pwrmgr_rstmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_rstmgr_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.pwrmgr_rstmgr_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : pwrmgr_rstmgr_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	33	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv' or '../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
33	1	1

---

Cond Coverage for Module : pwrmgr_rstmgr_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       33
 EXPRESSION (((!rst_slow_ni)) || disable_sva)
             --------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T6
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T13,T14

---

Assert Coverage for Module : pwrmgr_rstmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_assertions_per_power_domains[0].LcHandshakeOff_A	22347900	6107	0	0
gen_assertions_per_power_domains[0].LcHandshakeOn_A	22347900	251925	0	0
gen_assertions_per_power_domains[0].SysHandshakeOff_A	22347900	9247853	0	0
gen_assertions_per_power_domains[0].SysHandshakeOn_A	22347900	251900	0	0
gen_assertions_per_power_domains[1].LcHandshakeOff_A	22347900	6107	0	0
gen_assertions_per_power_domains[1].LcHandshakeOn_A	22347900	251925	0	0
gen_assertions_per_power_domains[1].SysHandshakeOff_A	22347900	9247853	0	0
gen_assertions_per_power_domains[1].SysHandshakeOn_A	22347900	251900	0	0

gen_assertions_per_power_domains[0].LcHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22347900	6107	0	0
T2	2956	4	0	0
T3	3182	0	0	0
T4	1597	0	0	0
T5	1068	0	0	0
T6	8202	4	0	0
T7	1117	1	0	0
T8	2094	0	0	0
T9	1136	1	0	0
T10	1417	0	0	0
T13	0	6	0	0
T14	0	39	0	0
T20	0	122	0	0
T35	0	19	0	0
T36	0	7	0	0
T39	2213	1	0	0

gen_assertions_per_power_domains[0].LcHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22347900	251925	0	0
T2	2956	709	0	0
T3	3182	0	0	0
T4	1597	0	0	0
T5	1068	0	0	0
T6	8202	150	0	0
T7	1117	14	0	0
T8	2094	0	0	0
T9	1136	13	0	0
T10	1417	0	0	0
T13	0	602	0	0
T14	0	763	0	0
T20	0	9213	0	0
T35	0	1534	0	0
T36	0	84	0	0
T39	2213	12	0	0

gen_assertions_per_power_domains[0].SysHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22347900	9247853	0	0
T1	3277	2184	0	0
T2	2956	1159	0	0
T3	3182	0	0	0
T4	1597	0	0	0
T5	1068	0	0	0
T6	8202	4403	0	0
T7	1117	838	0	0
T8	2094	0	0	0
T9	1136	928	0	0
T10	1417	0	0	0
T13	0	31902	0	0
T14	0	64524	0	0
T35	0	25745	0	0
T39	0	1358	0	0
T49	0	857	0	0

gen_assertions_per_power_domains[0].SysHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22347900	251900	0	0
T2	2956	709	0	0
T3	3182	0	0	0
T4	1597	0	0	0
T5	1068	0	0	0
T6	8202	150	0	0
T7	1117	14	0	0
T8	2094	0	0	0
T9	1136	13	0	0
T10	1417	0	0	0
T13	0	602	0	0
T14	0	763	0	0
T20	0	9209	0	0
T35	0	1534	0	0
T36	0	84	0	0
T39	2213	12	0	0

gen_assertions_per_power_domains[1].LcHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22347900	6107	0	0
T2	2956	4	0	0
T3	3182	0	0	0
T4	1597	0	0	0
T5	1068	0	0	0
T6	8202	4	0	0
T7	1117	1	0	0
T8	2094	0	0	0
T9	1136	1	0	0
T10	1417	0	0	0
T13	0	6	0	0
T14	0	39	0	0
T20	0	122	0	0
T35	0	19	0	0
T36	0	7	0	0
T39	2213	1	0	0

gen_assertions_per_power_domains[1].LcHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22347900	251925	0	0
T2	2956	709	0	0
T3	3182	0	0	0
T4	1597	0	0	0
T5	1068	0	0	0
T6	8202	150	0	0
T7	1117	14	0	0
T8	2094	0	0	0
T9	1136	13	0	0
T10	1417	0	0	0
T13	0	602	0	0
T14	0	763	0	0
T20	0	9213	0	0
T35	0	1534	0	0
T36	0	84	0	0
T39	2213	12	0	0

gen_assertions_per_power_domains[1].SysHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22347900	9247853	0	0
T1	3277	2184	0	0
T2	2956	1159	0	0
T3	3182	0	0	0
T4	1597	0	0	0
T5	1068	0	0	0
T6	8202	4403	0	0
T7	1117	838	0	0
T8	2094	0	0	0
T9	1136	928	0	0
T10	1417	0	0	0
T13	0	31902	0	0
T14	0	64524	0	0
T35	0	25745	0	0
T39	0	1358	0	0
T49	0	857	0	0

gen_assertions_per_power_domains[1].SysHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22347900	251900	0	0
T2	2956	709	0	0
T3	3182	0	0	0
T4	1597	0	0	0
T5	1068	0	0	0
T6	8202	150	0	0
T7	1117	14	0	0
T8	2094	0	0	0
T9	1136	13	0	0
T10	1417	0	0	0
T13	0	602	0	0
T14	0	763	0	0
T20	0	9209	0	0
T35	0	1534	0	0
T36	0	84	0	0
T39	2213	12	0	0