Unified Coverage Report :: Module :: pwrmgr_csr_assert_fpv

Module : pwrmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_pwrmgr_csr_assert_0/pwrmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.pwrmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : pwrmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	22894518	12770	0	0
intr_enable_rd_A	22894518	43134	0	0
reset_en_rd_A	22894518	1575	0	0
reset_en_regwen_rd_A	22894518	1223	0	0
wake_info_capture_dis_rd_A	22894518	1270	0	0
wakeup_en_rd_A	22894518	2672	0	0
wakeup_en_regwen_rd_A	22894518	1294	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22894518	12770	0	0
T11	2409	0	0	0
T14	122845	10	0	0
T15	962	0	0	0
T20	636127	23	0	0
T21	126930	3	0	0
T35	55410	0	0	0
T36	29581	0	0	0
T37	3000	0	0	0
T38	2754	0	0	0
T40	508215	33	0	0
T68	0	6	0	0
T76	0	109	0	0
T127	0	3	0	0
T128	0	19	0	0
T129	0	8	0	0
T130	0	9	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22894518	43134	0	0
T7	1117	6	0	0
T8	2094	0	0	0
T9	1136	0	0	0
T10	1417	0	0	0
T13	81879	0	0	0
T14	122845	0	0	0
T15	962	0	0	0
T22	0	109	0	0
T35	55410	0	0	0
T39	2213	0	0	0
T49	7172	0	0	0
T54	0	40	0	0
T75	0	51	0	0
T91	0	25	0	0
T124	0	46	0	0
T125	0	257	0	0
T131	0	7	0	0
T132	0	20	0	0
T133	0	7	0	0

reset_en_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22894518	1575	0	0
T45	0	1	0	0
T52	0	8	0	0
T72	0	7	0	0
T93	2147	0	0	0
T129	492830	10	0	0
T130	272772	0	0	0
T134	0	3	0	0
T135	0	9	0	0
T136	0	8	0	0
T137	0	6	0	0
T138	0	10	0	0
T139	0	10	0	0
T140	1523	0	0	0
T141	1601	0	0	0
T142	5246	0	0	0
T143	3769	0	0	0
T144	1258	0	0	0
T145	4706	0	0	0
T146	38605	0	0	0

reset_en_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22894518	1223	0	0
T44	0	33	0	0
T45	0	23	0	0
T52	0	8	0	0
T72	0	13	0	0
T93	2147	0	0	0
T129	492830	5	0	0
T130	272772	0	0	0
T136	0	3	0	0
T137	0	9	0	0
T138	0	14	0	0
T139	0	7	0	0
T140	1523	0	0	0
T141	1601	0	0	0
T142	5246	0	0	0
T143	3769	0	0	0
T144	1258	0	0	0
T145	4706	0	0	0
T146	38605	0	0	0
T147	0	3	0	0

wake_info_capture_dis_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22894518	1270	0	0
T45	0	4	0	0
T52	0	3	0	0
T72	0	12	0	0
T93	2147	0	0	0
T129	492830	14	0	0
T130	272772	0	0	0
T134	0	1	0	0
T135	0	1	0	0
T136	0	1	0	0
T137	0	8	0	0
T138	0	7	0	0
T140	1523	0	0	0
T141	1601	0	0	0
T142	5246	0	0	0
T143	3769	0	0	0
T144	1258	0	0	0
T145	4706	0	0	0
T146	38605	0	0	0
T147	0	2	0	0

wakeup_en_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22894518	2672	0	0
T45	0	4	0	0
T52	0	6	0	0
T72	0	11	0	0
T93	2147	0	0	0
T129	492830	17	0	0
T130	272772	0	0	0
T135	0	8	0	0
T136	0	14	0	0
T137	0	5	0	0
T138	0	12	0	0
T139	0	16	0	0
T140	1523	0	0	0
T141	1601	0	0	0
T142	5246	0	0	0
T143	3769	0	0	0
T144	1258	0	0	0
T145	4706	0	0	0
T146	38605	0	0	0
T147	0	2	0	0

wakeup_en_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22894518	1294	0	0
T45	0	1	0	0
T52	0	8	0	0
T72	0	5	0	0
T93	2147	0	0	0
T129	492830	14	0	0
T130	272772	0	0	0
T134	0	9	0	0
T135	0	7	0	0
T136	0	2	0	0
T137	0	3	0	0
T138	0	14	0	0
T140	1523	0	0	0
T141	1601	0	0	0
T142	5246	0	0	0
T143	3769	0	0	0
T144	1258	0	0	0
T145	4706	0	0	0
T146	38605	0	0	0
T147	0	3	0	0