Unified Coverage Report :: Module :: clkmgr_pwrmgr_sva_if

Module : clkmgr_pwrmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_pwrmgr_sva_if_0.1/clkmgr_pwrmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_pwrmgr_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_pwrmgr_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : clkmgr_pwrmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
IoStatusFall_A	22347900	49632	0	0
IoStatusRise_A	22347900	55243	0	0
MainStatusFall_A	22347900	49632	0	0
MainStatusRise_A	22347900	55243	0	0
UsbStatusFall_A	22347900	34103	0	0
UsbStatusRise_A	22347900	38384	0	0

IoStatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22347900	49632	0	0
T1	3277	8	0	0
T2	2956	4	0	0
T3	3182	18	0	0
T4	1597	5	0	0
T5	1068	1	0	0
T6	8202	14	0	0
T7	1117	2	0	0
T8	2094	0	0	0
T9	1136	2	0	0
T10	1417	1	0	0
T39	0	2	0	0

IoStatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22347900	55243	0	0
T1	3277	9	0	0
T2	2956	5	0	0
T3	3182	20	0	0
T4	1597	6	0	0
T5	1068	2	0	0
T6	8202	15	0	0
T7	1117	3	0	0
T8	2094	5	0	0
T9	1136	3	0	0
T10	1417	3	0	0

MainStatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22347900	49632	0	0
T1	3277	8	0	0
T2	2956	4	0	0
T3	3182	18	0	0
T4	1597	5	0	0
T5	1068	1	0	0
T6	8202	14	0	0
T7	1117	2	0	0
T8	2094	0	0	0
T9	1136	2	0	0
T10	1417	1	0	0
T39	0	2	0	0

MainStatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22347900	55243	0	0
T1	3277	9	0	0
T2	2956	5	0	0
T3	3182	20	0	0
T4	1597	6	0	0
T5	1068	2	0	0
T6	8202	15	0	0
T7	1117	3	0	0
T8	2094	5	0	0
T9	1136	3	0	0
T10	1417	3	0	0

UsbStatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22347900	34103	0	0
T1	3277	5	0	0
T2	2956	4	0	0
T3	3182	18	0	0
T4	1597	5	0	0
T5	1068	1	0	0
T6	8202	5	0	0
T7	1117	2	0	0
T8	2094	0	0	0
T9	1136	2	0	0
T10	1417	1	0	0
T39	0	2	0	0

UsbStatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22347900	38384	0	0
T1	3277	6	0	0
T2	2956	5	0	0
T3	3182	20	0	0
T4	1597	6	0	0
T5	1068	2	0	0
T6	8202	5	0	0
T7	1117	3	0	0
T8	2094	5	0	0
T9	1136	3	0	0
T10	1417	3	0	0