Unified Coverage Report :: Module :: pwrmgr_sec_cm_checker_assert

Module : pwrmgr_sec_cm_checker_assert

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_sec_cm_checker_assert	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.pwrmgr_sec_cm_checker_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : pwrmgr_sec_cm_checker_assert

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	39	1	1	100.00
ALWAYS	40	1	1	100.00
ALWAYS	41	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv' or '../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
39	1	1
40	1	1
41	1	1

---

Cond Coverage for Module : pwrmgr_sec_cm_checker_assert

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       39
 EXPRESSION (((!rst_ni)) || disable_sva)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       40
 EXPRESSION (((!rst_esc_ni)) || disable_sva)
             -------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       41
 EXPRESSION (((!rst_slow_ni)) || disable_sva)
             --------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

---

Assert Coverage for Module : pwrmgr_sec_cm_checker_assert

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	10	10	100.00	10	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	10	10	100.00	10	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
RomAllowActiveState_A	22347900	54834	0	0
RomAllowCheckGoodState_A	22347900	54884	0	0
RomBlockActiveState_A	22347900	26265	0	0
RomBlockCheckGoodState_A	22347900	401608	0	0
RomIntgChkDisFalse_A	22347900	21762612	0	0
RomIntgChkDisTrue_A	22347900	96366	0	0
RstreqChkEsctimeout_A	22347900	3849	0	0
RstreqChkFsmterm_A	22347900	160	0	0
RstreqChkGlbesc_A	22347900	3850	0	0
RstreqChkMainpd_A	22347900	896112	0	0

RomAllowActiveState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22347900	54834	0	0
T1	3277	9	0	0
T2	2956	5	0	0
T3	3182	13	0	0
T4	1597	6	0	0
T5	1068	2	0	0
T6	8202	15	0	0
T7	1117	3	0	0
T8	2094	5	0	0
T9	1136	3	0	0
T10	1417	3	0	0

RomAllowCheckGoodState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22347900	54884	0	0
T1	3277	9	0	0
T2	2956	5	0	0
T3	3182	14	0	0
T4	1597	6	0	0
T5	1068	2	0	0
T6	8202	15	0	0
T7	1117	3	0	0
T8	2094	5	0	0
T9	1136	3	0	0
T10	1417	3	0	0

RomBlockActiveState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22347900	26265	0	0
T4	1597	244	0	0
T5	1068	0	0	0
T6	8202	0	0	0
T7	1117	0	0	0
T8	2094	0	0	0
T9	1136	0	0	0
T10	1417	0	0	0
T13	81879	0	0	0
T22	0	3	0	0
T23	0	760	0	0
T39	2213	0	0	0
T49	7172	0	0	0
T131	0	188	0	0
T132	0	451	0	0
T148	0	799	0	0
T149	0	13	0	0
T150	0	525	0	0
T151	0	506	0	0
T152	0	479	0	0

RomBlockCheckGoodState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22347900	401608	0	0
T4	1597	31	0	0
T5	1068	0	0	0
T6	8202	205	0	0
T7	1117	0	0	0
T8	2094	0	0	0
T9	1136	0	0	0
T10	1417	0	0	0
T13	81879	345	0	0
T14	0	1376	0	0
T20	0	4525	0	0
T21	0	3607	0	0
T22	0	1302	0	0
T35	0	4161	0	0
T36	0	114	0	0
T39	2213	0	0	0
T40	0	2134	0	0
T49	7172	0	0	0

RomIntgChkDisFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22347900	21762612	0	0
T1	3277	3209	0	0
T2	2956	2626	0	0
T3	3182	2151	0	0
T4	1597	1422	0	0
T5	1068	985	0	0
T6	8202	8116	0	0
T7	1117	1024	0	0
T8	2094	1689	0	0
T9	1136	1053	0	0
T10	1417	1248	0	0

RomIntgChkDisTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22347900	96366	0	0
T4	1597	119	0	0
T5	1068	0	0	0
T6	8202	0	0	0
T7	1117	0	0	0
T8	2094	0	0	0
T9	1136	0	0	0
T10	1417	0	0	0
T13	81879	0	0	0
T22	0	197	0	0
T23	0	1406	0	0
T39	2213	0	0	0
T49	7172	0	0	0
T131	0	840	0	0
T132	0	231	0	0
T148	0	294	0	0
T149	0	1012	0	0
T150	0	53	0	0
T151	0	1161	0	0
T153	0	154	0	0

RstreqChkEsctimeout_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22347900	3849	0	0
T3	3182	3	0	0
T4	1597	4	0	0
T5	1068	0	0	0
T6	8202	0	0	0
T7	1117	0	0	0
T8	2094	0	0	0
T9	1136	0	0	0
T10	1417	1	0	0
T11	0	1	0	0
T13	81879	9	0	0
T14	0	20	0	0
T20	0	83	0	0
T36	0	24	0	0
T37	0	6	0	0
T38	0	3	0	0
T39	2213	0	0	0

RstreqChkFsmterm_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22347900	160	0	0
T17	24378	20	0	0
T18	0	20	0	0
T19	0	40	0	0
T24	0	40	0	0
T25	0	40	0	0
T26	1727	0	0	0
T27	15455	0	0	0
T28	49163	0	0	0
T29	1234	0	0	0
T30	15141	0	0	0
T31	2305	0	0	0
T32	4561	0	0	0
T33	6973	0	0	0
T34	49818	0	0	0

RstreqChkGlbesc_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22347900	3850	0	0
T3	3182	3	0	0
T4	1597	4	0	0
T5	1068	0	0	0
T6	8202	0	0	0
T7	1117	0	0	0
T8	2094	0	0	0
T9	1136	0	0	0
T10	1417	1	0	0
T11	0	1	0	0
T13	81879	9	0	0
T14	0	20	0	0
T20	0	83	0	0
T36	0	24	0	0
T37	0	6	0	0
T38	0	3	0	0
T39	2213	0	0	0

RstreqChkMainpd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22347900	896112	0	0
T3	3182	89	0	0
T4	1597	96	0	0
T5	1068	0	0	0
T6	8202	645	0	0
T7	1117	0	0	0
T8	2094	22	0	0
T9	1136	0	0	0
T10	1417	0	0	0
T13	81879	2258	0	0
T14	0	1950	0	0
T15	0	10	0	0
T20	0	30140	0	0
T35	0	5985	0	0
T36	0	385	0	0
T39	2213	0	0	0