Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	499045	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

193547

1

T2

195

T3

29

T4

34

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	363616	1			T1	1		T2	409		T3	37
values[0x0]	163667	1			T2	227		T3	9		T4	36
values[0x1]	165309	1			T2	225		T3	7		T4	40

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	395196	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

297396

1

T1

1

T2

339

T3

34

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	2850	1			T28	4		T40	1		T41	2
valid_sources[0x01]	2258	1			T3	2		T8	1		T28	1
valid_sources[0x02]	3617	1			T28	1		T40	4		T21	22
valid_sources[0x03]	2139	1			T28	9		T41	1		T26	1
valid_sources[0x04]	4469	1			T10	879		T28	8		T40	1
valid_sources[0x05]	2046	1			T2	1		T8	2		T16	1
valid_sources[0x06]	2437	1			T2	9		T16	7		T28	3
valid_sources[0x07]	2485	1			T8	1		T15	2		T16	1
valid_sources[0x08]	2158	1			T40	14		T41	6		T26	6
valid_sources[0x09]	2257	1			T2	12		T8	1		T15	1
valid_sources[0x0a]	2432	1			T8	2		T15	1		T40	9
valid_sources[0x0b]	1964	1			T2	3		T8	2		T28	3
valid_sources[0x0c]	3047	1			T15	1		T41	1		T26	5
valid_sources[0x0d]	3412	1			T15	2		T40	7		T41	2
valid_sources[0x0e]	3396	1			T16	3		T28	9		T40	4
valid_sources[0x0f]	2511	1			T3	1		T8	2		T41	6
valid_sources[0x10]	2272	1			T2	18		T3	1		T15	1
valid_sources[0x11]	2391	1			T4	137		T15	1		T16	8
valid_sources[0x12]	2684	1			T3	1		T28	3		T41	11
valid_sources[0x13]	1990	1			T8	2		T40	9		T41	4
valid_sources[0x14]	2611	1			T40	7		T41	8		T26	1
valid_sources[0x15]	1975	1			T41	8		T12	1		T26	2
valid_sources[0x16]	3847	1			T7	2		T8	1		T15	2
valid_sources[0x17]	3193	1			T1	1		T28	1		T41	3
valid_sources[0x18]	2823	1			T16	3		T28	13		T40	3
valid_sources[0x19]	3157	1			T15	1		T16	1		T28	1
valid_sources[0x1a]	2237	1			T15	3		T28	2		T41	2
valid_sources[0x1b]	2282	1			T8	1		T15	1		T40	8
valid_sources[0x1c]	2026	1			T15	2		T16	1		T13	10
valid_sources[0x1d]	2453	1			T3	1		T28	11		T41	7
valid_sources[0x1e]	2151	1			T15	2		T41	4		T26	3
valid_sources[0x1f]	2975	1			T8	1		T15	1		T21	5
valid_sources[0x20]	2129	1			T2	16		T21	38		T41	4
valid_sources[0x21]	2514	1			T8	2		T28	2		T40	1
valid_sources[0x22]	2134	1			T8	1		T28	1		T40	2
valid_sources[0x23]	2185	1			T16	2		T28	5		T40	1
valid_sources[0x24]	2231	1			T2	27		T7	3		T8	2
valid_sources[0x25]	2140	1			T3	2		T40	5		T41	5
valid_sources[0x26]	4266	1			T40	3		T41	5		T26	2
valid_sources[0x27]	2227	1			T21	21		T41	3		T26	3
valid_sources[0x28]	2076	1			T8	2		T16	4		T40	4
valid_sources[0x29]	2145	1			T2	6		T3	1		T7	5
valid_sources[0x2a]	2402	1			T2	15		T28	1		T40	2
valid_sources[0x2b]	2292	1			T2	17		T8	2		T28	22
valid_sources[0x2c]	2467	1			T7	2		T8	1		T28	1
valid_sources[0x2d]	2050	1			T15	6		T28	1		T40	2
valid_sources[0x2e]	4439	1			T28	1		T41	7		T26	3
valid_sources[0x2f]	2521	1			T2	23		T16	3		T40	4
valid_sources[0x30]	2988	1			T3	1		T16	1		T28	1
valid_sources[0x31]	2954	1			T3	1		T8	1		T15	3
valid_sources[0x32]	2583	1			T8	1		T15	1		T28	3
valid_sources[0x33]	2365	1			T8	1		T28	3		T41	5
valid_sources[0x34]	2598	1			T2	5		T15	2		T16	7
valid_sources[0x35]	4412	1			T5	1		T28	4		T41	4
valid_sources[0x36]	2732	1			T40	14		T41	2		T26	4
valid_sources[0x37]	1961	1			T2	10		T15	1		T41	3
valid_sources[0x38]	3027	1			T3	1		T16	1		T28	4
valid_sources[0x39]	2091	1			T8	1		T15	1		T40	1
valid_sources[0x3a]	4024	1			T2	18		T40	2		T41	2
valid_sources[0x3b]	2649	1			T28	10		T40	14		T21	1
valid_sources[0x3c]	4658	1			T40	3		T41	1		T26	6
valid_sources[0x3d]	2232	1			T2	2		T8	1		T16	2
valid_sources[0x3e]	2112	1			T2	1		T8	1		T40	5
valid_sources[0x3f]	2625	1			T2	8		T28	1		T40	16
valid_sources[0x40]	2183	1			T2	2		T8	1		T15	2
valid_sources[0x41]	2647	1			T15	1		T28	2		T40	2
valid_sources[0x42]	2448	1			T2	7		T8	3		T15	2
valid_sources[0x43]	2250	1			T3	1		T28	2		T40	2
valid_sources[0x44]	3141	1			T8	1		T28	3		T41	7
valid_sources[0x45]	2035	1			T28	4		T40	1		T41	4
valid_sources[0x46]	2771	1			T13	21		T40	3		T21	1
valid_sources[0x47]	2867	1			T3	1		T8	1		T28	2
valid_sources[0x48]	2399	1			T2	5		T3	1		T8	1
valid_sources[0x49]	3073	1			T8	1		T15	4		T41	7
valid_sources[0x4a]	2251	1			T9	107		T15	11		T16	2
valid_sources[0x4b]	2866	1			T2	1		T41	4		T26	3
valid_sources[0x4c]	3205	1			T15	1		T28	12		T40	4
valid_sources[0x4d]	1867	1			T2	12		T15	1		T28	17
valid_sources[0x4e]	3174	1			T15	2		T28	10		T40	4
valid_sources[0x4f]	2066	1			T28	5		T40	3		T21	21
valid_sources[0x50]	2340	1			T28	9		T40	4		T41	4
valid_sources[0x51]	2477	1			T3	1		T8	1		T28	12
valid_sources[0x52]	2348	1			T15	3		T28	17		T41	3
valid_sources[0x53]	6337	1			T8	2		T28	4		T41	5
valid_sources[0x54]	2699	1			T26	3		T25	9		T22	28
valid_sources[0x55]	1884	1			T2	27		T15	5		T28	1
valid_sources[0x56]	2509	1			T3	1		T7	3		T15	3
valid_sources[0x57]	3720	1			T28	9		T40	8		T21	9
valid_sources[0x58]	2107	1			T40	5		T41	5		T26	2
valid_sources[0x59]	2347	1			T16	1		T28	24		T40	15
valid_sources[0x5a]	2160	1			T3	1		T15	1		T16	3
valid_sources[0x5b]	2123	1			T2	27		T15	1		T16	2
valid_sources[0x5c]	3058	1			T21	4		T41	6		T26	3
valid_sources[0x5d]	2000	1			T2	2		T15	2		T28	1
valid_sources[0x5e]	1983	1			T2	14		T8	2		T28	2
valid_sources[0x5f]	3032	1			T2	3		T3	1		T28	5
valid_sources[0x60]	2547	1			T3	1		T28	1		T41	2
valid_sources[0x61]	2800	1			T8	1		T40	3		T41	2
valid_sources[0x62]	2052	1			T15	1		T41	4		T26	4
valid_sources[0x63]	2130	1			T21	35		T41	2		T26	2
valid_sources[0x64]	2281	1			T8	2		T41	2		T26	7
valid_sources[0x65]	2054	1			T40	1		T41	5		T26	3
valid_sources[0x66]	2757	1			T15	2		T40	9		T41	4
valid_sources[0x67]	3305	1			T3	1		T15	1		T40	2
valid_sources[0x68]	2317	1			T28	13		T41	3		T26	1
valid_sources[0x69]	2268	1			T40	5		T41	6		T26	5
valid_sources[0x6a]	2578	1			T8	1		T28	5		T41	7
valid_sources[0x6b]	2365	1			T8	1		T16	2		T28	5
valid_sources[0x6c]	2195	1			T2	1		T7	1		T8	1
valid_sources[0x6d]	2875	1			T3	1		T8	1		T16	1
valid_sources[0x6e]	2122	1			T15	1		T28	6		T40	2
valid_sources[0x6f]	2868	1			T8	2		T28	4		T41	6
valid_sources[0x70]	4425	1			T40	2		T41	6		T26	2
valid_sources[0x71]	2680	1			T8	2		T28	22		T40	2
valid_sources[0x72]	2947	1			T8	1		T28	7		T40	5
valid_sources[0x73]	2195	1			T15	2		T41	4		T26	2
valid_sources[0x74]	2168	1			T40	2		T41	1		T26	2
valid_sources[0x75]	2700	1			T3	3		T16	2		T40	2
valid_sources[0x76]	2857	1			T40	2		T21	28		T41	6
valid_sources[0x77]	2329	1			T2	48		T8	1		T40	11
valid_sources[0x78]	2180	1			T40	2		T41	2		T26	6
valid_sources[0x79]	2384	1			T8	1		T15	1		T40	3
valid_sources[0x7a]	2363	1			T3	1		T8	7		T40	4
valid_sources[0x7b]	2411	1			T8	1		T15	1		T28	13
valid_sources[0x7c]	2137	1			T40	7		T41	3		T25	9
valid_sources[0x7d]	2205	1			T16	5		T28	1		T40	1
valid_sources[0x7e]	2064	1			T28	5		T41	2		T26	7
valid_sources[0x7f]	2501	1			T8	1		T40	3		T26	7
valid_sources[0x80]	2971	1			T15	3		T40	4		T41	3

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

98610

1

T2

71

T3

23

T4

11

values[0x0]

all_enables

biggest_size

61167

1

T2

82

T3

5

T4

16

values[0x1]

all_enables

biggest_size

33770

1

T2

42

T3

1

T4

7