SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING |
100.00 | 100.00 | 1 | 100 | 1 | 1 | 64 | 64 |
NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_rom_ctrl_done_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_rom_ctrl_good_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_sw_rst_req_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 35053 | 1 | T2 | 409 | T10 | 425 | T28 | 390 | ||||
others[1] | 34929 | 1 | T2 | 399 | T10 | 398 | T28 | 382 | ||||
others[2] | 34912 | 1 | T2 | 373 | T10 | 415 | T28 | 410 | ||||
others[3] | 58556 | 1 | T2 | 702 | T10 | 643 | T28 | 681 | ||||
false | 18561 | 1 | T2 | 50 | T10 | 50 | T28 | 50 | ||||
true | 28324 | 1 | T1 | 2 | T2 | 101 | T3 | 5 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 35292 | 1 | T2 | 393 | T10 | 402 | T28 | 421 | ||||
others[1] | 34593 | 1 | T2 | 386 | T10 | 403 | T28 | 386 | ||||
others[2] | 35197 | 1 | T2 | 398 | T10 | 398 | T28 | 428 | ||||
others[3] | 58467 | 1 | T2 | 701 | T10 | 665 | T28 | 636 | ||||
false | 11884 | 1 | T2 | 50 | T10 | 50 | T28 | 50 | ||||
true | 21703 | 1 | T1 | 2 | T2 | 101 | T3 | 5 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 641 | 1 | T43 | 1 | T162 | 3 | T25 | 1 | ||||
others[1] | 670 | 1 | T162 | 7 | T27 | 1 | T25 | 4 | ||||
others[2] | 638 | 1 | T9 | 1 | T42 | 3 | T43 | 1 | ||||
others[3] | 1099 | 1 | T14 | 1 | T42 | 1 | T43 | 1 | ||||
false | 12965 | 1 | T1 | 2 | T2 | 1 | T3 | 5 | ||||
true | 3783 | 1 | T9 | 7 | T13 | 7 | T14 | 2 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |