Unified Coverage Report :: Module :: pwrmgr_rstmgr_sva_if

Module : pwrmgr_rstmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_rstmgr_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.pwrmgr_rstmgr_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : pwrmgr_rstmgr_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	33	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv' or '../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
33	1	1

---

Cond Coverage for Module : pwrmgr_rstmgr_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       33
 EXPRESSION (((!rst_slow_ni)) || disable_sva)
             --------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T4
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T28,T41

---

Assert Coverage for Module : pwrmgr_rstmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_assertions_per_power_domains[0].LcHandshakeOff_A	24297326	6058	0	0
gen_assertions_per_power_domains[0].LcHandshakeOn_A	24297326	263891	0	0
gen_assertions_per_power_domains[0].SysHandshakeOff_A	24297326	10109824	0	0
gen_assertions_per_power_domains[0].SysHandshakeOn_A	24297326	263877	0	0
gen_assertions_per_power_domains[1].LcHandshakeOff_A	24297326	6058	0	0
gen_assertions_per_power_domains[1].LcHandshakeOn_A	24297326	263891	0	0
gen_assertions_per_power_domains[1].SysHandshakeOff_A	24297326	10109824	0	0
gen_assertions_per_power_domains[1].SysHandshakeOn_A	24297326	263877	0	0

gen_assertions_per_power_domains[0].LcHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24297326	6058	0	0
T2	59288	21	0	0
T3	2694	1	0	0
T4	9810	0	0	0
T5	560	0	0	0
T6	2712	0	0	0
T7	2111	0	0	0
T8	3926	0	0	0
T9	3895	0	0	0
T10	53794	23	0	0
T15	2441	0	0	0
T21	0	20	0	0
T25	0	26	0	0
T26	0	22	0	0
T28	0	20	0	0
T40	0	19	0	0
T41	0	29	0	0
T76	0	1	0	0

gen_assertions_per_power_domains[0].LcHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24297326	263891	0	0
T2	59288	1308	0	0
T3	2694	140	0	0
T4	9810	0	0	0
T5	560	0	0	0
T6	2712	0	0	0
T7	2111	0	0	0
T8	3926	0	0	0
T9	3895	0	0	0
T10	53794	1368	0	0
T15	2441	0	0	0
T21	0	930	0	0
T25	0	1790	0	0
T26	0	616	0	0
T28	0	456	0	0
T40	0	383	0	0
T41	0	1082	0	0
T76	0	12	0	0

gen_assertions_per_power_domains[0].SysHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24297326	10109824	0	0
T2	59288	28530	0	0
T3	2694	125	0	0
T4	9810	3288	0	0
T5	560	0	0	0
T6	2712	0	0	0
T7	2111	1053	0	0
T8	3926	874	0	0
T9	3895	0	0	0
T10	53794	28432	0	0
T15	2441	1110	0	0
T16	0	1283	0	0
T28	0	9599	0	0
T40	0	11210	0	0

gen_assertions_per_power_domains[0].SysHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24297326	263877	0	0
T2	59288	1308	0	0
T3	2694	140	0	0
T4	9810	0	0	0
T5	560	0	0	0
T6	2712	0	0	0
T7	2111	0	0	0
T8	3926	0	0	0
T9	3895	0	0	0
T10	53794	1368	0	0
T15	2441	0	0	0
T21	0	930	0	0
T25	0	1790	0	0
T26	0	614	0	0
T28	0	456	0	0
T40	0	383	0	0
T41	0	1082	0	0
T76	0	12	0	0

gen_assertions_per_power_domains[1].LcHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24297326	6058	0	0
T2	59288	21	0	0
T3	2694	1	0	0
T4	9810	0	0	0
T5	560	0	0	0
T6	2712	0	0	0
T7	2111	0	0	0
T8	3926	0	0	0
T9	3895	0	0	0
T10	53794	23	0	0
T15	2441	0	0	0
T21	0	20	0	0
T25	0	26	0	0
T26	0	22	0	0
T28	0	20	0	0
T40	0	19	0	0
T41	0	29	0	0
T76	0	1	0	0

gen_assertions_per_power_domains[1].LcHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24297326	263891	0	0
T2	59288	1308	0	0
T3	2694	140	0	0
T4	9810	0	0	0
T5	560	0	0	0
T6	2712	0	0	0
T7	2111	0	0	0
T8	3926	0	0	0
T9	3895	0	0	0
T10	53794	1368	0	0
T15	2441	0	0	0
T21	0	930	0	0
T25	0	1790	0	0
T26	0	616	0	0
T28	0	456	0	0
T40	0	383	0	0
T41	0	1082	0	0
T76	0	12	0	0

gen_assertions_per_power_domains[1].SysHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24297326	10109824	0	0
T2	59288	28530	0	0
T3	2694	125	0	0
T4	9810	3288	0	0
T5	560	0	0	0
T6	2712	0	0	0
T7	2111	1053	0	0
T8	3926	874	0	0
T9	3895	0	0	0
T10	53794	28432	0	0
T15	2441	1110	0	0
T16	0	1283	0	0
T28	0	9599	0	0
T40	0	11210	0	0

gen_assertions_per_power_domains[1].SysHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24297326	263877	0	0
T2	59288	1308	0	0
T3	2694	140	0	0
T4	9810	0	0	0
T5	560	0	0	0
T6	2712	0	0	0
T7	2111	0	0	0
T8	3926	0	0	0
T9	3895	0	0	0
T10	53794	1368	0	0
T15	2441	0	0	0
T21	0	930	0	0
T25	0	1790	0	0
T26	0	614	0	0
T28	0	456	0	0
T40	0	383	0	0
T41	0	1082	0	0
T76	0	12	0	0