Unified Coverage Report :: Module :: pwrmgr_csr_assert_fpv

Module : pwrmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_pwrmgr_csr_assert_0/pwrmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.pwrmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : pwrmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	24833143	14434	0	0
intr_enable_rd_A	24833143	34878	0	0
reset_en_rd_A	24833143	1336	0	0
reset_en_regwen_rd_A	24833143	1238	0	0
wake_info_capture_dis_rd_A	24833143	1249	0	0
wakeup_en_rd_A	24833143	1670	0	0
wakeup_en_regwen_rd_A	24833143	1025	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24833143	14434	0	0
T22	175179	24	0	0
T23	0	11	0	0
T24	0	4	0	0
T45	4383	0	0	0
T126	0	19	0	0
T127	0	4	0	0
T128	0	24	0	0
T129	0	8	0	0
T130	0	76	0	0
T131	0	6	0	0
T132	0	5	0	0
T133	2253	0	0	0
T134	15193	0	0	0
T135	1488	0	0	0
T136	4699	0	0	0
T137	1607	0	0	0
T138	1736	0	0	0
T139	5469	0	0	0
T140	4835	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24833143	34878	0	0
T2	59288	110	0	0
T3	2694	0	0	0
T4	9810	0	0	0
T5	560	0	0	0
T6	2712	0	0	0
T7	2111	19	0	0
T8	3926	0	0	0
T9	3895	38	0	0
T10	53794	0	0	0
T15	2441	44	0	0
T16	0	36	0	0
T28	0	174	0	0
T40	0	168	0	0
T41	0	111	0	0
T42	0	28	0	0
T76	0	3	0	0

reset_en_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24833143	1336	0	0
T49	0	36	0	0
T74	0	3	0	0
T75	0	3	0	0
T80	0	16	0	0
T82	0	1	0	0
T128	199331	4	0	0
T129	167198	0	0	0
T141	0	2	0	0
T142	0	21	0	0
T143	0	7	0	0
T144	0	13	0	0
T145	1565	0	0	0
T146	4215	0	0	0
T147	3608	0	0	0
T148	2170	0	0	0
T149	2062	0	0	0
T150	16837	0	0	0
T151	7070	0	0	0
T152	13803	0	0	0

reset_en_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24833143	1238	0	0
T74	0	2	0	0
T75	0	1	0	0
T80	0	3	0	0
T82	0	13	0	0
T128	199331	12	0	0
T129	167198	0	0	0
T141	0	3	0	0
T142	0	26	0	0
T143	0	21	0	0
T144	0	14	0	0
T145	1565	0	0	0
T146	4215	0	0	0
T147	3608	0	0	0
T148	2170	0	0	0
T149	2062	0	0	0
T150	16837	0	0	0
T151	7070	0	0	0
T152	13803	0	0	0
T153	0	4	0	0

wake_info_capture_dis_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24833143	1249	0	0
T49	0	31	0	0
T50	0	13	0	0
T61	0	488	0	0
T74	0	10	0	0
T75	0	4	0	0
T80	0	8	0	0
T128	199331	6	0	0
T129	167198	0	0	0
T142	0	27	0	0
T143	0	5	0	0
T144	0	8	0	0
T145	1565	0	0	0
T146	4215	0	0	0
T147	3608	0	0	0
T148	2170	0	0	0
T149	2062	0	0	0
T150	16837	0	0	0
T151	7070	0	0	0
T152	13803	0	0	0

wakeup_en_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24833143	1670	0	0
T49	0	40	0	0
T74	0	18	0	0
T75	0	5	0	0
T80	0	9	0	0
T82	0	21	0	0
T128	199331	17	0	0
T129	167198	0	0	0
T142	0	23	0	0
T143	0	11	0	0
T144	0	8	0	0
T145	1565	0	0	0
T146	4215	0	0	0
T147	3608	0	0	0
T148	2170	0	0	0
T149	2062	0	0	0
T150	16837	0	0	0
T151	7070	0	0	0
T152	13803	0	0	0
T153	0	9	0	0

wakeup_en_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24833143	1025	0	0
T49	0	9	0	0
T74	0	12	0	0
T75	0	7	0	0
T80	0	7	0	0
T82	0	2	0	0
T128	199331	2	0	0
T129	167198	3	0	0
T142	0	26	0	0
T143	0	9	0	0
T144	0	10	0	0
T145	1565	0	0	0
T146	4215	0	0	0
T147	3608	0	0	0
T148	2170	0	0	0
T149	2062	0	0	0
T150	16837	0	0	0
T151	7070	0	0	0
T152	13803	0	0	0