Unified Coverage Report :: Module :: clkmgr_pwrmgr_sva_if

Module : clkmgr_pwrmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_pwrmgr_sva_if_0.1/clkmgr_pwrmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_pwrmgr_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_pwrmgr_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : clkmgr_pwrmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
IoStatusFall_A	24297326	52011	0	0
IoStatusRise_A	24297326	57920	0	0
MainStatusFall_A	24297326	52011	0	0
MainStatusRise_A	24297326	57921	0	0
UsbStatusFall_A	24297326	35947	0	0
UsbStatusRise_A	24297326	40464	0	0

IoStatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24297326	52011	0	0
T1	834	1	0	0
T2	59288	85	0	0
T3	2694	4	0	0
T4	9810	10	0	0
T5	560	0	0	0
T6	2712	0	0	0
T7	2111	3	0	0
T8	3926	6	0	0
T9	3895	14	0	0
T10	53794	87	0	0
T15	0	12	0	0
T16	0	11	0	0

IoStatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24297326	57920	0	0
T1	834	3	0	0
T2	59288	86	0	0
T3	2694	5	0	0
T4	9810	11	0	0
T5	560	3	0	0
T6	2712	5	0	0
T7	2111	4	0	0
T8	3926	7	0	0
T9	3895	16	0	0
T10	53794	88	0	0

MainStatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24297326	52011	0	0
T1	834	1	0	0
T2	59288	85	0	0
T3	2694	4	0	0
T4	9810	10	0	0
T5	560	0	0	0
T6	2712	0	0	0
T7	2111	3	0	0
T8	3926	6	0	0
T9	3895	14	0	0
T10	53794	87	0	0
T15	0	12	0	0
T16	0	11	0	0

MainStatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24297326	57921	0	0
T1	834	3	0	0
T2	59288	86	0	0
T3	2694	5	0	0
T4	9810	11	0	0
T5	560	3	0	0
T6	2712	5	0	0
T7	2111	4	0	0
T8	3926	7	0	0
T9	3895	16	0	0
T10	53794	88	0	0

UsbStatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24297326	35947	0	0
T1	834	1	0	0
T2	59288	45	0	0
T3	2694	4	0	0
T4	9810	6	0	0
T5	560	0	0	0
T6	2712	0	0	0
T7	2111	4	0	0
T8	3926	3	0	0
T9	3895	14	0	0
T10	53794	39	0	0
T15	0	9	0	0
T16	0	12	0	0

UsbStatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24297326	40464	0	0
T1	834	3	0	0
T2	59288	46	0	0
T3	2694	5	0	0
T4	9810	7	0	0
T5	560	3	0	0
T6	2712	5	0	0
T7	2111	4	0	0
T8	3926	3	0	0
T9	3895	16	0	0
T10	53794	39	0	0