Unified Coverage Report :: Module :: pwrmgr_sec_cm_checker_assert

Module : pwrmgr_sec_cm_checker_assert

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_sec_cm_checker_assert	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.pwrmgr_sec_cm_checker_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : pwrmgr_sec_cm_checker_assert

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	42	1	1	100.00
ALWAYS	43	1	1	100.00
ALWAYS	44	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv' or '../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
42	1	1
43	1	1
44	1	1

---

Cond Coverage for Module : pwrmgr_sec_cm_checker_assert

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       42
 EXPRESSION (((!rst_ni)) || disable_sva)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       43
 EXPRESSION (((!rst_esc_ni)) || disable_sva)
             -------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       44
 EXPRESSION (((!rst_slow_ni)) || disable_sva)
             --------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

---

Assert Coverage for Module : pwrmgr_sec_cm_checker_assert

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
EscClkStopEscTimeout_A	24297904	5549	0	0
EscTimeoutStoppedByClReset_A	24297326	3468218	0	0
EscTimeoutTriggersReset_A	4812997	316	0	0
RomAllowActiveState_A	24297326	57546	0	0
RomAllowCheckGoodState_A	24297326	57597	0	0
RomBlockActiveState_A	24297326	30601	0	0
RomBlockCheckGoodState_A	24297326	428488	0	0
RomIntgChkDisFalse_A	24297326	23595103	0	0
RomIntgChkDisTrue_A	24297326	193263	0	0
RstreqChkEsctimeout_A	24297326	4060	0	0
RstreqChkFsmterm_A	24297326	120	0	0
RstreqChkGlbesc_A	24297326	4060	0	0
RstreqChkMainpd_A	24297326	980698	0	0

EscClkStopEscTimeout_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24297904	5549	0	0
T12	15774	272	0	0
T17	1412	0	0	0
T22	175180	0	0	0
T25	69912	0	0	0
T26	16527	0	0	0
T27	1689	0	0	0
T43	3378	0	0	0
T44	5055	0	0	0
T45	4383	0	0	0
T134	0	18	0	0
T154	0	265	0	0
T155	0	32	0	0
T156	0	94	0	0
T157	0	30	0	0
T158	0	15	0	0
T159	0	94	0	0
T160	0	3	0	0
T161	0	258	0	0
T162	3709	0	0	0

EscTimeoutStoppedByClReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24297326	3468218	0	0
T1	834	12	0	0
T2	59288	11239	0	0
T3	2694	153	0	0
T4	9810	2494	0	0
T5	560	0	0	0
T6	2712	54	0	0
T7	2111	48	0	0
T8	3926	906	0	0
T9	3895	444	0	0
T10	53794	9449	0	0
T15	0	10	0	0

EscTimeoutTriggersReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4812997	316	0	0
T1	275	5	0	0
T2	6168	0	0	0
T3	270	0	0	0
T4	1080	0	0	0
T5	374	0	0	0
T6	274	0	0	0
T7	167	0	0	0
T8	792	0	0	0
T9	597	0	0	0
T10	5174	0	0	0
T11	0	2	0	0
T12	0	3	0	0
T85	0	3	0	0
T134	0	2	0	0
T154	0	3	0	0
T155	0	2	0	0
T156	0	3	0	0
T157	0	2	0	0
T163	0	3	0	0

RomAllowActiveState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24297326	57546	0	0
T1	834	3	0	0
T2	59288	86	0	0
T3	2694	5	0	0
T4	9810	11	0	0
T5	560	3	0	0
T6	2712	5	0	0
T7	2111	4	0	0
T8	3926	7	0	0
T9	3895	16	0	0
T10	53794	88	0	0

RomAllowCheckGoodState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24297326	57597	0	0
T1	834	3	0	0
T2	59288	86	0	0
T3	2694	5	0	0
T4	9810	11	0	0
T5	560	3	0	0
T6	2712	5	0	0
T7	2111	4	0	0
T8	3926	7	0	0
T9	3895	16	0	0
T10	53794	88	0	0

RomBlockActiveState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24297326	30601	0	0
T11	2490	0	0	0
T12	15773	0	0	0
T13	6477	0	0	0
T14	1776	263	0	0
T21	53463	0	0	0
T27	0	248	0	0
T28	22482	6	0	0
T40	25604	4	0	0
T41	36060	0	0	0
T42	3813	0	0	0
T44	0	915	0	0
T76	1700	0	0	0
T89	0	96	0	0
T135	0	206	0	0
T139	0	1127	0	0
T164	0	12	0	0
T165	0	619	0	0

RomBlockCheckGoodState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24297326	428488	0	0
T2	59288	4023	0	0
T3	2694	0	0	0
T4	9810	0	0	0
T5	560	0	0	0
T6	2712	0	0	0
T7	2111	0	0	0
T8	3926	0	0	0
T9	3895	0	0	0
T10	53794	4165	0	0
T14	0	90	0	0
T15	2441	0	0	0
T21	0	4072	0	0
T25	0	1261	0	0
T26	0	1322	0	0
T27	0	65	0	0
T28	0	1039	0	0
T40	0	1308	0	0
T41	0	2227	0	0

RomIntgChkDisFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24297326	23595103	0	0
T1	834	656	0	0
T2	59288	59210	0	0
T3	2694	2412	0	0
T4	9810	9758	0	0
T5	560	339	0	0
T6	2712	2327	0	0
T7	2111	2061	0	0
T8	3926	3873	0	0
T9	3895	3774	0	0
T10	53794	53709	0	0

RomIntgChkDisTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24297326	193263	0	0
T12	15773	0	0	0
T14	1776	160	0	0
T17	1412	0	0	0
T25	69911	0	0	0
T26	16526	239	0	0
T27	1689	672	0	0
T42	3813	0	0	0
T43	3378	0	0	0
T44	5055	1478	0	0
T84	0	3055	0	0
T89	0	183	0	0
T91	0	15422	0	0
T139	0	1884	0	0
T162	3708	0	0	0
T164	0	586	0	0
T165	0	156	0	0

RstreqChkEsctimeout_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24297326	4060	0	0
T1	834	1	0	0
T2	59288	0	0	0
T3	2694	0	0	0
T4	9810	0	0	0
T5	560	0	0	0
T6	2712	0	0	0
T7	2111	0	0	0
T8	3926	0	0	0
T9	3895	4	0	0
T10	53794	0	0	0
T11	0	1	0	0
T12	0	1	0	0
T13	0	5	0	0
T14	0	4	0	0
T25	0	17	0	0
T27	0	2	0	0
T42	0	6	0	0
T43	0	7	0	0

RstreqChkFsmterm_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24297326	120	0	0
T18	23106	20	0	0
T19	0	40	0	0
T20	0	20	0	0
T29	0	20	0	0
T30	0	20	0	0
T31	15469	0	0	0
T32	1380	0	0	0
T33	1975	0	0	0
T34	4015	0	0	0
T35	3919	0	0	0
T36	4600	0	0	0
T37	3023	0	0	0
T38	3444	0	0	0
T39	3854	0	0	0

RstreqChkGlbesc_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24297326	4060	0	0
T1	834	1	0	0
T2	59288	0	0	0
T3	2694	0	0	0
T4	9810	0	0	0
T5	560	0	0	0
T6	2712	0	0	0
T7	2111	0	0	0
T8	3926	0	0	0
T9	3895	4	0	0
T10	53794	0	0	0
T11	0	1	0	0
T12	0	1	0	0
T13	0	5	0	0
T14	0	4	0	0
T25	0	17	0	0
T27	0	2	0	0
T42	0	6	0	0
T43	0	7	0	0

RstreqChkMainpd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24297326	980698	0	0
T2	59288	5474	0	0
T3	2694	0	0	0
T4	9810	0	0	0
T5	560	5	0	0
T6	2712	24	0	0
T7	2111	0	0	0
T8	3926	0	0	0
T9	3895	462	0	0
T10	53794	5973	0	0
T13	0	190	0	0
T15	2441	0	0	0
T21	0	4060	0	0
T28	0	1595	0	0
T40	0	1249	0	0
T41	0	3448	0	0